The ISA bus is not well defined and this is one of the biggest problems
with it. But here is what I found on the hardware level based on 286 and
386 stuff.
A write cycle consists of 6 oscillator periods (for a write with 1 wait
state) or 12 with 4 wait states.
Assuming that the ISA bus is operating at 10 MHz (different for each
motherboard) this translates to .6 to 1.2 us for the write cycle on the
bus. A 16 bit to 8 bit will take 24 clocks (10 wait states) where as a 16
to 16 bit takes 6 clocks (1 wait state). 8 to 8 is 12 clocks (4 wait
states). (I hope that I converted the numbers correctly).
New designs could potentially use a faster clock to the isa bus but it is
usually 10 MHz (older systems were 4.77 MHz). The device on the bus
generates the wait states. The timer may generate a wait state or two I do
not know. I suspect that it does not. This would imply (8 to 8) a best case
delay ~1.2 us per access to the timer. We are seeing 2 to 4 us ??? How many
outb calls are made? Is there other activity that can slow this down? The
8254 is newer that the older systems and can operate at a higher clock rate
so I am just guessing that the designers chose to have it able to operate
at 10 MHz ISA bus with 1 wait state. If anyone knows this for sure please
reply.
Please let me know if you agree with my theoretical numbers and why we are
at 2-4 us.
application/ms-tnef
