Paul Koning wrote:
>
> I wonder if people have examined the worst case timing properties of
> PCI... assuming it has any.  Lots of buses have no reasonable or
> defined worst case behavior.
>
>         paul
 
Typical 33 MHz PCI hardware latencies are 10-20 uSec according to an IBM
datasheet.  Add to this any delays caused by the 'readPCI' code running
on the CPU before and after the read.  The PCI 2.1 Specification has two
equations for calculating bus latencies after a device wins arbitration
of the bus:
 
worst case:

  latency (bus clocks) = 16 + 8*(n-1) 
  n = number of 32 bit words transferred
  bus clocks = 1/33 MHz or 1/66 MHz depending on your PCI bus speed.

typical case:

  latency (bus clocks) = 8 + 8*(n-1)

The arbitration latency is:

  m * Latency Timer

  m = number of masters ( max is 8 )
  Latency Timer = typical is 22 bus clocks

 Your total PCI bus delay is the sum of the two latencies.

 - Each device can have a different timer setting.  Check the settings
   of your devices.
 - Some devices can do an endless data transfer without a timer.
 - Normal Linux can start a PCI data transfer that can run into
   a real time Linux interval.
 
Experiment with your system setup.  If you need shorter delays stop
any  unnecessary Linux PCI transfers, and plan the transfers better.

The PCI 2.1 Specification is available for download at:

 http://akulin.npi.msu.su/docs/standard/pci21.pdf

Latencies are covered in section 3.5.

 - Kal.
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