Hi all,
short update on the TDMA-V2 development: I just committed a larger extension of the tdma module which implements the packet delay calibration procedure. I forgot to mention in the checkin log that it also implements the TDMA API device to retrieve the improved global clock offset (yet untested, though). tdmacfg has been finished and can be used to tweak all TDMA parameters now - except the backup master offset as this features is still not implemented in the core. And finally the /proc support has been improved and should provide all required information about the current TDMA configuration.
Some numbers: Between my notebook and an industrial PC I get about 30 us delay averaged over 100 rounds with a 2 ms cycle. This delay expresses the time a minimum sized (!) packet takes between the triggering hardware command on the sender and the time taken in the interrupt handler of the receiver. Larger packets take longer because they first have to be transfered from the NIC into the main memory when DMA is used by the receiver. But as all TDMA control frames are minimum sized, this effect does not matter (it happened that I intuitively designed the protocol correctly although I just realised this tiny difference).
As we already learned about periodic tasks, latencies increase with the scheduling period. This can also be observed with the TDMA calibration. I think it must be the same effect: more cache misses.
Jan
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