Calvin Wong wrote: > I'm getting the following results with vcs. > > @6 clk0 PosEdge seen > @8 clk1 PosEdge seen
I have fixed the +1 delay that occurs in VCS (your results above show that the clock edge was seen by the "processes" at time 6, when in reality, the edge actually occurred at time 5). The concurrency model behaves the same in all simulators now, so you should be seeing the first posedge at time 5, the second at time 7, and so on. On a side note, I've been having a hell of a time getting Modelsim 6.2g (Feb 2007 build) to cooperate with this new concurrency model. It is not handling VPI callbacks consistently because the same tests sometimes pass and sometimes fail. If you have a newer or same version of Modelsim available, please run: rake test SIMULATOR=vsim | grep 'Failure|FAILED' a few times and tell me if it succeeds. I'm tempted to believe this is a problem in Modelsim itself because the tests pass with the other simulators (VCS, NC-Sim, Cver).
