> Actually, what is the timing issue, I don't think I ever really properly > understood it... is it every contended memory access is 4 cycles?
Only (Non ASIC I/O) instructions executed in ROM space are uncontended and use the standard Z80 timings In ram instructions are always aligned to a multiple of 4 Ts. and ASIC IO to multiples of 8Ts When the ASIC needs to draw the screen there is an additional delay of I think 4Ts. With ASIC IO I mean IO instructions using ports 248 to 255 or F8 to FF in hex. Edwin
