>Anyway, almost all instructions are just rounded up to the next multiple
>of 4. A few take 4 extra.  Anyone who tells you that "LD A,7" takes 9.3
>cycles is obviously lying.  :-)

Okay... well, I'm getting the ASIC documentation from Bruce Gordon with the
week (yep, that's right - the full documentation of how the ASIC works, as
done for Maplins when they were interested in buying up Bruce's old
stock)... with a bit of luck, that'll explain it all.

Interesting note: On hacking at the 1Mb board I've got, it uses the CPU CLK
line and the REFRESH line to update the contents of the DRAMs... now,
there's a whopping great GAL on that board... so, what I reckon is that the
CPU CLK line is being used to generate CAS/RAS timing for memory reads, and
the REFRESH line is being used in conjunction with it to produce the
necessary refresh signals...

Anyone got a >6MHz storage scope who can back me up on this one? :)

Other hardware notes (just for amusement factor):
The ASIC is decoupled from the Z80 bus by a bank of 470ohm resistors... and
its bus is tied low. The Z80's bus, however, is tied high... what this means
is that:

1) unfortunately, you can't really read the ASIC's output from the back of
the SAM unless you tristate the Z80 -- and even then, I'm not sure if the
ASIC has enough pulling power to drop the data lines enough.

2) it's possible to override what the Z80 sees when it reads one of the
ASIC's ports... or even when it reads memory.....
soooo.....
Hardware 128k speccy emulator anybody??? :) :) :)

Simon

ps the forthcoming accelerator design may incorporate a ... you guessed it
... 128k spectrum emulator. Neat, huh?
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