Ian Collier wrote: > Not really - it's mostly guesswork, although I did measure a lot of > instructions experimentally. I think Pedro Gimeno did something similar > for the Spectrum and the results are in the cssfaq
I found Pedro's work at lunch-time and it looks like a good starting point. At the weekend I might have a look at adding the delays to (normal RAM) reads and writes, just by rounding up to the next 8 t-states when I think the main display area is being read by the ASIC (not including border). The extra split timings will then need to be added for reads and writes within the various instructions - thankfully a good chunk of the instructions don't access memory! It'll take a lot to get right, but hopfully it'll allow some timing sensitive code (particularly in demos) to be closer to working as expected. Si
