PLEASE REPLY TO [email protected] ONLY
Hello,
I am Baachi working on behalf of Ziplogic LLC. We have an Urgent Opportunity in
Chandler, AZ for SR Design Verification Engineer.
Please review the below need and let us know if you have anyone available and
interested.
Email me a copy of your WORD formatted resume with requirement title.
1. Full Name:
2. Availability:
3. Contact number:
4. Email Id:
5. Current Location:
6. Visa Status(Citizen/G.C/H1B) :
7. Expected Rate:
Requirement Details:
Job Title : SR Design Verification Engineer
Job Type (Contract) : 3 months+
Location : Chandler, AZ
Project Description:
Final phase of design verification, encompassing system level test, compliance
and gate level simulation
Responsibilities:
Ø Develop and debug new tests for chip level traffic
Ø Bring up gate level simulation with and without back-annotated timing
Ø Participate in compliance testing
Necessary Skills (Must Have):
Ø Proficient in System Verilog and random constraint methodology
Ø Strong knowledge of object oriented approach to Design Verification using
System Verilog
Ø Proficient in Synopsys VCS
Ø Proficient in Synopsys VMM
Ø Familiar with DPI calls to and from non-SV constructs
Ø Skilled in gate level simulation
Ø Working knowledge of video encoders/decoders
Ø Familiarity with operation of PLL, DMAs, DDR controllers
Ø Familiarity with PCIe, DDR3, JPEG, H264, I2C and JTAG standards
Ø Self starter, team player
Ø Familiarity with SystemC and TLM2.0
Ø Familiarity with Transaction Level BFMs
Ø Familiarity with Software Simulators
Thanks and Regards
Baachi
Resource Manager,
Direct: 510-250-7616, Alt Ph: 510-250-7617
EFax: 510-578-1309
[email protected]
Yahoo IM: baachi_hr
Gtalk IM: ziplogicbaachi
We help our clients, employees & partners compete and win!
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