Analog Layout - (5-8 YEARS)
Location: Portland, Oregon Duration: 6+ Months JD: This position requires industry experience in analog/ custom digital / Standard cell layout. Good understanding of analog concepts along with experience in layout/Mask design of complex analog circuits is required. Should have worked in Layout of any one of the following is required : Power Management blocks, PLL, PHY, LDO, high performance ADCs, high speed IO’s or Standard cells, integration and taking the block from specification to release. Should have deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc. Should be capable of leading a team and should have experience in leading the team and setting up the pdk environment. Responsibilities will include floor planning, DRC/LVS verification and fix, Reliability Analysis and fix, implementation, handling team, customer interaction, debugging skills, talking to vendors for support and closing. Good communication skills. Hands-on experience with Cadence /Synopsys EDA tools for custom layout. *Thanks & Regards* *AMIT KUMAR* Phone: 609-897-9670 x 4009/2165 Email: *[email protected] <[email protected]>* Gmail:[email protected] Fax: 609-228-5522 Add: 38 Washington Road, Princeton Jn, NJ 08550 [image: sysmind] -- You received this message because you are subscribed to the Google Groups "SAP ABAP" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at http://groups.google.com/group/sap-abap. For more options, visit https://groups.google.com/d/optout.
