HI, *Hope you are doing great, *
Visa independent candidate *(Only USC & GC) * *ROLE: VLSI Tech Lead verification Engineer* *LOCATION:Santa Clara,CA USA* *DURATION: Long Term* *JD-- exp - (9+yrs)* *1- *verification engineers – OVM/UVM is Mandatory 2- CPU subsystem/DDR/Modem verification 3- RTL Design Engineer, 4- with experience on CPU subsystem/DDR/Modem design Best Regards, *Tej Mishra* | SYSMIND, LLc Phone: 609-897-9670 x 2167 Email: [email protected] <[email protected]> Gtalk: tej.sysmind Website: sysmind.com Address: 38 Washington Road, Princeton Junction, NJ 08550 -- You received this message because you are subscribed to the Google Groups "SAP BASIS" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at https://groups.google.com/group/sap-basis. For more options, visit https://groups.google.com/d/optout.
