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*Please reply at **soh...@panzersolutions.com* <soh...@panzersolutions.com> Title : Senior FPGA Engineer Location : San Jose, CA Duration : 4-6 Months Interview : Face 2 Face after telephonic *Must Haves:* 10+ years of high speed PCB and FPGA design (primarily front-end) Mixed Signal (Analog and Digital) experience Some exposure to signal integrity/validation Senior to expert level experience with PCB design tools (examples – Mentor Graphics Viewlogic, Cadence Concept, etc.) Familiar with Verilog and FPGA design flows (Xilinx and Altera) Great communication, team player, able to work well with cross functional teams Exposure to network protocols such as TCP/IP, EIGRP, OSPF, etc. BS degree *Plusses:* background interfacing with customer engineering, marketing and sales teams to understand problems and requirements *Role: * Consultant will be responsible for front-end PCB and FPGA design of mixed signal boards. Will be expected to have proficiency with PCB design tools for schematic capture, and able to conduct signal integrity tests on designs. Responsibilities include board and product level architecture design, writing unit and integration tests for product as well as debugging system level problems. Will be using Verilog for design flows, and expected to interface with cross functional teams such as Customer Engineering, marketing and sales to understand requirements and provide raw materials for training. Regards, *Sohail Khan * <http://www.panzersolutions.com/> -- You received this message because you are subscribed to the Google Groups "SAP BASIS" group. To unsubscribe from this group and stop receiving emails from it, send an email to sap-basis+unsubscr...@googlegroups.com. To post to this group, send email to sap-basis@googlegroups.com. Visit this group at http://groups.google.com/group/sap-basis. For more options, visit https://groups.google.com/groups/opt_out.
