*Please send profiles to [email protected] *
Hi, Please go through the requirement and send your available consultants updated profiles with contact details and rate per hour ASAP. ** *SENIOR/LEAD FPGA DESIGN AND ASIC ENGINEER* Location: Lake Forest Orange County, CA Duration: 6 months *Skills Required * · This individual would be responsible for high speed pipelined FPGA/ASIC (RTL) design. · The position involves direct FPGA design work at RED as well as coordination/help managing outside contractors designing an ASIC for RED. · Candidate must be fluent in VHDL, Verilog and CAD/simulation tools and have prior experience leading a technical group. · System hardware debug and design experience is required. · Real-time video design experience would be a plus but is not absolutely required. -- Regards, Venkat Technical Recruiter 609 945 1186 [email protected] Ezen Computer Services Inc. --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "SAP FI/CO FUNCTIONAL" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.co.in/group/SAP-FICO-FUNCTIONAL?hl=en-GB -~----------~----~----~----~------~----~------~--~---
