*Please revert with resume @ j...@amtechpro.com <j...@amtechpro.com> or call me @ 202-800-8409*
*Title:* Verification Engineer *Location:* Dallas, TX *Duration:* 6 month contract position *Manger Comments:-- “I am looking for a good SystemVerilog testcase developer with strong debug and verification closure skills.”* *REQUIRED:* Must have a minimum of 8 years of relevant experience. Must know SystemVerilog. Must have experience with SystemVerilog based verification for mixed-signal chips. Must have excellent debug skills. Must have experience in doing Functional Fault Simulation. A candidate with any prior experience in Automotive Chip Functional/Safety/Fault Verification will be preferred. *Primary activities *will be verification of complex high speed digital logic with focus on SystemVerilog based Functional Verification for a next generation Automotive Chip. *Primary responsibilities* will include verification planning, test case development, test case debug, coverage analysis, and metric/status reporting and verification closure. -- You received this message because you are subscribed to the Google Groups "SAP-UK" group. To unsubscribe from this group and stop receiving emails from it, send an email to sap-uk+unsubscr...@googlegroups.com. To post to this group, send email to sap-uk@googlegroups.com. Visit this group at https://groups.google.com/group/sap-uk. For more options, visit https://groups.google.com/d/optout.
