This is Amit, working with SysMind. We have the below contract job opportunity with one of our direct clients and would like to check if you have any resources available. Please send across the resume of your consultants along with the contact information at the earliest to [email protected] or call me at 609-897-9670 X2174****
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Role: Pre-Silicon functional verification Engineer****
Experience Level: 4+ Years****
Location: Santa Clara, CA****
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Skill set and experience****
**· **At least 3+ years’ experience in pre-silicon verification****
**· **Expertise in Building scalable HVL based verification
environment from Scratch using System Verilog OVM/UVM****
**· **Good experience in System Verilog – OVM/UVM based verification
environment development****
**· **Sound understanding of Random and constrained
random-verification concepts****
**· **Experience with assertion based verification would be a plus***
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**· **Understanding PCI-E, USB, SATA, DDR3 type protocols would be
a plus ****
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Job Role:****
**· **Driving the verification environment architecture****
**· **Creating test scenarios(System Verilog OVM)****
**· **Work with RTL teams to debug verification failures****
**· **Review and ensure that expected Code and functional coverage
metrics are achieved****
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Regards,****
Amit Sharma****
SysMind LLC****
38 washington Road, Princeton Junction, NJ-08550****
Ph: 609-897-9670 x 2174****
Fax: 609-228-5522****
Email: [email protected]****
[image: SysMind]****
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