Please reply to:- Upadhyay, Priyadarshni / [email protected] / 609-606-9010 Ext.# 1336
Job Details:-
| Job Title : | ASIC Design/Validation Engineer |
| Location : | Sacramento, CA |
| Expected Duration of Project : | 12 Months |
| Start Date : | 08/21/2013 |
| Interview Type : | Telephonic |
| Duties & Responsibilites : | Job Details:-
ASIC Design/Validation Engineer Status: Very Urgent
Industries: IDM/Fabless Semi
Levels: Intermediate / Senior
Type: Contract ~ 6 to 12 mths, extendable
No of positions: 4
Key qualifying skills:
Design/verification experience, along with testbench
Strong Verilog coding alongside SystemVerilog (preferably OVM) experience
Validation experience
Highly desirable: MIPI (Mobile industry processor interface) experience preferable |
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