Hi, Hope you are doing well, My Name is Sam and I am from Enterprise solution, I have a good opportunity for you Please go through the requirement and send me your updated resume and below mentions Details at sham...@enterprisesolutioninc.com
Location: Hillsboro, OR/Santa Clara, CA Duration: 12 months In this position, you will be working as part of a pre-silicon validation team for future microprocessors and/or SoCs and will be responsible for mixed signal validation in the pre-silicon environment. -Functional validation of products with both analog and digital components in them using digital and mixed signal simulation tools -Defining and developing necessary validation infrastructure tests, checkers and occasional scripting in Perl or Unix shell to execute the validation plans to ensure functional correctness of the design -Read and interpret technical specs and create high quality technical documentation -Understanding DUT specifications, digital logic and analog circuit implementation, defining validation strategy, creating test plans -Document validation plan and create appropriate software/content to execute to the plan The ideal candidate should exhibit behavioral traits that indicate: -Strong problem solving -Ability to deal with ambiguity -Effective communication You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work, research and/or relevant previous job and/or internship experiences. Minimum qualifications -Must have either a BS or MS in Electrical Engineering, Computer Engineering or Electrical and Computer Engineering -2yrs experience with basic analog, mixed signal circuits -2yrs experience with digital logic design and simulation using Verilog/VHDL - 1yr experience in developing verification collateral using SVTB based OVM/UVM or Verilog/VHDL - 1yr experience with high speed I/Os like DDR, PCI-express, USB or similar IO interfaces - 6mths experience with computer architecture - 6mths experience with scripting languages like Perl and/or Shell - 6mths experience with circuit simulation tools like Pspice and application of circuit analysis concepts - 2yrs experience with UNIX* or Linux* Preferred qualifications -6mths+ experience with Verilog-A/VHDL-A/AMS and mixed signal simulation tools like Cadence* AMS, Mentor* ADMS and/or their equivalent -6mths+ industry experience in SOC/ASIC verification -6mths+ experience in post-si debug and validation -Working knowledge of C/C++/SystemC and other high level languages *Priority* *Skillset* *Years Experience* 1 Pre-silicon Validation (Design Validation or Digital Validation) 2 years Tool: System Verilog Bonus: Behavioral Modeling 2 Familiar with Analog Circuit 2 years OVM/UVM verification methodology *3* *Mixed Signal Simulation Tool experience* *6 months* *Personal Details of the consultant* Full Name as per Records Best Number to reach Secondary Number Best Time to reach Email Id Rate/hr or Salary per annum Work Authorization Current Location Willing to relocate Current Project Status Availability Notice Period required to start from the date of confirmation Any special Remarks or notes Regards: Sam Enterprise Solutions, Inc. Email : sham...@enterprisesolutioninc.com Contact-Desk-4086933156 Cell-3313052509 www.enterprisesolutioninc.com [image: Description: Description: Description: Description: Description: logo] -- You received this message because you are subscribed to the Google Groups "SAP Workflow" group. To unsubscribe from this group and stop receiving emails from it, send an email to sap-workflow+unsubscr...@googlegroups.com. To post to this group, send email to firstname.lastname@example.org. Visit this group at https://groups.google.com/group/sap-workflow. For more options, visit https://groups.google.com/d/optout.