Hi,
I'm using the sdcc compiler for a z80 embedded fpga core. I don't understand a
few things on the mapping in the crt0.s and perhaps somebody can give an
explanation.
The C program is right now super simple:
sfr at 0x80 led_port;
int main(){
led_port = 0x33;
return 0;
}
I've used the standard crt0.s as startup but when the call to GSINIT is made
the program doesn't work. All code should start from an embedded rom memory
located at 0x0000 to 0x2000 address space. And I make the file with
$(PROGRAM).ihx : $(PROGRAM).c test_crt0.o
$(CC) --no-std-crt0 --codeseg 0x100 --code-loc 0x100 --data-loc 0x410
$^
ihex2rom.py $(PROGRAM).ihx testrom.v
First question: What's the difference between the --codeseg and --code-loc
option?
Second question: If I set the code location to 0x100 I would presume that code
really starts at 0x100, but my mapping file shows:
Hexadecimal
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_GSINIT 0410 0000 = 0. bytes (REL,CON)
Value Global
-------- --------------------------------
0410 gsinit
Hexadecimal
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_0x100 0411 0008 = 8. bytes (REL,CON)
Value Global
-------- --------------------------------
0411 _main
0411 _main_start
0419 _main_end
So the assembler listing of the ld a,#33 out(led_port),a of the c program is
located at 0x410 which is the data segment. Are there any examples or is
there some basic documentation where all this gsinit, gsfinal home, etc. is
explained?
taco walstra
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