The problem: (Answer below)
I've noticed an interesting quirk on the fx2 chip I've been working
with. It seems that some sbits work and some don't.
For instance, EA is an sbit for setting the global interrupt on or off.
I use this all the time and it works correctly.
The assembly for setting EA=1 is:
setb _EA
I recently started working with output port A (sfr IOA and OEA)
my regs file looks like this
sfr at 0xb2 OEA;
sfr at 0x80 IOA;
sbit at 0x80 + 0 PA0;
sbit at 0x80 + 1 PA1;
sbit at 0x80 + 2 PA2;
sbit at 0x80 + 3 PA3;
sbit at 0x80 + 4 PA4;
sbit at 0x80 + 5 PA5;
sbit at 0x80 + 6 PA6;
sbit at 0x80 + 7 PA7;
Instead of setting OEA to 0x08, instead I thought I'd define sbits for
OEA0-7
wbit at 0xb2 + 0 OEA0; // etc
Setting OEA3=1 generates the same assembly that EA=1 generates:
setb _OEA3
The resulting sfr OEA does not change though.
The Answer:
Well, you know how writing an email generally makes you think and look
for an answer while writing.
I just found section 15.2 of the fx2 trm which states that only rows 0
and 8 of table 15-1 (the sfr registers) are bit addressable.
So according to that:
row 0: IOA, IOB, IOC, IOD, SCON1, PSW, ACC, B
row 8: TCON, SCON0, IE, IP, T2CON, IECON, EIE, EIP
can use sbits. All the rest you have to mov a byte to the sfr.
Hm.
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