> I admit to not having looked at the documentation for some time but > could sdcc not have a "reserve" switch. A really powerful option would > be to have the compiler not use a register, or reserve a register set on > on a per arch basis depending on the switch options, this would apply > all the way through (IE compiler and optimiser).
gcc does it with register globals - which are extremely useful on a CPU with a lot of registers, but not otherwise. > I can see lots of problems, push all might get complex as it would > suddenly turn into push all except - or maybe pop all but backup and > restore this register register around it, the mind boggles .... I did look briefly at the code consequences and concluded it was way outside anything I was going to fiddle with in sdcc (I'm still trying to finish debugging 8080 support). > PS I think the compiler should have per op-code clock cycle knowledge > and macros for delays like the powerful but piss poorly documented > CCS-PIC C compilers [#use delay (clock=) and delay_ms macros] sdcc does - within the limits of not knowing the actual memory latencies and wait states, only the CPU timing. On a non wait-stated Z80 it's model is pretty damn good. It does now and then move 16bits between registers with push then pop which seems odd timing wise but I don't have a small demo case for it yet. Alan ------------------------------------------------------------------------------ Dive into the World of Parallel Programming. The Go Parallel Website, sponsored by Intel and developed in partnership with Slashdot Media, is your hub for all things parallel software development, from weekly thought leadership blogs to news, videos, case studies, tutorials and more. Take a look and join the conversation now. http://goparallel.sourceforge.net/ _______________________________________________ Sdcc-user mailing list Sdcc-user@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/sdcc-user
