On 26.08.2015 23:27, Wolle K. wrote: > Derived from ST Micro's workaround 2 (CD00237242.pdf, 1.1.3): > > Expecting a DIV / DIVW instruction in ISR, you can simply insert > > push #0x28 > pop cc > > at the beginning of interrupt handler. > > This is for concurrent interrupt handling only, for nested interrupts, > the interruptability level must be encoded: > > push #0b00<i1>0<i0>000 > pop cc > . > Advantage: 3 bytes of code, 2 execution cycles > Disadvantage: overrides Software priority register settings.
I saw it in the Erratum notes, but I wanted a solution that just works in every situation without the user having to worry about anything. IMO, with rthe recent improvements, the current situation in SDCC is good enough now: We do static code analysis (even some interprocedural one), so that when we can prove that there is no div/divw, we leave out the workaround. The woraround we use for the remaining interrupt handlers is not the one recommended by STM, it is one I found by experimenting on the hardware. The cost by default is 2 bytes of code and 3-4 cycles. When using --opt-code-size, the cost is 1 byte and 2-17 cycles. Philipp
signature.asc
Description: OpenPGP digital signature
------------------------------------------------------------------------------
_______________________________________________ Sdcc-user mailing list Sdcc-user@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/sdcc-user
