Hi, thanks
The MCS51 has the JBC instruction, which tests a bit, jumps if its set
and also clears the bit - all atomically. These would be perfect for
atomic flags. In addition the MCS51 supports an array of XCH
instructions which exchange the full accumulator with a
register/sfr/memory location, and given the wider range of addressing
modes these would be a more useful alternative than the XCHD.
The XCHD instruction swaps the low nibble of the accumulator with the
low nibble of @R0 or @R1. My guess is that this instruction was included
to marginally "optimize" packing/unpacking two BCD or HEX digits in/from
a byte - for instance in a calculator.
The specificity of the XCHD instructions (and a few others) makes me
suspect that it is unlikely that they are produced by a C compiler[*],
though they may be used in handcrafted assembly library routines. If I
were to venture a guess, I would also expect that the SWAP, DA, NOP
instructions will not be produced by a C compiler (and perhaps also not
the RR,RL, RRC and RLC instructions)
regards, Theo
[*]The observation that compilers frequently used few of the
complex/iregular instructions of CISC architectures was also one of the
driving forces behind the development of RISC architectures
On 7/27/21 9:21 PM, Philipp Klaus Krause wrote:
Am 27.07.21 um 19:49 schrieb theo_sd...@borm.org:
Though I guess the XCHD opcodes had some use "back in the day",
I'm not an mcs51 expert, but I think these are the only efficient way to
implement somewhat-useable C11 atomic_flag on MCS-51.
Philipp
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