On 25/04/2022 08:35, Daniel Drotos wrote: > > AN3181 > (https://www.st.com/resource/en/application_note/an3181-guidelines-for-obtaining-ulcsaiec-607301603351-class-b-certification-in-any-stm8-application-stmicroelectronics.pdf) > mentions roll-over on page12, some Lxx types are listed in the table.
I think that's the /only/ place that explicitly states the STM8[A]Lx[56]x has HW stack limits. Neither RM0031 nor the datasheets mention it :-(. Mind you, all the STM8A parts are automotive and (can be coded to be) compliant to ISO 26262 and ASIL B (neither of which I've read :-) ) so it makes sense that range was taped-out using a "hardened" CPU core. Aha! Here's a clue that doesn't involve buying the standards: https://www.eetimes.com/is-your-processor-ip-iso-26262-compliant/2/ ARC EM SEP processors also include the following safety features to support ISO 26262 compliance: * Hardware stack protection that checks overflow and underflow of reserved stack space Now RM0016 gets the bit about stack due to a merge of RM0009 which was the original reference manual for the STM8A family. RM0031 never got that merge even though it covers A parts so should be considered suspect. RM0009 (it's on datasheetarchive.com) predates all the other reference manuals. And AN3181 says the L101 and TL5x has HW limits. So what else is there? I suspect the documentation is just lacking. I've opened a case with STM to query it... Mike
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