Am 12.08.22 um 21:52 schrieb Basil Hussain:
Hi all,
For the STM8 platform, SDCC adds "clr a", "div x, a" instructions as a
prologue to the start of all interrupt service routines (ISRs) in order
to mitigate the published errata "Unexpected DIV/DIVW instruction result
in ISR". However, as far as I know, this workaround is unnecessary when
the code within the ISR does not perform any division instructions.
If SDCC can find out that there is no division in the ISR, it will omit
the workaround. Can you show the code of your ISR here?
Philipp
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