On 13/01/2024 16:30, Philipp Klaus Krause wrote:
idxm a, M reads a byte from an adress; that address does not need to
be a word address. It is a byte address, and both even and odd
addresses work. However, that address itself needs to be located at a
word address (i.e. here p needs to be at an even address, which is
true, since p is always at address 0, but p might hold an odd value,
also the upper byte of that word (i.e. here the byte at address 1)
needs to be 0 for pdk13, pdk14 and pdk15).
Oh, I misunderstood about the word alignment. I did think it rather odd
that the address pointed to needed to be word-aligned when only a single
byte was being read.
sp-1 and sp-2 point to the bytes of the return address for the current
function.
Of course, I forgot about the return address! That's why minus 4...
By the way, one thing I have noticed about SDCC's PDK code generation is
that it seems to prefer "add"-ing a negative number rather than using
the "sub" instruction. Why is that? Do not all PDK instruction sets have
"sub"? I'm pretty certain they do.
sp-3 point to the padding byte that we need to ensure that sp is
always even, sp-4 points to the data byte of the argument.
Are you sure? Won't SP-3 be a copy of the flag register, not padding?
The push af instruction pushes two bytes: the a register and the flag
register.
You mean using that byte at adress 1 in some assembler code? That
could work, but you'd have to reset it back to zero before it is used
by any SDCC-generated code. So you'd have to disable interrupts before
using the byte (and then reeenable them again after zeroing the byte).
Yes, precisely. I hadn't thought about interrupts attempting to use P,
thanks for that tip. So other than that, it's all good?
Regards,
Basil Hussain
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