Op dinsdag 06-03-2012 om 22:25 uur [tijdzone -0500], schreef Kevin
O'Connor:
> You could try, dumping the value of cntl->regs->periodicstart and
> cntl->regs->fminterval at the end of start_ohci() to see if there's
> something odd there.
>
> You could also try setting the Skip bit in ohci_alloc_intr_pipe
> (ed->hwINFO |= ED_SKIP) to see if the issue is with the TDs or EDs.
> You could also try replacing malloc_low calls with malloc_high calls
> in ohci_alloc_intr_pipe to see if maybe the controller doesn't like
> the memory addresses.
Ok now i have some results!
With the original ohci pipe free fix and the 3 malloc's changed to
malloc_high the controller seems to keep running. :)
There is probably also another problem.(see attached log)
While booting i did not touch the keyboard, but it received (partly
unknown) keycodes.
At the end of the log SeaBIOS crashed.
This sequence is reproducible at every boot.
When i unplug the keyboard then boot and then plug in again after
SeaBIOS finished, then linux runs fine.
Thanks, Nils.
======= Wed Mar 7 22:31:46 2012 (adjust=0.0us)
00.000: <00>
00.352:
00.352:
00.352: coreboot-4.0-1975-g1b785c7-v1975_559 Wed Mar 7 22:14:05 CET 2012 starting...
00.376: POST: 0xa0
00.385: POST: 0xa1
00.516:
00.516:
00.520: coreboot-4.0-1975-g1b785c7-v1975_559 Wed Mar 7 22:14:05 CET 2012 starting...
00.536: done cpuRegInit
00.544: Ram1.00
00.549: Ram2.00
00.549: sdram_set_spd_register
00.556: POST: 0x70
00.560: Check DIMM 0
00.564: Check DIMM 1
00.568: POST: 0x72
00.572: Check DDR MAX
00.576: POST: 0x73
00.584: AUTOSIZE DIMM 0
00.584: Check present
00.588: MODBANKS
00.592: FIELDBANKS
00.596: SPDNUMROWS
00.604: SPDBANKDENSITY
00.608: DIMMSIZE
00.612: BEFORT CTZ
00.612: TEST DIMM SIZE>7
00.616: PAGESIZE
00.620: MAXCOLADDR
00.624: >11address test
00.628: RDMSR CF07
00.628: WRMSR CF07
00.632: ALL DONE
00.636: POST: 0x74
00.640: AUTOSIZE DIMM 1
00.640: Check present
00.644: set cas latency
00.652: POST: 0x75
00.660: set all latency
00.668: MSR MC_CF8F_DATA (20000019) value is 18000108:296332a3
00.684: set emrs
00.688: set ref rate
00.692: Ram3
00.696: sdram_enable step 2
00.700: sdram_enable step 3
00.704: sdram_enable step 4
00.708: sdram_enable step 6
00.712: sdram_enable step 7
00.720: sdram_enable step 8
00.728: RAM DLL lock
00.732: Ram4
00.732: ram setup done
00.736: Loading image.
00.740: Searching for fallback/coreboot_ram
00.744: Check fallback/romstage
00.748: Check fallback/coreboot_ram
00.748: Stage: loading fallback/coreboot_ram @ 0x100000 (114688 bytes), entry @ 0x100000
00.832: Stage: done loading.
00.836: Jumping to image.
00.836: POST: 0x80
00.836: POST: 0x39
00.840: coreboot-4.0-1975-g1b785c7-v1975_559 Wed Mar 7 22:14:05 CET 2012 booting...
00.844: POST: 0x40
00.848: clocks_per_usec: 366
00.852: Enumerating buses...
00.852: Show all devs...Before device enumeration.
00.856: Root Device: enabled 1
00.863: PCI_DOMAIN: 0000: enabled 1
00.863: PCI: 00:01.0: enabled 1
00.863: PCI: 00:01.1: enabled 1
00.868: PCI: 00:0e.0: enabled 1
00.868: PCI: 00:0f.0: enabled 1
00.868: PCI: 00:0f.2: enabled 1
00.872: PCI: 00:0f.3: enabled 1
00.876: PCI: 00:0f.4: enabled 1
00.876: PCI: 00:0f.5: enabled 1
00.880: APIC_CLUSTER: 0: enabled 1
00.880: APIC: 00: enabled 1
00.884: Compare with tree...
00.884: Root Device: enabled 1
00.888: PCI_DOMAIN: 0000: enabled 1
00.888: PCI: 00:01.0: enabled 1
00.895: PCI: 00:01.1: enabled 1
00.895: PCI: 00:0e.0: enabled 1
00.895: PCI: 00:0f.0: enabled 1
00.900: PCI: 00:0f.2: enabled 1
00.900: PCI: 00:0f.3: enabled 1
00.904: PCI: 00:0f.4: enabled 1
00.904: PCI: 00:0f.5: enabled 1
00.908: APIC_CLUSTER: 0: enabled 1
00.912: APIC: 00: enabled 1
00.912: scan_static_bus for Root Device
00.916: >> Entering northbridge.c: enable_dev with path 6
00.920: >> Entering northbridge.c: pci_domain_enable
00.924: Enter northbridge_init_early
00.928: writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80
00.932: writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0
00.936: sizeram: _MSR MC_CF07_DATA: 10077113:00003500
00.940: sizeram: sizem 0x200
00.944: SysmemInit: enable for 512MBytes
00.944: SysmemInit: MSR 0x10000028, val 0x2000001f:0xfdf00100
00.952: sizeram: _MSR MC_CF07_DATA: 10077113:00003500
00.956: sizeram: sizem 0x200
00.956: SMMGL0Init: 536739840 bytes
00.960: SMMGL0Init: offset is 0x40400000
00.960: SMMGL0Init: MSR 0x10000026, val 0x2dfbe040:0x400fffe0
00.968: writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003
00.972: writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80
00.976: writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0
00.980: sizeram: _MSR MC_CF07_DATA: 10077113:00003500
00.984: sizeram: sizem 0x200
00.988: SysmemInit: enable for 512MBytes
00.988: SysmemInit: MSR 0x40000029, val 0x2000001f:0xfdf00100
00.996: SMMGL1Init:
00.996: SMMGL1Init: MSR 0x40000023, val 0x20000040:0x400fffe0
01.000: writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001
01.004: writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0
01.012: CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x11FFDF00
01.016: CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000
01.020: POST: 0x60
01.020: Enabling cache
01.020: GLPCI R1: system msr.lo 0x00100130 msr.hi 0x1ffdf000
01.024: GLPCI R2: system msr.lo 0x40400120 msr.hi 0x4041f000
01.032: Exit northbridge_init_early
01.032: Doing cpubug fixes for rev 0x21
01.036: CPU_BUG:eng2900
01.036: Done cpubug fixes
01.040: POST: 0xe0
01.040: Not Doing ChipsetFlashSetup()
01.044: ---------- CPU ------------
01.048: MSR 0x00001700 is now 0x00000000:0x00100000
01.052: MSR 0x00001800 is now 0x00002000:0x00000022
01.052: MSR 0x00001808 is now 0x25FFFC02:0x11FFDF00
01.056: MSR 0x0000180A is now 0x00000000:0x00000000
01.060: MSR 0x0000180B is now 0x21212121:0x21212121
01.064: MSR 0x0000180C is now 0x21212121:0x21212121
01.068: MSR 0x0000180D is now 0x21212121:0x21212121
01.072: MSR 0x0000180E is now 0x00000001:0x00000001
01.076: MSR 0x0000180F is now 0x00000001:0x00000001
01.080: MSR 0x4C00000F is now 0x830D415A:0x8EA0AD6A
01.084: ---------- GLIU 0 ------------
01.088: MSR 0x10000020 is now 0x20000000:0x000FFF80
01.092: MSR 0x10000021 is now 0x20000000:0x080FFFE0
01.096: MSR 0x10000022 is now 0x000000FF:0xFFF00000
01.100: MSR 0x10000023 is now 0x000000FF:0xFFF00000
01.104: MSR 0x10000024 is now 0x000000FF:0xFFF00000
01.108: MSR 0x10000025 is now 0x000000FF:0xFFF00000
01.112: MSR 0x10000026 is now 0x2DFBE040:0x400FFFE0
01.116: MSR 0x10000027 is now 0x000000FF:0xFFF00000
01.120: MSR 0x10000028 is now 0x2000001F:0xFDF00100
01.124: MSR 0x10000029 is now 0x00000000:0x000FFFFF
01.128: MSR 0x1000002A is now 0x00000000:0x000FFFFF
01.132: MSR 0x1000002B is now 0x00000000:0x000FFFFF
01.136: MSR 0x1000002C is now 0x2000FFFF:0xFFFF0003
01.140: MSR 0x100000E0 is now 0x000000FF:0xFFF00000
01.144: MSR 0x100000E1 is now 0x000000FF:0xFFF00000
01.148: MSR 0x100000E2 is now 0x000000FF:0xFFF00000
01.152: MSR 0x100000E3 is now 0x00000000:0x00000000
01.156: MSR 0x100000E4 is now 0x00000000:0x00000000
01.160: MSR 0x100000E5 is now 0x00000000:0x00000000
01.164: MSR 0x100000E6 is now 0x00000000:0x00000000
01.168: MSR 0x100000E7 is now 0x00000000:0x00000000
01.172: MSR 0x100000E8 is now 0x00000000:0x00000000
01.176: MSR 0x10000080 is now 0x00000000:0x00000003
01.180: ---------- GLIU 1 ------------
01.180: MSR 0x40000020 is now 0x20000000:0x000FFF80
01.184: MSR 0x40000021 is now 0x20000000:0x080FFFE0
01.188: MSR 0x40000022 is now 0x000000FF:0xFFF00000
01.192: MSR 0x40000023 is now 0x20000040:0x400FFFE0
01.196: MSR 0x40000024 is now 0x000000FF:0xFFF00000
01.200: MSR 0x40000025 is now 0x000000FF:0xFFF00000
01.204: MSR 0x40000026 is now 0x000000FF:0xFFF00000
01.208: MSR 0x40000027 is now 0x000000FF:0xFFF00000
01.212: MSR 0x40000028 is now 0x000000FF:0xFFF00000
01.216: MSR 0x40000029 is now 0x2000001F:0xFDF00100
01.220: MSR 0x4000002A is now 0x00000000:0x000FFFFF
01.224: MSR 0x4000002B is now 0x00000000:0x000FFFFF
01.228: MSR 0x4000002C is now 0x00000000:0x000FFFFF
01.232: MSR 0x4000002D is now 0x2000FFFF:0xFFFF0003
01.236: MSR 0x400000E0 is now 0x000000FF:0xFFF00000
01.240: MSR 0x400000E1 is now 0x000000FF:0xFFF00000
01.244: MSR 0x400000E2 is now 0x000000FF:0xFFF00000
01.248: MSR 0x400000E3 is now 0x60000000:0x033000F0
01.254: MSR 0x400000E4 is now 0x00000000:0x00000000
01.254: MSR 0x400000E5 is now 0x00000000:0x00000000
01.260: MSR 0x400000E6 is now 0x00000000:0x00000000
01.264: MSR 0x400000E7 is now 0x00000000:0x00000000
01.268: MSR 0x400000E8 is now 0x00000000:0x00000000
01.272: MSR 0x40000080 is now 0x00000000:0x00000001
01.276: ---------- RCONF ------------
01.276: MSR 0x00001810 is now 0x00000000:0x00000000
01.280: MSR 0x00001811 is now 0x00000000:0x00000000
01.284: MSR 0x00001812 is now 0x00000000:0x00000000
01.288: MSR 0x00001813 is now 0x00000000:0x00000000
01.292: MSR 0x00001814 is now 0x00000000:0x00000000
01.296: MSR 0x00001815 is now 0x00000000:0x00000000
01.300: MSR 0x00001816 is now 0x00000000:0x00000000
01.304: MSR 0x00001817 is now 0x00000000:0x00000000
01.308: ---------- VARIA ------------
01.312: MSR 0x51300010 is now 0x00000000:0x00000000
01.316: MSR 0x51400014 is now 0x00000000:0x04070003
01.320: MSR 0x51400015 is now 0x00000000:0x00000071
01.324: ---------- PCI ------------
01.328: MSR 0x50002010 is now 0xFFF030F8:0x001A0215
01.328: MSR 0x50002011 is now 0x00000300:0x00000100
01.332: MSR 0x50002014 is now 0x00000000:0x00FFFF00
01.336: MSR 0x50002015 is now 0x35353535:0x35353535
01.340: MSR 0x50002016 is now 0x35353535:0x35353535
01.344: MSR 0x50002017 is now 0x35353535:0x35353535
01.348: MSR 0x50002018 is now 0x0009F000:0x00000130
01.352: MSR 0x50002019 is now 0x1FFDF000:0x00100130
01.356: MSR 0x5000201A is now 0x4041F000:0x40400120
01.360: MSR 0x5000201B is now 0x00000000:0x00000000
01.364: MSR 0x5000201E is now 0x00000000:0x00000F00
01.368: MSR 0x5000201F is now 0x00000000:0x0000006B
01.372: ---------- LPC/UART DMA ------------
01.376: MSR 0x51400040 is now 0x00000000:0x00000000
01.380: MSR 0x51400041 is now 0x00000000:0x0000007C
01.384: MSR 0x51400042 is now 0x00000000:0x000000FD
01.388: MSR 0x51400043 is now 0x00000000:0x000000FE
01.392: MSR 0x51400044 is now 0x00000000:0x000000FF
01.396: MSR 0x51400045 is now 0x00000000:0x00000038
01.400: MSR 0x51400046 is now 0x00000000:0x000000BD
01.404: MSR 0x51400047 is now 0x00000000:0x000000F6
01.408: MSR 0x51400048 is now 0x00000000:0x0000007F
01.412: MSR 0x51400049 is now 0x00000000:0x000000FF
01.416: ---------- DIVIL IRQ ------------
01.420: MSR 0x51400020 is now 0x00000000:0x00000000
01.424: MSR 0x51400021 is now 0x00000000:0x00000000
01.428: MSR 0x51400022 is now 0x00000000:0x00000000
01.432: MSR 0x51400023 is now 0x00000000:0x00000000
01.436: MSR 0x51400024 is now 0x00000000:0x0000FFFF
01.440: ---------- DIVIL LBAR -----------
01.440: MSR 0x5140000C is now 0x0000F001:0x00006100
01.444: MSR 0x51400010 is now 0x00000000:0x00000000
01.448: MSR 0x51400011 is now 0x00000000:0x00000000
01.452: IOR 0x00006120 is now 0x3DFBC204
01.456: IOR 0x00006138 is now 0xFFFFFFFF
01.460: IOR 0x00006124 is now 0xFFFFFFFF
01.460: IOR 0x000061E0 is now 0xFFFFFFFF
01.464: Preparing for VSA...
01.468: VSA: Real mode stub @00000600: 862 bytes
01.472: Searching for vsa
01.472: Check fallback/romstage
01.476: Check fallback/coreboot_ram
01.476: Check fallback/payload
01.480: Check vsa
01.480: Stage: loading vsa @ 0x60000 (57368 bytes), entry @ 0x60020
01.584: Stage: done loading.
01.584: VSA: Buffer @00060000 *[0k]=ba
01.588: VSA: Signature *[0x20-0x23] is b0:10:e6:80
01.592: Calling VSA module...
01.596: ... VSA module returned.
01.600: VSM: VSA2 VR signature verified.
01.600: Graphics init...
01.604: VRC_VG value: 0x0810
01.604: Finding PCI configuration type.
01.608: PCI: Using configuration type 1
01.612: POST: 0x5f
01.612: PCI_DOMAIN: 0000 enabled
01.616: >> Entering northbridge.c: enable_dev with path 7
01.620: APIC_CLUSTER: 0 enabled
01.620: PCI_DOMAIN: 0000 scanning...
01.624: PCI: pci_scan_bus for bus 00
01.628: POST: 0x24
01.628: >> Entering northbridge.c: enable_dev with path 2
01.632: PCI: 00:01.0 [100b/0028] ops
01.636: PCI: 00:01.0 [100b/0028] enabled
01.636: >> Entering northbridge.c: enable_dev with path 2
01.644: PCI: 00:01.1 [100b/0030] enabled
01.644: cs5536: southbridge_enable: dev is 0010ef1c
01.648: PCI: 00:0e.0 [10ec/8139] enabled
01.652: cs5536: southbridge_enable: dev is 0010ef64
01.665: PCI: 00:0f.0 [1022/2090] bus ops
01.665: PCI: 00:0f.0 [1022/2090] enabled
01.665: cs5536: southbridge_enable: dev is 0010efac
01.665: PCI: 00:0f.2 [1022/209a] ops
01.668: PCI: 00:0f.2 [1022/209a] enabled
01.672: cs5536: southbridge_enable: dev is 0010eff4
01.676: PCI: 00:0f.3 [1022/2093] enabled
01.680: cs5536: southbridge_enable: dev is 0010f03c
01.684: PCI: 00:0f.4 [1022/2094] enabled
01.684: cs5536: southbridge_enable: dev is 0010f084
01.688: PCI: 00:0f.5 [1022/2095] enabled
01.692: PCI: 00:0f.6 [1022/2096] enabled
01.696: PCI: 00:0f.7 [1022/2097] enabled
01.700: POST: 0x25
01.700: scan_static_bus for PCI: 00:0f.0
01.704: scan_static_bus for PCI: 00:0f.0 done
01.708: PCI: pci_scan_bus returning with max=000
01.708: POST: 0x55
01.712: scan_static_bus for Root Device done
01.716: done
01.716: POST: 0x66
01.716: Setting up VGA for PCI: 00:01.1
01.720: Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
01.724: Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
01.728: Allocating resources...
01.732: Reading resources...
01.732: Root Device read_resources bus 0 link: 0
01.736: PCI_DOMAIN: 0000 read_resources bus 0 link: 0
01.752: PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
01.756: APIC_CLUSTER: 0 read_resources bus 0 link: 0
01.760: APIC: 00 missing read_resources
01.764: APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
01.768: Root Device read_resources bus 0 link: 0 done
01.772: Done reading resources.
01.776: Show resources in subtree (Root Device)...After reading.
01.780: Root Device child on link 0 PCI_DOMAIN: 0000
01.784: PCI_DOMAIN: 0000 child on link 0 PCI: 00:01.0
01.788: PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
01.796: PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
01.804: PCI: 00:01.0
01.808: PCI: 00:01.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 10
01.816: PCI: 00:01.1
01.816: PCI: 00:01.1 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
01.824: PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14
01.832: PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 18
01.840: PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
01.848: PCI: 00:0e.0
01.852: PCI: 00:0e.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
01.856: PCI: 00:0e.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14
01.864: PCI: 00:0f.0
01.868: PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
01.876: PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
01.880: PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 18
01.888: PCI: 00:0f.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 1c
01.896: PCI: 00:0f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 20
01.904: PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24
01.912: PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
01.920: PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
01.928: PCI: 00:0f.2
01.932: PCI: 00:0f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
01.936: PCI: 00:0f.3
01.940: PCI: 00:0f.3 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10
01.948: PCI: 00:0f.4
01.948: PCI: 00:0f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
01.956: PCI: 00:0f.5
01.956: PCI: 00:0f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
01.964: PCI: 00:0f.6
01.968: PCI: 00:0f.6 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
01.976: PCI: 00:0f.7
01.976: PCI: 00:0f.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
01.984: APIC_CLUSTER: 0 child on link 0 APIC: 00
01.988: APIC: 00
01.992: PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
01.996: PCI: 00:0e.0 10 * [0x0 - 0xff] io
02.000: PCI: 00:0f.0 14 * [0x400 - 0x4ff] io
02.004: PCI: 00:0f.0 20 * [0x800 - 0x87f] io
02.008: PCI: 00:0f.3 10 * [0x880 - 0x8ff] io
02.012: PCI: 00:0f.0 18 * [0xc00 - 0xc3f] io
02.016: PCI: 00:0f.0 24 * [0xc40 - 0xc7f] io
02.016: PCI: 00:0f.0 1c * [0xc80 - 0xc9f] io
02.020: PCI: 00:0f.2 20 * [0xca0 - 0xcaf] io
02.024: PCI: 00:0f.0 10 * [0xcb0 - 0xcb7] io
02.028: PCI: 00:01.0 10 * [0xcb8 - 0xcbb] io
02.032: PCI_DOMAIN: 0000 compute_resources_io: base: cbc size: cbc align: 8 gran: 0 limit: ffff done
02.038: PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
02.048: PCI: 00:01.1 10 * [0x0 - 0xffffff] mem
02.052: PCI: 00:01.1 14 * [0x1000000 - 0x1003fff] mem
02.056: PCI: 00:01.1 18 * [0x1004000 - 0x1007fff] mem
02.060: PCI: 00:01.1 1c * [0x1008000 - 0x100bfff] mem
02.064: PCI: 00:0f.6 10 * [0x100c000 - 0x100dfff] mem
02.068: PCI: 00:0f.4 10 * [0x100e000 - 0x100efff] mem
02.072: PCI: 00:0f.5 10 * [0x100f000 - 0x100ffff] mem
02.076: PCI: 00:0f.7 10 * [0x1010000 - 0x1010fff] mem
02.080: PCI: 00:0e.0 14 * [0x1011000 - 0x10110ff] mem
02.084: PCI_DOMAIN: 0000 compute_resources_mem: base: 1011100 size: 1011100 align: 24 gran: 0 limit: ffffffff done
02.092: avoid_fixed_resources: PCI_DOMAIN: 0000
02.096: avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
02.104: avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
02.108: constrain_resources: PCI_DOMAIN: 0000
02.112: constrain_resources: PCI: 00:01.0
02.116: constrain_resources: PCI: 00:01.1
02.120: constrain_resources: PCI: 00:0e.0
02.120: constrain_resources: PCI: 00:0f.0
02.124: constrain_resources: PCI: 00:0f.2
02.128: constrain_resources: PCI: 00:0f.3
02.128: constrain_resources: PCI: 00:0f.4
02.132: constrain_resources: PCI: 00:0f.5
02.136: constrain_resources: PCI: 00:0f.6
02.140: constrain_resources: PCI: 00:0f.7
02.144: avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
02.148: <09>lim->base 00001000 lim->limit 0000ffff
02.152: avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
02.156: <09>lim->base 00000000 lim->limit febfffff
02.160: Setting resources...
02.164: PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:cbc align:8 gran:0 limit:ffff
02.172: Assigned: PCI: 00:0e.0 10 * [0x1000 - 0x10ff] io
02.176: Assigned: PCI: 00:0f.0 14 * [0x1400 - 0x14ff] io
02.180: Assigned: PCI: 00:0f.0 20 * [0x1800 - 0x187f] io
02.184: Assigned: PCI: 00:0f.3 10 * [0x1880 - 0x18ff] io
02.188: Assigned: PCI: 00:0f.0 18 * [0x1c00 - 0x1c3f] io
02.192: Assigned: PCI: 00:0f.0 24 * [0x1c40 - 0x1c7f] io
02.196: Assigned: PCI: 00:0f.0 1c * [0x1c80 - 0x1c9f] io
02.200: Assigned: PCI: 00:0f.2 20 * [0x1ca0 - 0x1caf] io
02.208: Assigned: PCI: 00:0f.0 10 * [0x1cb0 - 0x1cb7] io
02.212: Assigned: PCI: 00:01.0 10 * [0x1cb8 - 0x1cbb] io
02.216: PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1cbc size: cbc align: 8 gran: 0 done
02.224: PCI_DOMAIN: 0000 allocate_resources_mem: base:fd000000 size:1011100 align:24 gran:0 limit:febfffff
02.232: Assigned: PCI: 00:01.1 10 * [0xfd000000 - 0xfdffffff] mem
02.236: Assigned: PCI: 00:01.1 14 * [0xfe000000 - 0xfe003fff] mem
02.244: Assigned: PCI: 00:01.1 18 * [0xfe004000 - 0xfe007fff] mem
02.248: Assigned: PCI: 00:01.1 1c * [0xfe008000 - 0xfe00bfff] mem
02.252: Assigned: PCI: 00:0f.6 10 * [0xfe00c000 - 0xfe00dfff] mem
02.256: Assigned: PCI: 00:0f.4 10 * [0xfe00e000 - 0xfe00efff] mem
02.264: Assigned: PCI: 00:0f.5 10 * [0xfe00f000 - 0xfe00ffff] mem
02.268: Assigned: PCI: 00:0f.7 10 * [0xfe010000 - 0xfe010fff] mem
02.272: Assigned: PCI: 00:0e.0 14 * [0xfe011000 - 0xfe0110ff] mem
02.280: PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe011100 size: 1011100 align: 24 gran: 0 done
02.288: Root Device assign_resources, bus 0 link: 0
02.292: >> Entering northbridge.c: pci_domain_set_resources
02.296: PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
02.300: PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 mem
02.308: PCI: 00:01.1 14 <- [0x00fe000000 - 0x00fe003fff] size 0x00004000 gran 0x0e mem
02.316: PCI: 00:01.1 18 <- [0x00fe004000 - 0x00fe007fff] size 0x00004000 gran 0x0e mem
02.320: PCI: 00:01.1 1c <- [0x00fe008000 - 0x00fe00bfff] size 0x00004000 gran 0x0e mem
02.328: PCI: 00:0e.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
02.336: PCI: 00:0e.0 14 <- [0x00fe011000 - 0x00fe0110ff] size 0x00000100 gran 0x08 mem
02.344: PCI: 00:0f.0 10 <- [0x0000001cb0 - 0x0000001cb7] size 0x00000008 gran 0x03 io
02.348: PCI: 00:0f.0 14 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
02.356: PCI: 00:0f.0 18 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
02.364: PCI: 00:0f.0 1c <- [0x0000001c80 - 0x0000001c9f] size 0x00000020 gran 0x05 io
02.368: PCI: 00:0f.0 20 <- [0x0000001800 - 0x000000187f] size 0x00000080 gran 0x07 io
02.376: PCI: 00:0f.0 24 <- [0x0000001c40 - 0x0000001c7f] size 0x00000040 gran 0x06 io
02.384: PCI: 00:0f.2 20 <- [0x0000001ca0 - 0x0000001caf] size 0x00000010 gran 0x04 io
02.392: PCI: 00:0f.3 10 <- [0x0000001880 - 0x00000018ff] size 0x00000080 gran 0x07 io
02.396: PCI: 00:0f.4 10 <- [0x00fe00e000 - 0x00fe00efff] size 0x00001000 gran 0x0c mem
02.404: PCI: 00:0f.5 10 <- [0x00fe00f000 - 0x00fe00ffff] size 0x00001000 gran 0x0c mem
02.412: PCI: 00:0f.6 10 <- [0x00fe00c000 - 0x00fe00dfff] size 0x00002000 gran 0x0d mem
02.420: PCI: 00:0f.7 10 <- [0x00fe010000 - 0x00fe010fff] size 0x00001000 gran 0x0c mem
02.428: PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
02.432: Root Device assign_resources, bus 0 link: 0
02.436: Done setting resources.
02.436: Show resources in subtree (Root Device)...After assigning values.
02.444: Root Device child on link 0 PCI_DOMAIN: 0000
02.448: PCI_DOMAIN: 0000 child on link 0 PCI: 00:01.0
02.452: PCI_DOMAIN: 0000 resource base 1000 size cbc align 8 gran 0 limit ffff flags 40040100 index 10000000
02.458: PCI_DOMAIN: 0000 resource base fd000000 size 1011100 align 24 gran 0 limit febfffff flags 40040200 index 10000100
02.468: PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
02.480: PCI_DOMAIN: 0000 resource base c0000 size 1f720000 align 0 gran 0 limit 0 flags e0004200 index b
02.488: PCI: 00:01.0
02.488: PCI: 00:01.0 resource base 1cb8 size 4 align 2 gran 2 limit ffff flags 40000100 index 10
02.496: PCI: 00:01.1
02.496: PCI: 00:01.1 resource base fd000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10
02.508: PCI: 00:01.1 resource base fe000000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 14
02.516: PCI: 00:01.1 resource base fe004000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 18
02.524: PCI: 00:01.1 resource base fe008000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 1c
02.536: PCI: 00:0e.0
02.536: PCI: 00:0e.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
02.544: PCI: 00:0e.0 resource base fe011000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14
02.552: PCI: 00:0f.0
02.556: PCI: 00:0f.0 resource base 1cb0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
02.564: PCI: 00:0f.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
02.572: PCI: 00:0f.0 resource base 1c00 size 40 align 6 gran 6 limit ffff flags 60000100 index 18
02.580: PCI: 00:0f.0 resource base 1c80 size 20 align 5 gran 5 limit ffff flags 60000100 index 1c
02.588: PCI: 00:0f.0 resource base 1800 size 80 align 7 gran 7 limit ffff flags 60000100 index 20
02.596: PCI: 00:0f.0 resource base 1c40 size 40 align 6 gran 6 limit ffff flags 60000100 index 24
02.604: PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
02.612: PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
02.620: PCI: 00:0f.2
02.620: PCI: 00:0f.2 resource base 1ca0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
02.632: PCI: 00:0f.3
02.632: PCI: 00:0f.3 resource base 1880 size 80 align 7 gran 7 limit ffff flags 60000100 index 10
02.640: PCI: 00:0f.4
02.640: PCI: 00:0f.4 resource base fe00e000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
02.652: PCI: 00:0f.5
02.652: PCI: 00:0f.5 resource base fe00f000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
02.660: PCI: 00:0f.6
02.664: PCI: 00:0f.6 resource base fe00c000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 10
02.672: PCI: 00:0f.7
02.672: PCI: 00:0f.7 resource base fe010000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
02.684: APIC_CLUSTER: 0 child on link 0 APIC: 00
02.688: APIC: 00
02.688: Done allocating resources.
02.692: POST: 0x88
02.692: Enabling resources...
02.692: PCI: 00:01.0 cmd <- 05
02.696: PCI: 00:01.1 subsystem <- 0000/0000
02.700: PCI: 00:01.1 cmd <- 03
02.700: PCI: 00:0e.0 subsystem <- 0000/0000
02.704: PCI: 00:0e.0 cmd <- 03
02.708: PCI: 00:0f.0 cmd <- 09
02.708: PCI: 00:0f.2 cmd <- 01
02.712: PCI: 00:0f.3 subsystem <- 0000/0000
02.712: PCI: 00:0f.3 cmd <- 01
02.716: PCI: 00:0f.4 subsystem <- 0000/0000
02.720: PCI: 00:0f.4 cmd <- 02
02.720: PCI: 00:0f.5 subsystem <- 0000/0000
02.724: PCI: 00:0f.5 cmd <- 02
02.728: PCI: 00:0f.6 cmd <- 02
02.728: PCI: 00:0f.7 cmd <- 02
02.732: done.
02.732: Initializing devices...
02.732: Root Device init
02.736: S50 ENTER init
02.736: S50 EXIT init
02.740: APIC_CLUSTER: 0 init
02.740: >> Entering northbridge.c: cpu_bus_init
02.744: Initializing CPU #0
02.744: CPU: vendor NSC device 552
02.748: CPU: family 05, model 05, stepping 02
02.752: model_gx2_init
02.752: POST: 0x60
02.752: Enabling cache
02.756: model_gx2_init DONE
02.756: CPU #0 initialized
02.760: PCI: 00:01.0 init
02.760: >> Entering northbridge: northbridge_init()
02.764: PCI: 00:01.1 init
02.768: PCI: 00:0e.0 init
02.768: PCI: 00:0f.0 init
02.768: cs5536: southbridge_init
02.772: RTC Init
02.772: GPIO_ADDR: 00001400
02.776: uarts_init: enable COM1
02.776: uarts_init: disable COM2
02.780: cs5536: southbridge_init: enable_ide_nand_flash is 0
02.784: PCI: 00:0f.2 init
02.784: cs5536_ide: ide_init
02.788: PCI: 00:0f.3 init
02.788: PCI: 00:0f.4 init
02.792: PCI: 00:0f.5 init
02.792: PCI: 00:0f.6 init
02.796: PCI: 00:0f.7 init
02.796: Devices initialized
02.800: Show all devs...After init.
02.800: Root Device: enabled 1
02.804: PCI_DOMAIN: 0000: enabled 1
02.804: PCI: 00:01.0: enabled 1
02.808: PCI: 00:01.1: enabled 1
02.808: PCI: 00:0e.0: enabled 1
02.812: PCI: 00:0f.0: enabled 1
02.812: PCI: 00:0f.2: enabled 1
02.816: PCI: 00:0f.3: enabled 1
02.820: PCI: 00:0f.4: enabled 1
02.820: PCI: 00:0f.5: enabled 1
02.824: APIC_CLUSTER: 0: enabled 1
02.824: APIC: 00: enabled 1
02.828: PCI: 00:0f.6: enabled 1
02.828: PCI: 00:0f.7: enabled 1
02.832: CPU: 00: enabled 1
02.832: POST: 0x89
02.836: Initializing CBMEM area to 0x1f7d0000 (65536 bytes)
02.840: Adding CBMEM entry as no. 1
02.840: Moving GDT to 1f7d0200...ok
02.844: High Tables Base is 1f7d0000.
02.848: POST: 0x9a
02.848: Copying Interrupt Routing Table to 0x000f0000... done.
02.852: PIRQ Entry 0 Dev/Fn: F Slot: 5
02.856: INT: A link: 1 bitmap: 800 IRQ: 11
02.860: INT: B link: 2 bitmap: 20 IRQ: 5
02.860: INT: C link: 3 bitmap: 400 IRQ: 10
02.864: INT: D link: 4 bitmap: 400 IRQ: 10
02.868: Assigning IRQ 5 to 0:f.3
02.872: i8259_configure_irq_trigger: current interrupts are 0x0
02.876: i8259_configure_irq_trigger: try to set interrupts 0x20
02.880: Assigning IRQ 10 to 0:f.4
02.884: i8259_configure_irq_trigger: current interrupts are 0x20
02.888: i8259_configure_irq_trigger: try to set interrupts 0x420
02.892: Assigning IRQ 10 to 0:f.5
02.896: i8259_configure_irq_trigger: current interrupts are 0x420
02.900: i8259_configure_irq_trigger: try to set interrupts 0x420
02.904: PIRQ Entry 1 Dev/Fn: D Slot: 1
02.908: INT: A link: 4 bitmap: 400 IRQ: 10
02.912: INT: B link: 3 bitmap: 400 IRQ: 10
02.916: INT: C link: 2 bitmap: 20 IRQ: 5
02.916: INT: D link: 1 bitmap: 800 IRQ: 11
02.920: PIRQ Entry 2 Dev/Fn: E Slot: 2
02.924: INT: A link: 1 bitmap: 800 IRQ: 11
02.928: INT: B link: 2 bitmap: 20 IRQ: 5
02.932: INT: C link: 3 bitmap: 400 IRQ: 10
02.932: INT: D link: 4 bitmap: 400 IRQ: 10
02.938: Assigning IRQ 11 to 0:e.0
02.938: i8259_configure_irq_trigger: current interrupts are 0x420
02.944: i8259_configure_irq_trigger: try to set interrupts 0xc20
02.948: PIRQ1: 11
02.952: PIRQ2: 5
02.952: PIRQ3: 10
02.952: PIRQ4: 10
02.952: Adding CBMEM entry as no. 2
02.956: Copying Interrupt Routing Table to 0x1f7d0400... done.
02.960: PIRQ Entry 0 Dev/Fn: F Slot: 5
02.964: INT: A link: 1 bitmap: 800 IRQ: 11
02.968: INT: B link: 2 bitmap: 20 IRQ: 5
02.968: INT: C link: 3 bitmap: 400 IRQ: 10
02.972: INT: D link: 4 bitmap: 400 IRQ: 10
02.976: Assigning IRQ 5 to 0:f.3
02.980: i8259_configure_irq_trigger: current interrupts are 0xc20
02.984: i8259_configure_irq_trigger: try to set interrupts 0xc20
02.988: Assigning IRQ 10 to 0:f.4
02.992: i8259_configure_irq_trigger: current interrupts are 0xc20
02.998: i8259_configure_irq_trigger: try to set interrupts 0xc20
03.000: Assigning IRQ 10 to 0:f.5
03.004: i8259_configure_irq_trigger: current interrupts are 0xc20
03.008: i8259_configure_irq_trigger: try to set interrupts 0xc20
03.016: PIRQ Entry 1 Dev/Fn: D Slot: 1
03.016: INT: A link: 4 bitmap: 400 IRQ: 10
03.020: INT: B link: 3 bitmap: 400 IRQ: 10
03.024: INT: C link: 2 bitmap: 20 IRQ: 5
03.028: INT: D link: 1 bitmap: 800 IRQ: 11
03.028: PIRQ Entry 2 Dev/Fn: E Slot: 2
03.032: INT: A link: 1 bitmap: 800 IRQ: 11
03.036: INT: B link: 2 bitmap: 20 IRQ: 5
03.040: INT: C link: 3 bitmap: 400 IRQ: 10
03.040: INT: D link: 4 bitmap: 400 IRQ: 10
03.044: Assigning IRQ 11 to 0:e.0
03.048: i8259_configure_irq_trigger: current interrupts are 0xc20
03.052: i8259_configure_irq_trigger: try to set interrupts 0xc20
03.058: PIRQ1: 11
03.058: PIRQ2: 5
03.058: PIRQ3: 10
03.060: PIRQ4: 10
03.060: PIRQ table: 80 bytes.
03.064: Adding CBMEM entry as no. 3
03.068: smbios_write_tables: 1f7d1400
03.068: Root Device (WYSE S50 Mainboard)
03.072: PCI_DOMAIN: 0000 (AMD GX (previously GX2) Northbridge)
03.076: PCI: 00:01.0 (AMD GX (previously GX2) Northbridge)
03.080: PCI: 00:01.1 (AMD GX (previously GX2) Northbridge)
03.084: PCI: 00:0e.0 (AMD Geode CS5536 Southbridge)
03.088: PCI: 00:0f.0 (AMD Geode CS5536 Southbridge)
03.092: PCI: 00:0f.2 (AMD Geode CS5536 Southbridge)
03.096: PCI: 00:0f.3 (AMD Geode CS5536 Southbridge)
03.100: PCI: 00:0f.4 (AMD Geode CS5536 Southbridge)
03.104: PCI: 00:0f.5 (AMD Geode CS5536 Southbridge)
03.108: APIC_CLUSTER: 0 (AMD GX (previously GX2) Northbridge)
03.118: APIC: 00 ()
03.118: PCI: 00:0f.6 ()
03.118: PCI: 00:0f.7 ()
03.118: CPU: 00 ()
03.118: SMBIOS tables: 282 bytes.
03.120: POST: 0x9d
03.120: Adding CBMEM entry as no. 4
03.124: Writing high table forward entry at 0x00000500
03.128: Wrote coreboot table at: 00000500 - 00000518 checksum c461
03.136: New low_table_end: 0x00000518
03.136: Now going to write high coreboot table at 0x1f7d1c00
03.144: rom_table_end = 0x1f7d1c00
03.144: Adjust low_table_end from 0x00000518 to 0x00001000
03.148: Adjust rom_table_end from 0x1f7d1c00 to 0x1f7e0000
03.152: Adding high table area
03.156: coreboot memory table:
03.160: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
03.164: 1. 0000000000001000-000000000009ffff: RAM
03.168: 2. 00000000000c0000-000000001f7cffff: RAM
03.172: 3. 000000001f7d0000-000000001f7dffff: CONFIGURATION TABLES
03.176: Wrote coreboot table at: 1f7d1c00 - 1f7d1da4 checksum 5ac9
03.180: coreboot table: 420 bytes.
03.184: POST: 0x9e
03.184: POST: 0x9d
03.188: Multiboot Information structure has been written.
03.192: 0. FREE SPACE 1f7d3c00 0000c400
03.192: 1. GDT 1f7d0200 00000200
03.196: 2. IRQ TABLE 1f7d0400 00001000
03.200: 3. SMBIOS 1f7d1400 00000800
03.204: 4. COREBOOT 1f7d1c00 00002000
03.204: Searching for fallback/payload
03.208: Check fallback/romstage
03.212: Check fallback/coreboot_ram
03.212: Check fallback/payload
03.216: Got a payload
03.216: Loading segment from rom address 0xfff0b4f8
03.220: data (compression=1)
03.224: New segment dstaddr 0xea7d0 memsize 0x15830 srcaddr 0xfff0b530 filesize 0xaa99
03.232: (cleaned up) New segment addr 0xea7d0 size 0x15830 offset 0xfff0b530 filesize 0xaa99
03.236: Loading segment from rom address 0xfff0b514
03.240: Entry Point 0x00000000
03.244: Loading Segment: addr: 0x00000000000ea7d0 memsz: 0x0000000000015830 filesz: 0x000000000000aa99
03.252: lb: [0x0000000000100000, 0x000000000011c000)
03.256: Post relocation: addr: 0x00000000000ea7d0 memsz: 0x0000000000015830 filesz: 0x000000000000aa99
03.264: using LZMA
03.412: [ 0x000ea7d0, 00100000, 0x00100000) <- fff0b530
03.416: dest 000ea7d0, end 00100000, bouncebuffer 1f798000
03.424: Loaded segments
03.424: Jumping to boot code at fc276
03.428: POST: 0xf8
03.428: entry = 0x000fc276
03.428: lb_start = 0x00100000
03.432: lb_size = 0x0001c000
03.432: adjust = 0x1f6b4000
03.436: buffer = 0x1f798000
03.436: elf_boot_notes = 0x0010f0cc
03.442: adjusted_boot_notes = 0x1f7c30cc
03.443: Start bios (version pre-1.6.4-20120307_220838-Debian)
03.448: Find memory size
03.452: Attempting to find coreboot table
03.456: Found coreboot table forwarder.
03.456: Now attempting to find coreboot memory map
03.460: Add to e820 map: 00000000 00001000 2
03.464: Add to e820 map: 00001000 0009f000 1
03.468: Add to e820 map: 000c0000 1f710000 1
03.475: Add to e820 map: 1f7d0000 00010000 2
03.475: Add to e820 map: 00000000 00004000 1
03.476: Found mainboard Wyse s50
03.480: Found CBFS header at 0xfffffd30
03.484: Add to e820 map: 000a0000 00050000 -1
03.488: Add to e820 map: 000f0000 00010000 2
03.488: Ram Size=0x1f7d0000 (0x0000000000000000 high)
03.492: malloc setup
03.496: Add to e820 map: 1f7c0000 00010000 2
03.500: pmm_malloc zone=0x000f3870 handle=ffffffff size=34972 align=10 ret=0x1f7b7640 (detail=0x1f7bfee0)
03.508: Relocating init from 0x000eafe0 to 0x1f7b7640 (size 34972)
03.520: malloc fixup reloc
03.520: init ivt
03.524: init bda
03.524: Add to e820 map: 0009fc00 00000400 2
03.528: init pic
03.528: init timer
03.528: tsc calibrate start=1144469936 end=1145097058 diff=627122
03.536: CPU Mhz=365
03.536: math cp init
03.536: PCI probe
03.537: Searching CBFS for prefix etc/extra-pci-roots
03.544: Found CBFS file fallback/romstage
03.544: Found CBFS file fallback/coreboot_ram
03.548: Found CBFS file fallback/payload
03.552: Found CBFS file vsa
03.556: Found CBFS file config
03.556: Found CBFS file etc/boot-menu-wait
03.560: Found CBFS file
03.560: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=112 align=10 ret=0x1f7b7570 (detail=0x1f7b75e0)
03.568: PCI device 00:01.0 (vd=100b:0028 c=0600)
03.572: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=112 align=10 ret=0x1f7b74d0 (detail=0x1f7b7540)
03.580: PCI device 00:01.1 (vd=100b:0030 c=0300)
03.584: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=112 align=10 ret=0x1f7b7430 (detail=0x1f7b74a0)
03.596: PCI device 00:0e.0 (vd=10ec:8139 c=0200)
03.596: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=112 align=10 ret=0x1f7b7390 (detail=0x1f7b7400)
03.608: PCI device 00:0f.0 (vd=1022:2090 c=0601)
03.612: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=112 align=10 ret=0x1f7b72f0 (detail=0x1f7b7360)
03.616: PCI device 00:0f.2 (vd=1022:209a c=0101)
03.624: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=112 align=10 ret=0x1f7b7250 (detail=0x1f7b72c0)
03.632: PCI device 00:0f.3 (vd=1022:2093 c=0401)
03.633: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=112 align=10 ret=0x1f7b71b0 (detail=0x1f7b7220)
03.644: PCI device 00:0f.4 (vd=1022:2094 c=0c03)
03.648: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=112 align=10 ret=0x1f7b7110 (detail=0x1f7b7180)
03.656: PCI device 00:0f.5 (vd=1022:2095 c=0c03)
03.657: Found 8 PCI devices (max PCI bus is 00)
03.664: Searching CBFS for prefix bootorder
03.664: Found CBFS file fallback/romstage
03.668: Found CBFS file fallback/coreboot_ram
03.672: Found CBFS file fallback/payload
03.676: Found CBFS file vsa
03.676: Found CBFS file config
03.680: Found CBFS file etc/boot-menu-wait
03.684: Found CBFS file
03.684: No apic - only the main cpu is present.
03.688: init bios32
03.688: init PMM
03.688: init PNPBIOS table
03.692: init keyboard
03.692: init mouse
03.692: Relocating coreboot bios tables
03.696: pmm_malloc zone=0x1f7bfec8 handle=ffffffff size=80 align=10 ret=0x000fdb10 (detail=0x1f7b70e0)
03.704: Copying PIR from 0x1f7d0400 to 0x000fdb10
03.708: pmm_malloc zone=0x1f7bfec8 handle=ffffffff size=31 align=10 ret=0x000fdaf0 (detail=0x1f7b70b0)
03.716: Copying SMBIOS entry point from 0x1f7d1400 to 0x000fdaf0
03.724: Scan for VGA option rom
03.724: Searching CBFS for prefix etc/optionroms-checksum
03.728: Found CBFS file fallback/romstage
03.732: Found CBFS file fallback/coreboot_ram
03.736: Found CBFS file fallback/payload
03.740: Found CBFS file vsa
03.740: Found CBFS file config
03.744: Found CBFS file etc/boot-menu-wait
03.748: Found CBFS file
03.748: Searching CBFS for prefix etc/s3-resume-vga-init
03.752: Found CBFS file fallback/romstage
03.756: Found CBFS file fallback/coreboot_ram
03.760: Found CBFS file fallback/payload
03.760: Found CBFS file vsa
03.764: Found CBFS file config
03.764: Found CBFS file etc/boot-menu-wait
03.768: Found CBFS file
03.772: Searching CBFS for prefix etc/screen-and-debug
03.776: Found CBFS file fallback/romstage
03.776: Found CBFS file fallback/coreboot_ram
03.780: Found CBFS file fallback/payload
03.784: Found CBFS file vsa
03.785: Found CBFS file config
03.788: Found CBFS file etc/boot-menu-wait
03.792: Found CBFS file
03.800: Attempting to init PCI bdf 00:01.1 (vd 100b:0030)
03.804: Searching CBFS for prefix pci100b,0030.rom
03.808: Found CBFS file fallback/romstage
03.812: Found CBFS file fallback/coreboot_ram
03.816: Found CBFS file fallback/payload
03.816: Found CBFS file vsa
03.820: Found CBFS file config
03.820: Found CBFS file etc/boot-menu-wait
03.824: Found CBFS file
03.828: Attempting to map option rom on dev 00:01.1
03.832: Option rom sizing returned 0 0
03.832: Searching CBFS for prefix vgaroms/
03.836: Found CBFS file fallback/romstage
03.840: Found CBFS file fallback/coreboot_ram
03.844: Found CBFS file fallback/payload
03.844: Found CBFS file vsa
03.848: Found CBFS file config
03.848: Found CBFS file etc/boot-menu-wait
03.852: Found CBFS file
03.853: init usb
03.856: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=28 align=10 ret=0x1f7b7060 (detail=0x1f7b7080)
03.864: OHCI init on dev 00:0f.4 (regs=0xfe00e000)
03.868: pmm_malloc zone=0x1f7bfec4 handle=ffffffff size=256 align=100 ret=0x1f7cff00 (detail=0x1f7b7030)
03.876: pmm_malloc zone=0x1f7bfec4 handle=ffffffff size=16 align=10 ret=0x1f7cfef0 (detail=0x1f7b7000)
03.976: set_address 0x1f7b7060
03.980: ohci_alloc_control_pipe 0x1f7b7060
03.984: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=48 align=10 ret=0x1f7b6fa0 (detail=0x1f7b6fd0)
04.000: ohci_control 0x1f7b6fb0
04.004: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=48 align=10 ret=0x1f7b6f40 (detail=0x1f7b6f70)
04.012: pmm_free 0x1f7b6f40 (detail=0x1f7b6f70)
04.016: ohci_alloc_control_pipe 0x1f7b7060
04.020: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=48 align=10 ret=0x1f7b6f40 (detail=0x1f7b6f70)
04.028: config_usb: 0x1f7b6f50
04.032: ohci_control 0x1f7b6f50
04.032: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=48 align=10 ret=0x1f7b6ee0 (detail=0x1f7b6f10)
04.040: pmm_free 0x1f7b6ee0 (detail=0x1f7b6f10)
04.044: device rev=0110 cls=00 sub=00 proto=00 size=08
04.048: ohci_control 0x1f7b6f50
04.052: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=48 align=10 ret=0x1f7b6ee0 (detail=0x1f7b6f10)
04.060: pmm_free 0x1f7b6ee0 (detail=0x1f7b6f10)
04.064: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=59 align=10 ret=0x1f7b6ed0 (detail=0x1f7b6f10)
04.072: ohci_control 0x1f7b6f50
04.076: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=48 align=10 ret=0x1f7b6e70 (detail=0x1f7b6ea0)
04.084: pmm_free 0x1f7b6e70 (detail=0x1f7b6ea0)
04.088: ohci_control 0x1f7b6f50
04.092: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=48 align=10 ret=0x1f7b6e70 (detail=0x1f7b6ea0)
04.100: pmm_free 0x1f7b6e70 (detail=0x1f7b6ea0)
04.104: usb_hid_init 0x1f7b6f50
04.104: ohci_control 0x1f7b6f50
04.108: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=48 align=10 ret=0x1f7b6e70 (detail=0x1f7b6ea0)
04.116: pmm_free 0x1f7b6e70 (detail=0x1f7b6ea0)
04.120: ohci_control 0x1f7b6f50
04.124: pmm_malloc zone=0x1f7bfed0 handle=ffffffff size=48 align=10 ret=0x1f7b6e70 (detail=0x1f7b6ea0)
04.132: pmm_free 0x1f7b6e70 (detail=0x1f7b6ea0)
04.133: ohci_alloc_intr_pipe 0x1f7b7060 3
04.136: pmm_malloc zone=0x1f7bfec4 handle=ffffffff size=48 align=10 ret=0x1f7cfec0 (detail=0x1f7b6ea0)
04.148: pmm_malloc zone=0x1f7bfec4 handle=ffffffff size=240 align=10 ret=0x1f7cfdd0 (detail=0x1f7b6e70)
04.156: pmm_malloc zone=0x1f7bfec4 handle=ffffffff size=120 align=10 ret=0x1f7cfd50 (detail=0x1f7b6e40)
04.161: USB keyboard initialized
04.164: pmm_free 0x1f7b6ed0 (detail=0x1f7b6f10)
04.168: ohci_free_pipes 0x1f7b7060
04.172: Got key 0 0
04.172: Got key 53 0
04.172: enter handle_15:
04.176: a=00004f1d b=00000000 c=0000d270 d=fffe7953 ds=0000 es=9fc0 ss=0000
04.180: si=00006e1e di=00000000 bp=00000001 sp=00006de2 cs=f000 ip=8462 f=0203
04.188: enter handle_15:
04.188: a=00004f2a b=00000000 c=0000d272 d=00000052 ds=0000 es=0040 ss=0000
04.196: si=00006e1e di=00000001 bp=00000001 sp=00006de2 cs=f000 ip=8462 f=0203
04.204: enter handle_15:
04.204: a=00004fe0 b=0000e01d c=0000d278 d=00000050 ds=0000 es=0040 ss=0000
04.212: si=00006e1e di=00000004 bp=00000001 sp=00006dda cs=f000 ip=8462 f=0203
04.216: enter handle_15:
04.220: a=00004f1d b=00000000 c=00000040 d=00000006 ds=0000 es=0040 ss=0000
04.224: si=00006e1e di=00000004 bp=00000001 sp=00006de2 cs=f000 ip=8462 f=0203
04.232: enter handle_15:
04.232: a=00004fe0 b=0000e038 c=0000d27c d=00000040 ds=0000 es=0040 ss=0000
04.240: si=00006e1e di=00000006 bp=00000001 sp=00006dda cs=f000 ip=8462 f=0203
04.248: enter handle_15:
04.248: a=00004f38 b=00000000 c=00000040 d=00000006 ds=0000 es=0040 ss=0000
04.253: si=00006e1e di=00000006 bp=00000001 sp=00006de2 cs=f000 ip=8462 f=0203
04.260: <00>
04.261: <f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><f8><ff>S
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