diff --git a/src/bootsplash.c b/src/bootsplash.c index a85e2b2..0869d1d 100644 --- a/src/bootsplash.c +++ b/src/bootsplash.c @@ -126,7 +126,7 @@ enable_bootsplash(void) br.es = FLATPTR_TO_SEG(vesa_info); call16_int10(&br); if (vesa_info->signature != VESA_SIGNATURE) { - dprintf(1,"No VBE2 found.\n"); + dprintf(1,"No VBE2 found. was %x \n", vesa_info->signature); goto done; } diff --git a/src/misc.c b/src/misc.c index 54d8aef..7d971aa 100644 --- a/src/misc.c +++ b/src/misc.c @@ -51,6 +51,7 @@ handle_10(struct bregs *regs) { debug_enter(regs, DEBUG_HDL_10); // dont do anything, since the VGA BIOS handles int10h requests + dprintf(1, "Here I am\n"); } // NMI handler diff --git a/vgasrc/geodevga.c b/vgasrc/geodevga.c index 5c6caf0..52e333a 100644 --- a/vgasrc/geodevga.c +++ b/vgasrc/geodevga.c @@ -106,6 +106,7 @@ static int legacyio_check(void) return ret; } + /**************************************************************** * Extened CRTC Register functions ****************************************************************/ @@ -136,6 +137,7 @@ static void crtce_write(u8 reg, u8 val) crtce_lock(); } + /**************************************************************** * Display Controller Functions ****************************************************************/ @@ -151,7 +153,7 @@ static void dc_write(u16 seg, u32 reg, u32 val) u32 *dest_far = (void*)reg; SET_FARVAR(seg,*dest_far,val); } - +#if 0 static void dc_set(u16 seg, u32 reg, u32 and, u32 or) { u32 val = dc_read(seg,reg); @@ -159,7 +161,7 @@ static void dc_set(u16 seg, u32 reg, u32 and, u32 or) val |=or; dc_write(seg,reg,val); } - +#endif static void dc_unlock(u16 seg) { dc_write(seg,DC_UNLOCK,DC_LOCK_UNLOCK); @@ -204,7 +206,7 @@ static void dc_unmap(void) /**************************************************************** * Init Functions ****************************************************************/ - +#if 0 /* Set up the dc (display controller) portion of the geodelx * The dc provides hardware support for VGA graphics * for features not accessible from the VGA registers, @@ -226,7 +228,7 @@ static int dc_setup(void) dc_write(seg,DC_CURS_ST_OFFSET,0x0); /* read fb-bar from pci, then point dc to the fb base */ - dc_fb = dc_read(seg,DC_GLIU0_MEM_OFFSET); + dc_fb = dc_read(seg,DC_GLIU0_MEM_OFFSET); // 0x84 fb = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0); if (fb!=dc_fb) { dc_write(seg,DC_GLIU0_MEM_OFFSET,fb); @@ -280,6 +282,387 @@ int vp_setup(void) return 0; } +#endif + +#define OUTPUT_PANEL (1 << 0) +#define OUTPUT_CRT (1 << 1) + +static const struct mode { + unsigned int pll; + unsigned int hactive, hblankstart, hsyncstart; + unsigned int hsyncend, hblankend, htotal; + unsigned int vactive, vblankstart, vsyncstart; + unsigned int vsyncend, vblankend, vtotal; + unsigned int synccfg; + unsigned int output; +} vga_mode = { + .pll = 0x215D, + .hactive = 640, + .vactive = 400, + .hblankstart = 640, + .hsyncstart = 640 + 40, + .hsyncend = 640 + 40 + 96, + .hblankend = 640 + 40 + 96 + 24, + .htotal = 640 + 40 + 96 + 24, + .vblankstart = 400, + .vsyncstart = 400 + 39, + .vsyncend = 400 + 39 + 2, + .vblankend = 400 + 39 + 2 + 9, + .vtotal = 400 + 39 + 2 + 9, + .synccfg = 0x300, + .output = OUTPUT_PANEL|OUTPUT_CRT, +}; + + +#define VP_FP_START 0x400 + +#define VP_VRR 0x120 + +#define VP_DCFG_GV_GAM (1 << 21) +#define VP_DCFG_PWR_SEQ_DELAY ((1 << 17) | (1 << 18) | (1 << 19)) +#define VP_DCFG_PWR_SEQ_DELAY_DEFAULT (1 << 19) /* undocumented */ +#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16)) +#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16) +#define VP_DCFG_CRT_VSYNC_POL (1 << 9) +#define VP_DCFG_CRT_HSYNC_POL (1 << 8) +#define VP_DCFG_DAC_BL_EN (1 << 3) +#define VP_DCFG_VSYNC_EN (1 << 2) +#define VP_DCFG_HSYNC_EN (1 << 1) +#define VP_DCFG_CRT_EN (1 << 0) + +#define FP_PT1 0x00 +#define FP_PT2 0x08 +#define FP_PM 0x10 +#define FP_DFC 0x18 + +#define FP_PM_P (1 << 24) /* panel power ctl */ +#define FP_PT2_SCRC (1 << 27) /* shfclk free */ +#define FP_DFC_BC ((1 << 4) | (1 << 5) | (1 << 6)) + +#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */ +#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */ + +#define VP_MISC_APWRDN (1 << 11) +#define VP_MISC_DACPWRDN (1 << 10) + +#define MSR_LX_MSR_PADSEL 0x48002011 + + +static void dump_mem(const char *title, void *mem, u32 size) +{ + int i; + u8 *data = (u8 *)mem; + + dprintf(1, "%s dump:\n", title); + for (i = 0; i < size; i++) { + if (0 == (i % 16)) + dprintf(1, "%02x:", i); + + dprintf(1, " %02x", data[i]); + + if (15 == (i % 16)) + dprintf(1, "\n"); + } +} + +static void dump_registers(void) +{ + int i; + u16 seg = dc_map(SEG_GRAPH); + + /* wait for the BLT engine to stop being busy */ +#if 0 + do { + i = read_gp(par, GP_BLT_STATUS); + } while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE)); +#endif + +#if 0 + /* save MSRs */ + rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel); + rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); + rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); + rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare); +#endif + + /* Unlock the DC registers */ + dc_unlock(seg); + + + u32 vp = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_3); + +#define GP_REG_COUNT (0x7c / 4) +#define DC_REG_COUNT (0xf0 / 4) +#define VP_REG_COUNT (0x158 / 8) +#define FP_REG_COUNT (0x60 / 8) + + //dump_mem("GP", par->gp, sizeof(par->gp)); + //dump_mem("DC", par->dc, sizeof(par->dc)); + dump_mem("VP", vp, VP_REG_COUNT); + dump_mem("FP", vp + VP_FP_START, FP_REG_COUNT); +#if 0 + + /* save the display controller palette */ + write_dc(par, DC_PAL_ADDRESS, 0); + for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++) + par->dc_pal[i] = read_dc(par, DC_PAL_DATA); + + /* save the video processor palette */ + write_vp(par, VP_PAR, 0); + for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++) + par->vp_pal[i] = read_vp(par, VP_PDR); + + /* save the horizontal filter coefficients */ + filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL; + for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) { + write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); + par->hcoeff[i] = read_dc(par, DC_FILT_COEFF1); + par->hcoeff[i + 1] = read_dc(par, DC_FILT_COEFF2); + } + + /* save the vertical filter coefficients */ + filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL; + for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) { + write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); + par->vcoeff[i] = read_dc(par, DC_FILT_COEFF1); + } + + /* save video coeff ram */ + memcpy(par->vp_coeff, par->vp_regs + VP_VCR, sizeof(par->vp_coeff)); +#endif +} + +static void set_dotpll(void) +{ + union u64_u32_u msr; + int i; + + msr = geode_msrRead(MSR_GLCP_DOTPLL); + + msr.hi = vga_mode.pll; + msr.lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX); + msr.lo |= MSR_GLCP_DOTPLL_DOTRESET; + + geode_msrWrite(MSR_GLCP_DOTPLL, 0, 0, msr.hi, msr.lo); + + /* Wait 100us for the PLL to lock */ + //udelay(100); + + /* Now, loop for the lock bit */ + for(i = 0; i < 1000; i++) { + msr = geode_msrRead(MSR_GLCP_DOTPLL); + if (msr.lo & MSR_GLCP_DOTPLL_LOCK) + break; + } + + /* Clear the reset bit */ + msr.lo &= ~MSR_GLCP_DOTPLL_DOTRESET; + geode_msrWrite(MSR_GLCP_DOTPLL, 0, 0, msr.hi, msr.lo); +} + +static void graphics_enable(void) +{ + u32 temp, config; + u32 vp = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_3); + + /* Set the video request register */ + geode_memWrite(vp + VP_VRR, 0x0, 0x00); //write_vp(par, VP_VRR, 0); + + /* Set up the polarities */ + + //config = read_vp(par, VP_DCFG); + config = geode_memRead(vp + VP_DCFG); + + config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY | + VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL); + + config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT + | VP_DCFG_GV_GAM); + + //if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) + // config |= VP_DCFG_CRT_HSYNC_POL; + + //if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) + // config |= VP_DCFG_CRT_VSYNC_POL; + + if (vga_mode.output & OUTPUT_PANEL) { + union u64_u32_u msr; + //u32 msrlo, msrhi; + + geode_memWrite(vp + VP_FP_START + FP_PT1, 0x0, 0x0); //write_fp(par, FP_PT1, 0); + temp = FP_PT2_SCRC; + + //if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) + // temp |= FP_PT2_HSP; + + //if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) + // temp |= FP_PT2_VSP; + + geode_memWrite(vp + VP_FP_START + FP_PT2, 0x0, temp); //write_fp(par, FP_PT2, temp); + geode_memWrite(vp + VP_FP_START + FP_DFC, 0x0, FP_DFC_BC); //write_fp(par, FP_DFC, FP_DFC_BC); + + msr.lo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW; + msr.hi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH; + + geode_msrWrite(MSR_LX_MSR_PADSEL, 0, 0, msr.hi, msr.lo); //wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi); + } + + if (vga_mode.output & OUTPUT_CRT) { + config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN | + VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN; + } + + geode_memWrite(vp + VP_DCFG, 0x0, config); //write_vp(par, VP_DCFG, config); + + /* Turn the CRT dacs back on */ + + if (vga_mode.output & OUTPUT_CRT) { + temp = geode_memRead(vp + VP_MISC); //temp = read_vp(par, VP_MISC); + temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN); + geode_memWrite(vp + VP_MISC, 0x0, temp); //write_vp(par, VP_MISC, temp); + } + + /* Turn the panel on (if it isn't already) */ + dprintf(1,"Turn the panel on\n"); + if (vga_mode.output & OUTPUT_PANEL) { + temp = geode_memRead(vp + VP_FP_START + FP_PM); + temp |= FP_PM_P; + geode_memWrite(vp + VP_FP_START + FP_PM, 0x00, temp); //write_fp(par, FP_PM, read_fp(par, FP_PM) | FP_PM_P); + } +} + +static void init_video_mode(void) +{ + union u64_u32_u msr; // unsigned int lo, hi, val; + u32 val; + u32 dv = 0x0; /*TODO*/ + u32 gcfg, dcfg; + + u16 seg = dc_map(SEG_GRAPH); + + /* Unlock the DC registers */ + dc_unlock(seg); + + /* Set the dot PLL */ + set_dotpll(); + + /* Set output mode */ + msr = geode_msrRead(VP_MSR_CONFIG_LX); //rdmsr(0x48002001, lo, hi); + msr.lo &= ~MSR_LX_GLD_MSR_CONFIG_FMT; + + if (vga_mode.output & 0x1) { + msr.lo |= MSR_LX_GLD_MSR_CONFIG_FMT_FP; + } else { + msr.lo |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT; + } + geode_msrWrite(VP_MSR_CONFIG_LX, 0, 0, msr.hi, msr.lo); //wrmsr(0x48002001, lo, hi); + + /* Clear the various buffers */ + dc_write(seg, DC_FB_ST_OFFSET, 0); + dc_write(seg, DC_CB_ST_OFFSET, 0); + dc_write(seg, DC_CURS_ST_OFFSET, 0); + + val = dc_read(seg, DC_GENLK_CTL); + val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN | DC_GENLK_CTL_FLICK_SEL_MASK); + + /* Set up the default scaling */ + + dc_write(seg, DC_GFX_SCALE, (0x4000 << 16) | 0x4000); + dc_write(seg, DC_IRQ_FILT_CTRL, 0); + dc_write(seg, DC_GENLK_CTL, val); + + /* Set up the compression (or lack thereof) */ + dc_write(seg, DC_DV_TOP, vga_mode.hactive * vga_mode.vactive | DC_DV_TOP_DV_TOP_EN); + + val = dc_read(seg, DC_DV_CTRL) & ~DC_DV_CTL_DV_LINE_SIZE; + dc_write(seg, DC_DV_CTRL, val | dv); + //dc_write(seg, 0x8C, 0); // DC_DV_CTL + + /* Set the pitch */ + dc_write(seg, DC_GFX_PITCH, vga_mode.hactive >> 3); + dc_write(seg, DC_LINE_SIZE, (vga_mode.hactive + 7) >> 3); + + /* Set up default watermarks */ + msr = geode_msrRead(DC_SPARE); + + msr.lo &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO + | MSR_LX_SPARE_MSR_VFIFO_ARB_SEL + | MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M + | MSR_LX_SPARE_MSR_WM_LPEN_OVRD); + msr.lo |= MSR_LX_SPARE_MSR_DIS_VIFO_WM | + MSR_LX_SPARE_MSR_DIS_INIT_V_PRI; + + geode_msrWrite(DC_SPARE, ~0, 0, 0, msr.lo); + + gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */ + gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */ + (0xb << DC_GENERAL_CFG_DFHPEL_SHIFT); + gcfg |= DC_GENERAL_CFG_FDTY; /* Set the frame dirty mode */ + + dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */ + dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */ + dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */ + dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */ + dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */ + dcfg |= DC_DISPLAY_CFG_VISL; + dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */ + + /* Set the current BPP mode */ + + //switch (info->var.bits_per_pixel) { + //case 8: + dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; + //break; + + //case 16: + // dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; + // break; + + //case 32: + //case 24: + // dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP; + // break; + //} + + /* Write the timings */ + dc_write(seg, DC_H_ACTIVE_TIMING, (vga_mode.hactive - 1) | ((vga_mode.htotal - 1) << 16)); + + dc_write(seg, DC_H_BLANK_TIMING, (vga_mode.hblankstart - 1) | ((vga_mode.hblankend - 1) << 16)); + + dc_write(seg, DC_H_SYNC_TIMING, (vga_mode.hsyncstart - 1) | ((vga_mode.hsyncend - 1) << 16)); + + dc_write(seg, DC_V_ACTIVE_TIMING, (vga_mode.vactive - 1) | ((vga_mode.vtotal - 1) << 16)); + + dc_write(seg, DC_V_BLANK_TIMING, (vga_mode.vblankstart - 1) | ((vga_mode.vblankend - 1) << 16)); + + dc_write(seg, DC_V_SYNC_TIMING, (vga_mode.vsyncstart - 1) | ((vga_mode.vsyncend - 1) << 16)); + + dc_write(seg, DC_FB_ACTIVE, ((vga_mode.hactive - 1) << 16) | (vga_mode.vactive - 1)); + + + /* read fb-bar from pci, then point dc to the fb base */ + u32 dc_fb = dc_read(seg,DC_GLIU0_MEM_OFFSET); // 0x84 + u32 fb = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0); + if (fb != dc_fb) { + dc_write(seg, DC_GLIU0_MEM_OFFSET, fb); + } + + /* enable the graphics output */ + graphics_enable(); + + /* Write the final configuration */ + + dc_write(seg, DC_DISPLAY_CFG, dcfg); + dc_write(seg, DC_ARB_CFG, 0); + dc_write(seg, DC_GENERAL_CFG, gcfg); + + + /* Lock the DC registers */ + dc_lock(seg); + dc_unmap(); + + //dump_registers(); +} static u8 geode_crtc_01[] VAR16 = { 0x2d, 0x27, 0x28, 0x90, 0x29, 0x8e, 0xbf, 0x1f, @@ -366,8 +749,8 @@ int geodevga_init(void) if (GET_GLOBAL(VgaBDF) < 0) // Device should be at 00:01.1 SET_VGA(VgaBDF, pci_to_bdf(0, 1, 1)); - ret |= vp_setup(); - ret |= dc_setup(); + + init_video_mode(); return ret; } diff --git a/vgasrc/geodevga.h b/vgasrc/geodevga.h index fd7ce43..c32f847 100644 --- a/vgasrc/geodevga.h +++ b/vgasrc/geodevga.h @@ -39,14 +39,44 @@ #define VP_MSR_CONFIG_GX2 0xc0002001 /* GX2 */ #define VP_MSR_CONFIG_LX 0x48002001 /* LX */ +/* note: this is actually the VP's GLD_MSR_CONFIG */ +#define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5)) +#define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3) +#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0) +#define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) + +/* Clock Control */ +#define MSR_GLCP_DOTPLL 0x4C000015 + +#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */ +#define MSR_GLCP_DOTPLL_HALFPIX (1 << 24) +#define MSR_GLCP_DOTPLL_BYPASS (1 << 15) +#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0) + /* DC REG OFFSET */ -#define DC_UNLOCK 0x0 -#define DC_GENERAL_CFG 0x4 -#define DC_DISPLAY_CFG 0x8 +#define DC_UNLOCK 0x00 +#define DC_GENERAL_CFG 0x04 +#define DC_DISPLAY_CFG 0x08 +#define DC_ARB_CFG 0x0C #define DC_FB_ST_OFFSET 0x10 #define DC_CB_ST_OFFSET 0x14 #define DC_CURS_ST_OFFSET 0x18 +#define DC_DV_TOP 0x2C +#define DC_LINE_SIZE 0x30 +#define DC_GFX_PITCH 0x34 +#define DC_H_ACTIVE_TIMING 0x40 +#define DC_H_BLANK_TIMING 0x44 +#define DC_H_SYNC_TIMING 0x48 +#define DC_V_ACTIVE_TIMING 0x50 +#define DC_V_BLANK_TIMING 0x54 +#define DC_V_SYNC_TIMING 0x58 +#define DC_FB_ACTIVE 0x5C + #define DC_GLIU0_MEM_OFFSET 0x84 +#define DC_DV_CTRL 0x88 +#define DC_GFX_SCALE 0x90 +#define DC_IRQ_FILT_CTRL 0x94 +#define DC_GENLK_CTL 0xD4 /* VP REG OFFSET */ #define VP_VCFG 0x0 @@ -59,6 +89,32 @@ #define DC_GDEN (1 << 3) #define DC_TRUP (1 << 6) +#define DC_GENERAL_CFG_FDTY (1 << 17) +#define DC_GENERAL_CFG_DFHPEL_SHIFT (12) +#define DC_GENERAL_CFG_DFHPSL_SHIFT (8) +#define DC_GENERAL_CFG_DFLE (1 << 0) + +#define DC_DISPLAY_CFG_VISL (1 << 27) +#define DC_DISPLAY_CFG_PALB (1 << 25) +#define DC_DISPLAY_CFG_DCEN (1 << 24) +#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9) +#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8) +#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0) +#define DC_DISPLAY_CFG_TRUP (1 << 6) +#define DC_DISPLAY_CFG_VDEN (1 << 4) +#define DC_DISPLAY_CFG_GDEN (1 << 3) +#define DC_DISPLAY_CFG_TGEN (1 << 0) + +#define DC_DV_TOP_DV_TOP_EN (1 << 0) + +#define DC_DV_CTL_DV_LINE_SIZE ((1 << 10) | (1 << 11)) + +#define DC_GENLK_CTL_FLICK_SEL_MASK (0x0F << 28) +#define DC_GENLK_CTL_ALPHA_FLICK_EN (1 << 25) +#define DC_GENLK_CTL_FLICK_EN (1 << 24) +#define DC_GENLK_CTL_GENLK_EN (1 << 18) + + /* VP bits */ #define VP_CRT_EN (1 << 0) #define VP_HSYNC_EN (1 << 1) @@ -70,6 +126,15 @@ /* Mask */ #define DC_CFG_MSK 0xf000a6 +#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */ +#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */ +#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */ +#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */ +#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */ +#define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6) +#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */ +#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */ +#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */ int geodevga_init(); #endif diff --git a/vgasrc/vbe.c b/vgasrc/vbe.c index 227a244..2bb8393 100644 --- a/vgasrc/vbe.c +++ b/vgasrc/vbe.c @@ -383,6 +383,68 @@ vbe_104f10(struct bregs *regs) regs->ax = 0x004f; } +u8 edid[128] VAR16 = { +0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0c, 0xf4, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, +0x01, 0x0f, 0x01, 0x03, 0x80, 0x00, 0x00, 0x00, 0xee, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0xac, 0x00, 0x00, 0x31, 0x40, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, +0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xc4, 0x09, 0x80, 0xa0, 0x20, 0xe0, 0x2d, 0x10, 0x10, 0x60, +0xc2, 0x00, 0xd3, 0x9e, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32, 0x78, 0x19, +0x28, 0x03, 0x00, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfe, 0x00, 0x63, +0x6f, 0x6e, 0x67, 0x61, 0x74, 0x65, 0x63, 0x20, 0x41, 0x47, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x0e, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0 +}; + +static void +vbe_104f15(struct bregs *regs) +{ + u8 i; + u16 seg = regs->es; + void *data = (void *)(regs->di+0); + u16 unit = regs->cx; + u16 block = regs->dx; + //extern u8 _edid_data[128]; + + switch(regs->bl) { + case 0x00: + regs->bx = 0x1; /* DDC1 */ + break; + case 0x01: + dprintf(0, "VBE get EDID: unit 0x%02x - block 0x%02x\n", unit, block); + if (unit != 0) + { + dprintf(0, "VBE wrong unti=%x\n", unit); + regs->ax = 0x014f; + return; + } +#if 0 + /* our option rom can get patched during load e.g. from coreboot to + * update our _edid array with some usefull data. If this is the case, + * we return the edid data as-they-are, else we return an error code. + */ + if ((_edid_data[0] != 0x00) && (_edid_data[7] != 0x00)) { + regs->ax = 0x014f; + dprintf(1, "VBE invalid edid (0)\n"); + break; + } + + for (i = 1; i < 6; i++) { + if (_edid_data[i] != 0xff) { + regs->ax = 0x014f; + dprintf(1, "VBE invalid edid (1)\n"); + break; + } + } +#endif + //memcpy_far(seg, data, get_global_seg(), _edid_data, sizeof(_edid_data)); + memcpy_far(seg, data, get_global_seg(), edid, sizeof(edid)); + break; + default: + regs->ax = 0x014f; + return; + } + regs->ax = 0x004f; +} + static void vbe_104fXX(struct bregs *regs) { @@ -393,11 +455,15 @@ vbe_104fXX(struct bregs *regs) void noinline handle_104f(struct bregs *regs) { + dprintf(0, "%s\n", __func__); + if (!CONFIG_VGA_VBE) { vbe_104fXX(regs); return; } + dprintf(4, "handle_104f reg 0x%02x\n", regs->al); + switch (regs->al) { case 0x00: vbe_104f00(regs); break; case 0x01: vbe_104f01(regs); break; @@ -410,6 +476,7 @@ handle_104f(struct bregs *regs) case 0x08: vbe_104f08(regs); break; case 0x0a: vbe_104f0a(regs); break; case 0x10: vbe_104f10(regs); break; + case 0x15: vbe_104f15(regs); break; default: vbe_104fXX(regs); break; } } diff --git a/vgasrc/vgabios.c b/vgasrc/vgabios.c index b13d274..68d7331 100644 --- a/vgasrc/vgabios.c +++ b/vgasrc/vgabios.c @@ -1157,7 +1157,15 @@ handle_10XX(struct bregs *regs) void VISIBLE16 handle_10(struct bregs *regs) { + __debug_isr(__func__); + dprintf(1, "HE DU DA!\n"); + __debug_enter(regs, __func__); + __debug_enter((regs), "123"); debug_enter(regs, DEBUG_VGA_10); + + dprintf(1, "regs->ah = 0x%02\n", regs->ah); + __debug_isr(__func__); + switch (regs->ah) { case 0x00: handle_1000(regs); break; case 0x01: handle_1001(regs); break; @@ -1251,6 +1259,7 @@ vga_post(struct bregs *regs) extern void entry_10(void); SET_IVT(0x10, SEGOFF(get_global_seg(), (u32)entry_10)); + dprintf(1, "int10 handler is @ 0x%08x\n", (u32)entry_10); SET_VGA(HaveRunInit, 1); diff --git a/vgasrc/vgaentry.S b/vgasrc/vgaentry.S index d9fe05b..adc8060 100644 --- a/vgasrc/vgaentry.S +++ b/vgasrc/vgaentry.S @@ -39,7 +39,14 @@ _rom_header_other2: _rom_header_signature: .asciz "IBM" - +/**************************************************************** + * EDID data + ****************************************************************/ +/* + .global _edid_data +_edid_data: + .skip 128 +*/ /**************************************************************** * Entry points ****************************************************************/