Hi all,
I think I may have found a bug, and would appreciate someone taking a second
look.
Processor is an Atom C2718, we're using Coreboot 4.0 and booting into Grub and
Linux. I have found that making minor/trivial changes in Coreboot (such as
configuring an additional pin as a GPIO, or adding a couple of extra lines of
debut output) results in the processor rebooting during SeaBIOS' rtc_setup()
call.
Hard power-cycles work absolutely fine. The problem only occurs after issuing
the reboot command from Linux. It's worth noting that our platform doesn't
reset the power supplies, so rebooting is basically a "warm" reboot. Also, our
RTC isn't battery-backed. Following the reboot, the processor resets each time
it reaches rtc_setup(). My best guess so far is that my trivial code changes
are subtly changing the boot timing, meaning that by the time I hit the
rtc_setup, I have a pending NMI.
Anyway, rtc_setup() performs several CMOS register reads/writes. The function
that triggers the reset is rtc_mask(). This is the only routine in the RTC code
that doesn't explicitly disable non-maskable interrupts when writing to the
CMOS index register. The patch below allows everything to boot as it should.
Index: src/hw/rtc.c
===================================================================
--- a/src/hw/rtc.c
+++ b/src/hw/rtc.c
@@ -30,7 +30,7 @@
void
rtc_mask(u8 index, u8 off, u8 on)
{
- outb(index, PORT_CMOS_INDEX);
+ outb(index | NMI_DISABLE_BIT, PORT_CMOS_INDEX);
u8 val = inb(PORT_CMOS_DATA);
outb((val & ~off) | on, PORT_CMOS_DATA);
}
Best,
Tim
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