* Paolo Bonzini ([email protected]) wrote: > > > On 18/02/2017 17:55, Kevin O'Connor wrote: > > On Sat, Feb 18, 2017 at 04:11:28PM +0100, Paolo Bonzini wrote: > >> On 18/02/2017 04:45, Kevin O'Connor wrote: > >>> On Fri, Feb 17, 2017 at 02:12:57PM +0100, Paolo Bonzini wrote: > >>>> On 15/02/2017 18:35, Dr. David Alan Gilbert wrote: > >>>>> Yes it seems to. > >>>>> One worry is that if we ever fix the qemu triple-fault so it really > >>>>> does what you're describing and only resets the CPU, then I'm not > >>>>> sure your int3 is the right choice. > >>>>> > >>>>> The other question is whether that protected-mode exit switch > >>>>> works in practice on qemu; it's going to come back with a lot of it's > >>>>> devices reset. > >>>> > >>>> Right, keyboard reset (and port 92h reset) should be an INIT and not a > >>>> full system reset. But that's also something that should be fixed, not > >>>> a quirk to rely on... > >>> > >>> Could we rely on the pci reset mechanism (port 0xcf9)? > >> > >> That's only 3-4 years old, but 0xcf9 followed by keyboard reset should > >> always work. > > > > Since this would be qemu specific, I think it would be okay if reset > > only worked on qemu versions from the last few years. Or, are you > > saying only some machine types would support it? I checked, and > > reboots on isapc don't currently work at all (looks like the bios > > isn't mapped to 0xfff00000 on isapc) so I don't think that's a > > stopper. > > isapc should never be SMP, so the keyboard reset would be enough even if > it were fixed to be an INIT. Hence my suggestion of using 0xcf9 for > recent QEMU with PCI machine types, followed by keyboard reset for old > QEMU + isapc.
Any chance of getting this fix into the about to be tagged stable? Dave > Paolo > > _______________________________________________ > SeaBIOS mailing list > [email protected] > https://www.coreboot.org/mailman/listinfo/seabios -- Dr. David Alan Gilbert / [email protected] / Manchester, UK _______________________________________________ SeaBIOS mailing list [email protected] https://www.coreboot.org/mailman/listinfo/seabios
