On Sun, Jul 23, 2017 at 01:11:49AM +0300, Aleksandr Bezzubikov wrote: > On PCI init PCI bridge devices may need some > extra info about bus number to reserve, IO, memory and > prefetchable memory limits. QEMU can provide this > with special vendor-specific PCI capability. > > This capability is intended to be used only > for Red Hat PCI bridges, i.e. QEMU cooperation. > > Sizes of limits match ones from > PCI Type 1 Configuration Space Header, > number of buses to reserve occupies only 1 byte > since it is the size of Subordinate Bus Number register. > > Signed-off-by: Aleksandr Bezzubikov <zuban...@gmail.com> > --- > src/hw/pci_cap.h | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > create mode 100644 src/hw/pci_cap.h > > diff --git a/src/hw/pci_cap.h b/src/hw/pci_cap.h > new file mode 100644 > index 0000000..1382b0b > --- /dev/null > +++ b/src/hw/pci_cap.h > @@ -0,0 +1,23 @@ > +#ifndef _PCI_CAP_H > +#define _PCI_CAP_H > + > +#include "types.h" > + > +struct vendor_pci_cap { > + u8 id; > + u8 next; > + u8 len; > +};
Thanks. If you respin this series, please add this header to the src/fw/ directory instead of src/hw/. Also, I'd prefer to avoid a "pci_" prefix on the header as it makes it seem similar to the existing pci_regs.h and pci_ids.h headers which are a bit different - how about src/fw/dev-pci.h instead? -Kevin _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios