[forgot to cc to the mail list] Kevin O'Connor <[email protected]> 于2018年8月8日周三 下午10:14写道： > > On Thu, Aug 02, 2018 at 10:39:13AM +0800, Zihan Yang wrote: > > NOTE: This patch set is still ongoing and does not fully function > > as its goal. But it involves some API changes, therefore I post them for > > comments before moving on to make sure I'm on the right path. > > > > The corresponding qemu part can be found at > > https://gitlab.com/WhoisZihan/qemu-pci-domain/tree/master/qemu > > I will submit it to qemu list later. > > > > Currently seabios assumes there is only one pci domain(0), and almost > > everything operates on pci domain 0 by default. This patch aims to add > > multiple pci domain support for pci_device, while reserve the original > > API for compatibility. > > Thanks. I understand the desire to support multiple PCI domains in > QEMU and the guest OS. However, what is the high level reason for > wanting the BIOS to be able to interact with the secondary PCI > domains?
The pxb-pcie host bus is put into a separated domain, so are the devices under the pxb host bus. I think we should also initialize busses in other domains and probe those devices during bios initialization. But currently qemu only binds port 0xcf8 and 0xcfc to q35 host's conf_mem and data_mem, if we want to read the config space of pxb host, we should use another port. I use port range 0x1000 and 0x1004 for a temporary workaround because they seem to be 'free' now. Please correct me if I misunderstand it. P.S. Maybe you would want to ignore this patch set as there are a few bugs that I fix later, and I will soon send a v2 patch (v2 is not working either, but I think I find where the current problem is), soon after I fix my network proxy issue... Thanks Zihan _______________________________________________ SeaBIOS mailing list [email protected] https://mail.coreboot.org/mailman/listinfo/seabios
