On 30/07/2023 08:47, Paul Menzel wrote:
[Cc: +Paolo as original author of the driver]
Dear Mark,
Thank you for your patch.
Am 29.07.23 um 15:04 schrieb Mark Cave-Ayland:
The ESP SELATN command used to send SCSI commands from the ESP to thes SCSI bus
s/thes/the/
Ooops indeed, just a typo. As this is my first patch posted to the SeaBIOS list, is
this something that a maintainer can fix up when applying the patch, or does it need
a series repost?
is not a DMA command and therefore does not affect the STAT_TC bit. The only
reason this works at all is due to a bug in QEMU which (currently) always
updates the STAT_TC bit in ESP_RSTAT regardless of the state of the ESP_CMD_DMA
bit.
I’d appreciated a link to these QEMU patches, describing the problem in QEMU.
As mentioned on the cover letter, this is currently a WIP following on from my
earlier ESP series at
https://patchew.org/QEMU/20210304221103.6369-1-mark.cave-ayl...@ilande.co.uk/ which
was to enable QEMU's ESP emulation to boot MacOS classic.
Whilst the current implementation works, it's main problem is that there are
currently 4 different variations of the DMA transfer code: one for real DMA, another
for Mac "pseudo-DMA" (PDMA) and then each of those has a separate implementation for
MESSAGE OUT and COMMAND phases.
I have a WIP series that goes most of the way to consolidating everything down to a
single implementation, but progress had been paused due to the SeaBIOS boot test
failing. Now having looked at the SeaBIOS ESP SCSI driver I'm sure that the bug is
there, and that's why I submitted the patches here first with the aim of getting the
SeaBIOS fixes into QEMU first so I can finish off and submit the ESP series to QEMU.
The underlying issue resulting in this series is that QEMU changes the STAT_TC bit
(and the DMA counter) in several places where it shouldn't, and this has a subtle
effect on various OS driver state machines. The aim of my WIP changes is to fix this
so that QEMU's implementation matches the datasheet in this regard.
According to the NCR datasheet the INTR_BS/INTR_FC bits are set when the SELATN
Could you please mention the full name and revision of the datasheet?
The datasheet I have here is entitled "NCR 53C94, 53C95, 53C96 Advanced SCSI
Controller" and has the filename NCR_53C94_53C95_53C96_Data_Sheet_Feb90.pdf.
command has completed, so update the existing logic to check for these bits in
ESP_RINTR instead. Note that the read of ESP_RINTR needs to be restricted to
state == 0 as reading ESP_RINTR resets the ESP_RSTAT register which breaks the
STAT_TC check when state == 1.
This commit also includes an extra read of ESP_INTR to clear all the interrupt
bits before submitting the SELATN command to ensure that we don't accidentally
immediately progress to the data phase handling logic where ESP_RINTR bits have
already been set by a previous ESP command.
It’d be great, if you added the QEMU commands how to test your patch.
Sure! The QEMU command line I'm using to test SeaBIOS is:
./qemu-system-x86_64 -accel kvm -accel tcg -no-shutdown -device am53c974 \
-device scsi-cd,drive=cd1 \
-drive if=none,id=cd1,format=raw,file=debian-10.6.0-amd64-netinst.iso
If SeaBIOS boots to the Debian installer menu then all is working well.
Lastly, will SeaBIOS built with your patches still work with older QEMU versions
without your QEMU patches?
Yes indeed, and this is noted on the cover letter of the series.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
---
src/hw/esp-scsi.c | 36 ++++++++++++++++++++++--------------
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/src/hw/esp-scsi.c b/src/hw/esp-scsi.c
index e4815aa..2d2d915 100644
--- a/src/hw/esp-scsi.c
+++ b/src/hw/esp-scsi.c
@@ -57,6 +57,8 @@
#define ESP_STAT_MSG 0x04
#define ESP_STAT_TC 0x10
+#define ESP_INTR_FC 0x08
+#define ESP_INTR_BS 0x10
#define ESP_INTR_DC 0x20
struct esp_lun_s {
@@ -97,8 +99,9 @@ esp_scsi_process_op(struct disk_op_s *op)
outb(target, iobase + ESP_WBUSID);
- /* Clear FIFO before sending command. */
+ /* Clear FIFO and interrupts before sending command. */
outb(ESP_CMD_FLUSH, iobase + ESP_CMD);
+ inb(iobase + ESP_RINTR);
/*
* We need to pass the LUN at the beginning of the command, and the FIFO
@@ -115,22 +118,27 @@ esp_scsi_process_op(struct disk_op_s *op)
for (state = 0;;) {
u8 stat = inb(iobase + ESP_RSTAT);
+ u8 intr;
- /* Detect disconnected device. */
- if (state == 0 && (inb(iobase + ESP_RINTR) & ESP_INTR_DC)) {
- return DISK_RET_ENOTREADY;
- }
+ if (state == 0) {
+ intr = inb(iobase + ESP_RINTR);
- /* HBA reads command, clears CD, sets TC -> do DMA if needed. */
- if (state == 0 && (stat & ESP_STAT_TC)) {
- state++;
- if (op->count && blocksize) {
- /* Data phase. */
- u32 count = (u32)op->count * blocksize;
- esp_scsi_dma(iobase, (u32)op->buf_fl, count, scsi_is_read(op));
- outb(ESP_CMD_TI | ESP_CMD_DMA, iobase + ESP_CMD);
- continue;
+ /* Detect disconnected device. */
+ if (intr & ESP_INTR_DC) {
+ return DISK_RET_ENOTREADY;
}
+
+ /* HBA reads command, executes it, sets BS/FC -> do DMA if needed.
*/
+ if (intr & (ESP_INTR_BS | ESP_INTR_FC)) {
+ state++;
+ if (op->count && blocksize) {
+ /* Data phase. */
+ u32 count = (u32)op->count * blocksize;
+ esp_scsi_dma(iobase, (u32)op->buf_fl, count,
scsi_is_read(op));
+ outb(ESP_CMD_TI | ESP_CMD_DMA, iobase + ESP_CMD);
+ continue;
+ }
+ }
}
/* At end of DMA TC is set again -> complete command. */
Reviewed-by: Paul Menzel <pmen...@molgen.mpg.de>
Thanks!
Kind regards,
Paul
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ATB,
Mark.
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