[clang] [RISCV] Fix incorrect check prefix in riscv32-toolchain.c and riscv64-toolchain.c. NFC. (PR #109390)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.


https://github.com/llvm/llvm-project/pull/109390
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[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/89051
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[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

> What's the status of backend support for the large code model? That would 
> presumably be a prerequisite to landing this.

It was just merged: https://github.com/llvm/llvm-project/pull/70308.

https://github.com/llvm/llvm-project/pull/107817
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[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

> @JinjinLi868 are you still working on this?

I can ask him. Is this PR blocking some of your works on float16/bf16?

https://github.com/llvm/llvm-project/pull/89051
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[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

[Pengcheng Wang via cfe-commits]

@@ -664,5 +664,9 @@ def FRM: RISCVReg<0, "frm">;
 // Shadow Stack register
 def SSP: RISCVReg<0, "ssp">;
 
-// Dummy VCIX state register
+// Dummy VCIX state register and its register class
 def VCIX_STATE : RISCVReg<0, "vcix_state">;
+def : RISCVRegisterClass<[XLenVT], 32, (add VCIX_STATE)> {

wangpc-pp wrote:

Why do we need a RegisterClass for it?

https://github.com/llvm/llvm-project/pull/106914
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[clang] [clang][RISCV] Remove `experimental` for vector crypto intrinsics (PR #106359)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/106359
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[clang] [clang][RISCV] Remove `experimental` for vector crypto intrinsics (PR #106359)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp commented:

Do we still need this?
```
def Experimental
   : SubtargetFeature<"experimental", "HasExperimental",
  "true", "Experimental intrinsics">;
```

https://github.com/llvm/llvm-project/pull/106359
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[clang] [RISCV] Simplify reserse fixed regs (PR #104736)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/104736
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[clang] [RISCV] Simplify reserse fixed regs (PR #104736)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/104736

>From d45743a893a44dbb5da75d3dbe40dfbd34c14e71 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Mon, 19 Aug 2024 12:07:00 +0800
Subject: [PATCH 1/2] [RISCV] Simplify reserse fixed regs

Add a macro to simplify some codes.
---
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 98 --
 1 file changed, 35 insertions(+), 63 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 149a31f58e75d2..914b9ae4bebe3d 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -95,69 +95,41 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const 
llvm::Triple &Triple,
   CPUFastVectorUnaligned = true;
   }
 
-  // Handle features corresponding to "-ffixed-X" options
-  if (Args.hasArg(options::OPT_ffixed_x1))
-Features.push_back("+reserve-x1");
-  if (Args.hasArg(options::OPT_ffixed_x2))
-Features.push_back("+reserve-x2");
-  if (Args.hasArg(options::OPT_ffixed_x3))
-Features.push_back("+reserve-x3");
-  if (Args.hasArg(options::OPT_ffixed_x4))
-Features.push_back("+reserve-x4");
-  if (Args.hasArg(options::OPT_ffixed_x5))
-Features.push_back("+reserve-x5");
-  if (Args.hasArg(options::OPT_ffixed_x6))
-Features.push_back("+reserve-x6");
-  if (Args.hasArg(options::OPT_ffixed_x7))
-Features.push_back("+reserve-x7");
-  if (Args.hasArg(options::OPT_ffixed_x8))
-Features.push_back("+reserve-x8");
-  if (Args.hasArg(options::OPT_ffixed_x9))
-Features.push_back("+reserve-x9");
-  if (Args.hasArg(options::OPT_ffixed_x10))
-Features.push_back("+reserve-x10");
-  if (Args.hasArg(options::OPT_ffixed_x11))
-Features.push_back("+reserve-x11");
-  if (Args.hasArg(options::OPT_ffixed_x12))
-Features.push_back("+reserve-x12");
-  if (Args.hasArg(options::OPT_ffixed_x13))
-Features.push_back("+reserve-x13");
-  if (Args.hasArg(options::OPT_ffixed_x14))
-Features.push_back("+reserve-x14");
-  if (Args.hasArg(options::OPT_ffixed_x15))
-Features.push_back("+reserve-x15");
-  if (Args.hasArg(options::OPT_ffixed_x16))
-Features.push_back("+reserve-x16");
-  if (Args.hasArg(options::OPT_ffixed_x17))
-Features.push_back("+reserve-x17");
-  if (Args.hasArg(options::OPT_ffixed_x18))
-Features.push_back("+reserve-x18");
-  if (Args.hasArg(options::OPT_ffixed_x19))
-Features.push_back("+reserve-x19");
-  if (Args.hasArg(options::OPT_ffixed_x20))
-Features.push_back("+reserve-x20");
-  if (Args.hasArg(options::OPT_ffixed_x21))
-Features.push_back("+reserve-x21");
-  if (Args.hasArg(options::OPT_ffixed_x22))
-Features.push_back("+reserve-x22");
-  if (Args.hasArg(options::OPT_ffixed_x23))
-Features.push_back("+reserve-x23");
-  if (Args.hasArg(options::OPT_ffixed_x24))
-Features.push_back("+reserve-x24");
-  if (Args.hasArg(options::OPT_ffixed_x25))
-Features.push_back("+reserve-x25");
-  if (Args.hasArg(options::OPT_ffixed_x26))
-Features.push_back("+reserve-x26");
-  if (Args.hasArg(options::OPT_ffixed_x27))
-Features.push_back("+reserve-x27");
-  if (Args.hasArg(options::OPT_ffixed_x28))
-Features.push_back("+reserve-x28");
-  if (Args.hasArg(options::OPT_ffixed_x29))
-Features.push_back("+reserve-x29");
-  if (Args.hasArg(options::OPT_ffixed_x30))
-Features.push_back("+reserve-x30");
-  if (Args.hasArg(options::OPT_ffixed_x31))
-Features.push_back("+reserve-x31");
+// Handle features corresponding to "-ffixed-X" options
+#define RESERVE_REG(REG)   
\
+  if (Args.hasArg(options::OPT_ffixed_##REG))  
\
+Features.push_back("+reserve-" #REG);
+  RESERVE_REG(x1)
+  RESERVE_REG(x2)
+  RESERVE_REG(x3)
+  RESERVE_REG(x4)
+  RESERVE_REG(x5)
+  RESERVE_REG(x6)
+  RESERVE_REG(x7)
+  RESERVE_REG(x8)
+  RESERVE_REG(x9)
+  RESERVE_REG(x10)
+  RESERVE_REG(x11)
+  RESERVE_REG(x12)
+  RESERVE_REG(x13)
+  RESERVE_REG(x14)
+  RESERVE_REG(x15)
+  RESERVE_REG(x16)
+  RESERVE_REG(x17)
+  RESERVE_REG(x18)
+  RESERVE_REG(x19)
+  RESERVE_REG(x20)
+  RESERVE_REG(x21)
+  RESERVE_REG(x22)
+  RESERVE_REG(x23)
+  RESERVE_REG(x24)
+  RESERVE_REG(x25)
+  RESERVE_REG(x26)
+  RESERVE_REG(x27)
+  RESERVE_REG(x28)
+  RESERVE_REG(x29)
+  RESERVE_REG(x30)
+  RESERVE_REG(x31)
 
   // -mrelax is default, unless -mno-relax is specified.
   if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true)) {

>From 14120fecdd921972502a826b9b7c9d44968b50ec Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Mon, 19 Aug 2024 14:02:13 +0800
Subject: [PATCH 2/2] Undef RESERVE_REG

---
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 914b9ae4bebe3d..6935904a24edbf 100644
--- a/clang/lib/Driver/ToolChains/Arch/RIS

[clang] [RISCV] Simplify reserse fixed regs (PR #104736)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/104736

Add a macro to simplify some codes.


>From d45743a893a44dbb5da75d3dbe40dfbd34c14e71 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Mon, 19 Aug 2024 12:07:00 +0800
Subject: [PATCH] [RISCV] Simplify reserse fixed regs

Add a macro to simplify some codes.
---
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 98 --
 1 file changed, 35 insertions(+), 63 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 149a31f58e75d2..914b9ae4bebe3d 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -95,69 +95,41 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const 
llvm::Triple &Triple,
   CPUFastVectorUnaligned = true;
   }
 
-  // Handle features corresponding to "-ffixed-X" options
-  if (Args.hasArg(options::OPT_ffixed_x1))
-Features.push_back("+reserve-x1");
-  if (Args.hasArg(options::OPT_ffixed_x2))
-Features.push_back("+reserve-x2");
-  if (Args.hasArg(options::OPT_ffixed_x3))
-Features.push_back("+reserve-x3");
-  if (Args.hasArg(options::OPT_ffixed_x4))
-Features.push_back("+reserve-x4");
-  if (Args.hasArg(options::OPT_ffixed_x5))
-Features.push_back("+reserve-x5");
-  if (Args.hasArg(options::OPT_ffixed_x6))
-Features.push_back("+reserve-x6");
-  if (Args.hasArg(options::OPT_ffixed_x7))
-Features.push_back("+reserve-x7");
-  if (Args.hasArg(options::OPT_ffixed_x8))
-Features.push_back("+reserve-x8");
-  if (Args.hasArg(options::OPT_ffixed_x9))
-Features.push_back("+reserve-x9");
-  if (Args.hasArg(options::OPT_ffixed_x10))
-Features.push_back("+reserve-x10");
-  if (Args.hasArg(options::OPT_ffixed_x11))
-Features.push_back("+reserve-x11");
-  if (Args.hasArg(options::OPT_ffixed_x12))
-Features.push_back("+reserve-x12");
-  if (Args.hasArg(options::OPT_ffixed_x13))
-Features.push_back("+reserve-x13");
-  if (Args.hasArg(options::OPT_ffixed_x14))
-Features.push_back("+reserve-x14");
-  if (Args.hasArg(options::OPT_ffixed_x15))
-Features.push_back("+reserve-x15");
-  if (Args.hasArg(options::OPT_ffixed_x16))
-Features.push_back("+reserve-x16");
-  if (Args.hasArg(options::OPT_ffixed_x17))
-Features.push_back("+reserve-x17");
-  if (Args.hasArg(options::OPT_ffixed_x18))
-Features.push_back("+reserve-x18");
-  if (Args.hasArg(options::OPT_ffixed_x19))
-Features.push_back("+reserve-x19");
-  if (Args.hasArg(options::OPT_ffixed_x20))
-Features.push_back("+reserve-x20");
-  if (Args.hasArg(options::OPT_ffixed_x21))
-Features.push_back("+reserve-x21");
-  if (Args.hasArg(options::OPT_ffixed_x22))
-Features.push_back("+reserve-x22");
-  if (Args.hasArg(options::OPT_ffixed_x23))
-Features.push_back("+reserve-x23");
-  if (Args.hasArg(options::OPT_ffixed_x24))
-Features.push_back("+reserve-x24");
-  if (Args.hasArg(options::OPT_ffixed_x25))
-Features.push_back("+reserve-x25");
-  if (Args.hasArg(options::OPT_ffixed_x26))
-Features.push_back("+reserve-x26");
-  if (Args.hasArg(options::OPT_ffixed_x27))
-Features.push_back("+reserve-x27");
-  if (Args.hasArg(options::OPT_ffixed_x28))
-Features.push_back("+reserve-x28");
-  if (Args.hasArg(options::OPT_ffixed_x29))
-Features.push_back("+reserve-x29");
-  if (Args.hasArg(options::OPT_ffixed_x30))
-Features.push_back("+reserve-x30");
-  if (Args.hasArg(options::OPT_ffixed_x31))
-Features.push_back("+reserve-x31");
+// Handle features corresponding to "-ffixed-X" options
+#define RESERVE_REG(REG)   
\
+  if (Args.hasArg(options::OPT_ffixed_##REG))  
\
+Features.push_back("+reserve-" #REG);
+  RESERVE_REG(x1)
+  RESERVE_REG(x2)
+  RESERVE_REG(x3)
+  RESERVE_REG(x4)
+  RESERVE_REG(x5)
+  RESERVE_REG(x6)
+  RESERVE_REG(x7)
+  RESERVE_REG(x8)
+  RESERVE_REG(x9)
+  RESERVE_REG(x10)
+  RESERVE_REG(x11)
+  RESERVE_REG(x12)
+  RESERVE_REG(x13)
+  RESERVE_REG(x14)
+  RESERVE_REG(x15)
+  RESERVE_REG(x16)
+  RESERVE_REG(x17)
+  RESERVE_REG(x18)
+  RESERVE_REG(x19)
+  RESERVE_REG(x20)
+  RESERVE_REG(x21)
+  RESERVE_REG(x22)
+  RESERVE_REG(x23)
+  RESERVE_REG(x24)
+  RESERVE_REG(x25)
+  RESERVE_REG(x26)
+  RESERVE_REG(x27)
+  RESERVE_REG(x28)
+  RESERVE_REG(x29)
+  RESERVE_REG(x30)
+  RESERVE_REG(x31)
 
   // -mrelax is default, unless -mno-relax is specified.
   if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true)) {

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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/103709

>From 0330ffdcd0ff0230ef8ba7fac5eff5874ba2e544 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Wed, 14 Aug 2024 15:14:36 +0800
Subject: [PATCH 1/2] [RISCV][MC] Support experimental extensions Zvbc32e and
 Zvkgs

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.
---
 .../Driver/print-supported-extensions-riscv.c |  2 ++
 .../test/Preprocessor/riscv-target-features.c | 18 
 llvm/docs/RISCVUsage.rst  |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td| 19 +
 llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td| 12 +--
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  9 ++--
 llvm/test/CodeGen/RISCV/attributes.ll |  8 +++
 llvm/test/MC/RISCV/rvv/zvbc.s | 17 +++
 llvm/test/MC/RISCV/rvv/zvkgs.s| 21 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  2 ++
 10 files changed, 103 insertions(+), 8 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rvv/zvkgs.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 91f12b8416b2a4..132422393170a9 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -172,6 +172,8 @@
 // CHECK-NEXT: zicfiss  1.0   'Zicfiss' (Shadow stack)
 // CHECK-NEXT: zacas1.0   'Zacas' (Atomic 
Compare-And-Swap Instructions)
 // CHECK-NEXT: zalasr   0.1   'Zalasr' (Load-Acquire and 
Store-Release Instructions)
+// CHECK-NEXT: zvbc32e  0.7   'Zvbc32e' (Vector Carryless 
Multiplication with 32-bits elements)
+// CHECK-NEXT: zvkgs0.7   'Zvkgs' (Vector-Scalar GCM 
instructions for Cryptography)
 // CHECK-NEXT: smmpm1.0   'Smmpm' (Machine-level 
Pointer Masking for M-mode)
 // CHECK-NEXT: smnpm1.0   'Smnpm' (Machine-level 
Pointer Masking for next lower privilege mode)
 // CHECK-NEXT: ssnpm1.0   'Ssnpm' (Supervisor-level 
Pointer Masking for next lower privilege mode)
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 72131108cb5f6a..517702fab5b919 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -187,8 +187,10 @@
 // CHECK-NOT: __riscv_zicfilp {{.*$}}
 // CHECK-NOT: __riscv_zicfiss {{.*$}}
 // CHECK-NOT: __riscv_ztso {{.*$}}
+// CHECK-NOT: __riscv_zvbc32e {{.*$}}
 // CHECK-NOT: __riscv_zvfbfmin {{.*$}}
 // CHECK-NOT: __riscv_zvfbfwma {{.*$}}
+// CHECK-NOT: __riscv_zvkgs {{.*$}}
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ia -E -dM %s \
@@ -1658,6 +1660,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
 // CHECK-ZTSO-EXT: __riscv_ztso 100{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvbc32e0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
+// CHECK-ZVBC32E-EXT: __riscv_zvbc32e 7000{{$}}
+
 // RUN: %clang --target=riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32ifzvfbfmin1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
@@ -1674,6 +1684,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
 // CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 100{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvkgs0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvkgs0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
+// CHECK-ZVKGS-EXT: __riscv_zvkgs 7000{{$}}
+
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32izicfiss1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index b3c7b0e3883d01..3af1428138c021 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``experimental-zicfilp``, ``experimental-zicfiss``
   LLVM implements the `1.0 release specification 
`__.
 
+``experimental-zvbc32e``, ``experimen

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/103709

>From 0bdc302fb5b4dd7369d2f16a6da32412adbe7d7f Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Wed, 14 Aug 2024 15:14:36 +0800
Subject: [PATCH 1/2] [RISCV][MC] Support experimental extensions Zvbc32e and
 Zvkgs

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.
---
 .../Driver/print-supported-extensions-riscv.c |  2 ++
 .../test/Preprocessor/riscv-target-features.c | 18 
 llvm/docs/RISCVUsage.rst  |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td| 19 +
 llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td| 12 +--
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  9 ++--
 llvm/test/CodeGen/RISCV/attributes.ll |  8 +++
 llvm/test/MC/RISCV/rvv/zvbc.s | 17 +++
 llvm/test/MC/RISCV/rvv/zvkgs.s| 21 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  2 ++
 10 files changed, 103 insertions(+), 8 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rvv/zvkgs.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 91f12b8416b2a4..132422393170a9 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -172,6 +172,8 @@
 // CHECK-NEXT: zicfiss  1.0   'Zicfiss' (Shadow stack)
 // CHECK-NEXT: zacas1.0   'Zacas' (Atomic 
Compare-And-Swap Instructions)
 // CHECK-NEXT: zalasr   0.1   'Zalasr' (Load-Acquire and 
Store-Release Instructions)
+// CHECK-NEXT: zvbc32e  0.7   'Zvbc32e' (Vector Carryless 
Multiplication with 32-bits elements)
+// CHECK-NEXT: zvkgs0.7   'Zvkgs' (Vector-Scalar GCM 
instructions for Cryptography)
 // CHECK-NEXT: smmpm1.0   'Smmpm' (Machine-level 
Pointer Masking for M-mode)
 // CHECK-NEXT: smnpm1.0   'Smnpm' (Machine-level 
Pointer Masking for next lower privilege mode)
 // CHECK-NEXT: ssnpm1.0   'Ssnpm' (Supervisor-level 
Pointer Masking for next lower privilege mode)
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 72131108cb5f6a..517702fab5b919 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -187,8 +187,10 @@
 // CHECK-NOT: __riscv_zicfilp {{.*$}}
 // CHECK-NOT: __riscv_zicfiss {{.*$}}
 // CHECK-NOT: __riscv_ztso {{.*$}}
+// CHECK-NOT: __riscv_zvbc32e {{.*$}}
 // CHECK-NOT: __riscv_zvfbfmin {{.*$}}
 // CHECK-NOT: __riscv_zvfbfwma {{.*$}}
+// CHECK-NOT: __riscv_zvkgs {{.*$}}
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ia -E -dM %s \
@@ -1658,6 +1660,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
 // CHECK-ZTSO-EXT: __riscv_ztso 100{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvbc32e0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
+// CHECK-ZVBC32E-EXT: __riscv_zvbc32e 7000{{$}}
+
 // RUN: %clang --target=riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32ifzvfbfmin1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
@@ -1674,6 +1684,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
 // CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 100{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvkgs0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvkgs0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
+// CHECK-ZVKGS-EXT: __riscv_zvkgs 7000{{$}}
+
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32izicfiss1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index b3c7b0e3883d01..3af1428138c021 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``experimental-zicfilp``, ``experimental-zicfiss``
   LLVM implements the `1.0 release specification 
`__.
 
+``experimental-zvbc32e``, ``experimen

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

@@ -754,6 +754,17 @@ def HasStdExtZvbc : 
Predicate<"Subtarget->hasStdExtZvbc()">,
 AssemblerPredicate<(all_of FeatureStdExtZvbc),
 "'Zvbc' (Vector Carryless Multiplication)">;
 
+def FeatureStdExtZvbc32e
+: RISCVExperimentalExtension<"zvbc32e", 0, 7,
+ "'Zvbc32e' (Vector Carryless Multiplication 
with 32-bits elements)">;
+def HasStdExtZvbc32e : Predicate<"Subtarget->hasStdExtZvbc32e()">,

wangpc-pp wrote:

Currently no, I will remove it.

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = 
NoConstraint in {
  SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
 } // Predicates = [HasStdExtZvkg]
 
+let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

wangpc-pp wrote:

I made a comment in https://github.com/riscv/riscv-isa-manual/pull/1306. We may 
not need this constraint to keep the consistency between `.vv` and `.vs`.

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = 
NoConstraint in {
  SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
 } // Predicates = [HasStdExtZvkg]
 
+let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

wangpc-pp wrote:

Why? I was thinking it should be the same case?

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/102155
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = 
NoConstraint in {
  SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
 } // Predicates = [HasStdExtZvkg]
 
+let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

wangpc-pp wrote:

Oops, I think we should set this for `vghsh.vv` and `vgmul.vv` as well. cc 
@4vtomat 

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

@@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``experimental-zicfilp``, ``experimental-zicfiss``
   LLVM implements the `1.0 release specification 
`__.
 
+``experimental-zvbc32e``, ``experimental-zvkgs``
+  LLVM implements the `0.7 release specification 
`__.

wangpc-pp wrote:

Actually, there is no repo&tag. They are in a pull request.

https://github.com/llvm/llvm-project/pull/103709
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/103709

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.


>From 0bdc302fb5b4dd7369d2f16a6da32412adbe7d7f Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Wed, 14 Aug 2024 15:14:36 +0800
Subject: [PATCH] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs

These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.

Please see https://github.com/riscv/riscv-isa-manual/pull/1306.
---
 .../Driver/print-supported-extensions-riscv.c |  2 ++
 .../test/Preprocessor/riscv-target-features.c | 18 
 llvm/docs/RISCVUsage.rst  |  3 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td| 19 +
 llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td| 12 +--
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  9 ++--
 llvm/test/CodeGen/RISCV/attributes.ll |  8 +++
 llvm/test/MC/RISCV/rvv/zvbc.s | 17 +++
 llvm/test/MC/RISCV/rvv/zvkgs.s| 21 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  2 ++
 10 files changed, 103 insertions(+), 8 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rvv/zvkgs.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 91f12b8416b2a4..132422393170a9 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -172,6 +172,8 @@
 // CHECK-NEXT: zicfiss  1.0   'Zicfiss' (Shadow stack)
 // CHECK-NEXT: zacas1.0   'Zacas' (Atomic 
Compare-And-Swap Instructions)
 // CHECK-NEXT: zalasr   0.1   'Zalasr' (Load-Acquire and 
Store-Release Instructions)
+// CHECK-NEXT: zvbc32e  0.7   'Zvbc32e' (Vector Carryless 
Multiplication with 32-bits elements)
+// CHECK-NEXT: zvkgs0.7   'Zvkgs' (Vector-Scalar GCM 
instructions for Cryptography)
 // CHECK-NEXT: smmpm1.0   'Smmpm' (Machine-level 
Pointer Masking for M-mode)
 // CHECK-NEXT: smnpm1.0   'Smnpm' (Machine-level 
Pointer Masking for next lower privilege mode)
 // CHECK-NEXT: ssnpm1.0   'Ssnpm' (Supervisor-level 
Pointer Masking for next lower privilege mode)
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 72131108cb5f6a..517702fab5b919 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -187,8 +187,10 @@
 // CHECK-NOT: __riscv_zicfilp {{.*$}}
 // CHECK-NOT: __riscv_zicfiss {{.*$}}
 // CHECK-NOT: __riscv_ztso {{.*$}}
+// CHECK-NOT: __riscv_zvbc32e {{.*$}}
 // CHECK-NOT: __riscv_zvfbfmin {{.*$}}
 // CHECK-NOT: __riscv_zvfbfwma {{.*$}}
+// CHECK-NOT: __riscv_zvkgs {{.*$}}
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ia -E -dM %s \
@@ -1658,6 +1660,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
 // CHECK-ZTSO-EXT: __riscv_ztso 100{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvbc32e0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
+// CHECK-ZVBC32E-EXT: __riscv_zvbc32e 7000{{$}}
+
 // RUN: %clang --target=riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32ifzvfbfmin1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
@@ -1674,6 +1684,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
 // CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 100{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvkgs0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvkgs0p7 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
+// CHECK-ZVKGS-EXT: __riscv_zvkgs 7000{{$}}
+
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32izicfiss1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index b3c7b0e3883d01..3af1428138c021 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``ex

[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

[Pengcheng Wang via cfe-commits]

@@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith  = SiFiveP400FEXQ0;
 defvar SiFiveP400F2I  = SiFiveP400FEXQ0;
 def SiFiveP400FloatDiv: ProcResource<1>;
 
+// Vector pipeline
+def SiFiveP400VEXQ0: ProcResource<1>;

wangpc-pp wrote:

So there is 1 vector pipeline? Is it OK to model VLD/VST/VDiv/VFloatDiv as 
standalone resources?

https://github.com/llvm/llvm-project/pull/102155
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[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

[Pengcheng Wang via cfe-commits]

@@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith  = SiFiveP400FEXQ0;
 defvar SiFiveP400F2I  = SiFiveP400FEXQ0;
 def SiFiveP400FloatDiv: ProcResource<1>;
 
+// Vector pipeline
+def SiFiveP400VEXQ0: ProcResource<1>;

wangpc-pp wrote:

`EXQ0` means `execution queue 0`? But it seems there is no second unit and all 
arithmetic operations are executed on this unit (not a quene?).

https://github.com/llvm/llvm-project/pull/102155
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[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/102022
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[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

[Pengcheng Wang via cfe-commits]

@@ -304,6 +304,16 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck 
-check-prefix=MCPU-SIFIVE-P470 %s
+// MCPU-SIFIVE-P470: "-target-cpu" "sifive-p470"

wangpc-pp wrote:

One feature one line please. :-)

https://github.com/llvm/llvm-project/pull/102022
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[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

[Pengcheng Wang via cfe-commits]

@@ -1371,7 +1371,6 @@ def NoConditionalMoveFusion  : 
Predicate<"!Subtarget->hasConditionalMoveFusion()
 
 def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
"SiFive 7-Series processors">;
-

wangpc-pp wrote:

Removed by accident?

https://github.com/llvm/llvm-project/pull/102022
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[clang] [RISCV][clang] Remove unused base type in `vfncvt` (PR #101646)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

Make sense to me.
(Do we have a way to test these generated builtins?)

https://github.com/llvm/llvm-project/pull/101646
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[clang] [RISCV][NFC] Remove unneeded defining name of `vundefined` (PR #101643)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp commented:

I don't think this will be better. We may keep these names so that these code 
can be self-explanatory.

https://github.com/llvm/llvm-project/pull/101643
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[libunwind] [RISCV] Allow libunwind to build for rv32e (PR #98855)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.


https://github.com/llvm/llvm-project/pull/98855
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[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/101321
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[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

[Pengcheng Wang via cfe-commits]

@@ -106,6 +106,7 @@ Changes to the RISC-V Backend
 * `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
   the required alignment space with a sequence of `0x0` bytes (the requested
   fill value) rather than NOPs.
+* Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64``

wangpc-pp wrote:

This should be in `clang/docs/ReleaseNotes.rst` not llvm?

https://github.com/llvm/llvm-project/pull/101321
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[clang] [NFC][clang] Fix typo of `riscv_rvv_vector_bits` in AttrDocs (PR #101046)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.


https://github.com/llvm/llvm-project/pull/101046
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

[Pengcheng Wang via cfe-commits]

@@ -290,8 +290,24 @@ std::string riscv::getRISCVArch(const llvm::opt::ArgList 
&Args,
   // 2. Get march (isa string) based on `-mcpu=`
   if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
 StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "native") {
   CPU = llvm::sys::getHostCPUName();
+  // If the target cpu is unrecognized, use target features.
+  if (CPU.empty() || CPU.starts_with("generic")) {

wangpc-pp wrote:

I think `CPU` will never be empty now?

https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add QingKe "XW" compressed opcode extension (PR #97925)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/97925
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[clang] [llvm] [RISCV] Remove experimental for bf16 extensions (PR #97996)

[Pengcheng Wang via cfe-commits]

@@ -271,7 +271,7 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``experimental-zalasr``
   LLVM implements the `0.0.5 draft specification 
`__.
 
-``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
+``zfbfmin``, ``zvfbfmin``, ``zvfbfwma``

wangpc-pp wrote:

We should not just remove the `experimental` prefix, these extensions still 
belong to `Experimental Extensions` section.

https://github.com/llvm/llvm-project/pull/97996
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[clang] [libcxx] [llvm] [mlir] [openmp] [CodeGen] Add dump() to MachineTraceMetrics.h (PR #97799)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/97799
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[clang] [libcxx] [llvm] [mlir] [openmp] [CodeGen] Add dump() to MachineTraceMetrics.h (PR #97799)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/97799
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[clang] [llvm] [RISCV] Remove SeenExtMap from RISCVISAInfo::parseArchString. (PR #97506)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/97506
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[clang] [llvm] [RISCV] Remove SeenExtMap from RISCVISAInfo::parseArchString. (PR #97506)

[Pengcheng Wang via cfe-commits]

@@ -306,7 +306,7 @@
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_ -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s
 // RV32-XSEP: error: invalid arch name 'rv32ixabc_',
-// RV32-XSEP: extension name missing after separator '_'
+// RV32-XSEP: unsupported non-standard user-level extension 'xabc'

wangpc-pp wrote:

So there is no test coverage for `extension name missing after separator` now? 
Or is this error in a dead code path now?

https://github.com/llvm/llvm-project/pull/97506
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[clang] [clang-tools-extra] [llvm] [NFC][RISCV] Simplify the dynamic linker construction logic (PR #97383)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/97383
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[clang] [clang-tools-extra] [llvm] [NFC][RISCV] Simplify the dynamic linker construction logic (PR #97383)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/97383
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[clang] [clang] Default to -fno-sized-deallocation for AIX (PR #97076)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/97076
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

[Pengcheng Wang via cfe-commits]

@@ -83,8 +83,14 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const 
llvm::Triple &Triple,
   // and other features (ex. mirco architecture feature) from mcpu
   if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
 StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "native") {
   CPU = llvm::sys::getHostCPUName();
+  llvm::StringMap HostFeatures;
+  if (llvm::sys::getHostCPUFeatures(HostFeatures))
+for (auto &F : HostFeatures)
+  Features.push_back(
+  Args.MakeArgString((F.second ? "+" : "-") + F.first()));
+}

wangpc-pp wrote:

> @wangpc-pp @topperc Are there any equivalents of the helper `printMArch`?

No, I think there isn't. You may need to write a helper via 
`RISCVISAInfo::parseFeatures` and `RISCVISAInfo::toString()`.


https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/96465
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[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)

[Pengcheng Wang via cfe-commits]

@@ -365,24 +365,30 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -### %s \

wangpc-pp wrote:

Does this mean we should change this when `Zalasr` is no longer experimental?
(Thought I think we don't have a way to avoid this, we will always need an 
experimental extension here)

https://github.com/llvm/llvm-project/pull/96465
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[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/96465
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[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/96465
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

> I have no idea about why it corrupts StringMap. Sad :(
> 
> ![image](https://private-user-images.githubusercontent.com/15650457/341986439-fd427068-6ca0-4ecb-a340-48c51e5629a6.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MTkyMTE0NzgsIm5iZiI6MTcxOTIxMTE3OCwicGF0aCI6Ii8xNTY1MDQ1Ny8zNDE5ODY0MzktZmQ0MjcwNjgtNmNhMC00ZWNiLWEzNDAtNDhjNTFlNTYyOWE2LnBuZz9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA2MjQlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwNjI0VDA2MzkzOFomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPWQ3MzBjMmIwNGNhYmM3NmZiNjJiZWFmMTRhNmQ3MWM1Y2I4NGE2NGFjY2RhZDIwNGJmN2Q2MzUyYmI5NzI2OTgmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.z46AIxQBdVWJ2Z6xGXCA_5v54-NU9KwydxMTUHXxuRo)

Is this fixed after fixing the return statement? This may be caused by the 
corruption of `getHostCPUNameForRISCV`.

https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

[Pengcheng Wang via cfe-commits]

@@ -1571,7 +1571,9 @@ StringRef sys::getHostCPUName() {
 #if defined(__linux__)
   std::unique_ptr P = getProcCpuinfoContent();
   StringRef Content = P ? P->getBuffer() : "";
-  return detail::getHostCPUNameForRISCV(Content);
+  StringRef Name = detail::getHostCPUNameForRISCV(Content);
+  if (!Name.empty())
+return Name;

wangpc-pp wrote:

No return statement in the `else` case.

https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs builtins (PR #96283)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/96283

`riscv_atomic.h` contains all builtins for atomics.

Currently, we suppoprt builtins for Zawrs extension.

Doc: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/79


>From 4b597ebf69de59d62e5587a27cedf2b12e831763 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Fri, 21 Jun 2024 16:09:13 +0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
 =?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/include/clang/Basic/BuiltinsRISCV.td|  8 
 clang/lib/CodeGen/CGBuiltin.cpp   |  8 
 clang/lib/Headers/CMakeLists.txt  |  1 +
 clang/lib/Headers/riscv_atomic.h  | 18 
 .../CodeGen/RISCV/atomics-intrinsics/zawrs.c  | 42 +++
 llvm/include/llvm/IR/IntrinsicsRISCV.td   | 10 +
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td |  5 ++-
 llvm/test/CodeGen/RISCV/zawrs-intrinsic.ll| 33 +++
 8 files changed, 124 insertions(+), 1 deletion(-)
 create mode 100644 clang/lib/Headers/riscv_atomic.h
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
 create mode 100644 llvm/test/CodeGen/RISCV/zawrs-intrinsic.ll

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td 
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..429f1356aa5fd 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,11 @@ let Features = "zihintntl", Attributes = 
[CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2516ed4508242..1e130cad6d00d 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21834,6 +21834,14 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
 ID = Intrinsic::riscv_sm3p1;
 break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
 llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 89fa0ecd45eb4..f8f430e6921cb 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomic.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomic.h b/clang/lib/Headers/riscv_atomic.h
new file mode 100644
index 0..4c548bdfa8253
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomic.h
@@ -0,0 +1,18 @@
+/*=== riscv_atomic.h - RISC-V atomic intrinsics ===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __RISCV_ATOMIC_H
+#define __RISCV_ATOMIC_H
+
+#ifdef __riscv_zawrs
+#define __riscv_wrs_nto __builtin_riscv_wrs_nto
+#define __riscv_wrs_sto __builtin_riscv_wrs_sto
+#endif
+
+#endif
diff --git a/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c 
b/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
new file mode 100644
index 0..e3d4899244ca4
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zawrs -disable-O0-optnone \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefixes=CHECK-RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zawrs -disable-O0-optnone \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV32-LABEL: define dso_local void @zawrs_nto
+// CHECK-RV32-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:call void @llvm.riscv.wrs.nto()
+// CHECK-RV32-NEXT:ret void
+//
+// CHECK-RV64-LABEL: define dso_local void @zawrs_nto
+// CHECK-RV64-SAME

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.


https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM with nits.

https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Pengcheng Wang via cfe-commits]

@@ -358,3 +358,21 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
+// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-abi" "ilp32"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV32 %s
+// MTUNE-SYNTACORE-SCR3-RV32: "-tune-cpu" "syntacore-scr3-rv32"

wangpc-pp wrote:

I think we don't need to test this, but I don't have a strong opinion here.

https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Pengcheng Wang via cfe-commits]

@@ -358,3 +358,21 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
+// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+m" "-target-feature" "+c"

wangpc-pp wrote:

One `-target-feature` one line please.

https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/95953
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Pengcheng Wang via cfe-commits]

@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : 
RISCVProcessorModel<"xiangshan-nanhu",
 TuneZExtHFusion,
 TuneZExtWFusion,
 TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+   NoSchedModel,
+   !listconcat(RVA22S64Features,

wangpc-pp wrote:

I think you can just add `RVA22S64` feature here, no `!listconcat` is needed as 
profiles are subtarget features now.
```
[RVI20U32,
 FeatureStdExtV,
 FeatureStdExtSscofpmf,
 ...
```

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/94564
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[clang] [clang-tools-extra] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/94313
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[clang] [clang-tools-extra] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/94313
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From 9ab05b9f68def57e9abb9d5ac65293b84aacc95a Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c   |  5 -
 clang/test/Preprocessor/riscv-target-features.c  | 12 
 llvm/docs/RISCVUsage.rst |  1 +
 llvm/docs/ReleaseNotes.rst   |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td   |  8 
 llvm/test/CodeGen/RISCV/attributes.ll|  4 
 llvm/unittests/TargetParser/RISCVISAInfoTest.cpp |  9 ++---
 7 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ddf617bbb6237..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 09b9ad0a160bb..91307141e0406 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,17 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 35115e67ecf92..ef06f80c747f9 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 8cdb9db087c77..b46994bbcd66d 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -152,6 +152,7 @@ Changes to the RISC-V Backend
 * Zaamo and Zalrsc are no longer experimental.
 * Processors that enable post reg-alloc scheduling (PostMachineScheduler) by 
default should use the `UsePostRAScheduler` subtarget feature. Setting 
`PostRAScheduler = 1` in the scheduler model will have no effect on the 
enabling of the PostMachineScheduler.
 * Zabha is no longer experimental.
+* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9bf06850483d8..011edca019fd6 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: RISCVExtension<"b", 1, 0,
+ "'B' (the collection of the Zba, Zbb, Zbs extensions)",
+ [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
+def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
+   AssemblerPredicate<(all_of FeatureStdExtB),
+   "'B' (the collection of the Zba, Zbb, Zbs 
extensions)">;
+
 def FeatureStdExtZbkb
 : RISCVExtension<"zbkb", 1, 0,
  "'Z

[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

[Pengcheng Wang via cfe-commits]

@@ -86,8 +86,14 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const 
llvm::Triple &Triple,
   // and other features (ex. mirco architecture feature) from mcpu
   if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
 StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "native") {
   CPU = llvm::sys::getHostCPUName();
+  llvm::StringMap HostFeatures;
+  if (llvm::sys::getHostCPUFeatures(HostFeatures))

wangpc-pp wrote:

Open discussion here: `CPU` may fail and return `generic`. Should we failback 
to use `getHostCPUFeatures` if `getHostCPUName` fails? Or we should use 
`getHostCPUFeatures` all the time?

https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

If we are talking about the necessariness of adding these intrinsics, please 
refer to the ARM implementations in DPDK 
(https://github.com/DPDK/dpdk/blob/76cef1af8bdaeaf67a5c4ca5df3f221df994dc46/lib/eal/arm/include/rte_pause_64.h).We
 want to use 

https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

> lr/sc builtins are extremely fragile: there's no reasonable way for the 
> compiler to guarantee that the sc is placed in such a way that it will 
> eventually succeed.

I think the user should have enough knowledges about lr/sc to make the logic 
reasonable. If we don't provide these intrinsics, the user who wants to 
implement custom locks will use inline assemly instead.

>  (The equivalent intrinsics do exist on ARM, but ARM has significantly 
> stronger guarantees here. Even then, it's not completely reliable.)

I don't know much about there intrinsics on ARM, what are the `stronger 
guarantees`?

https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

The description needs to be revised.

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/94578

>From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Thu, 6 Jun 2024 13:48:34 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/include/clang/Basic/BuiltinsRISCV.td|  18 ++
 clang/lib/CodeGen/CGBuiltin.cpp   |  22 ++
 clang/lib/Headers/CMakeLists.txt  |   1 +
 clang/lib/Headers/riscv_atomics.h |  36 +++
 clang/lib/Sema/SemaRISCV.cpp  |  10 +-
 .../RISCV/atomics-intrinsics/zalrsc-error.c   |  13 +
 .../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 222 ++
 .../CodeGen/RISCV/atomics-intrinsics/zawrs.c  |  42 
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  32 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoA.td  |  25 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td |   5 +-
 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll|  74 ++
 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll|  74 ++
 llvm/test/CodeGen/RISCV/zawrs.ll  |  33 +++
 14 files changed, 605 insertions(+), 2 deletions(-)
 create mode 100644 clang/lib/Headers/riscv_atomics.h
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zawrs.ll

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td 
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..458c755179417 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,21 @@ let Features = "zihintntl", Attributes = 
[CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
+
+//===--===//
+// Zalrsc extension.
+//===--===//
+let Features = "zalrsc" in {
+def lr_w : RISCVBuiltin<"int(int *, _Constant unsigned int)">;
+def lr_d : RISCVBuiltin<"int64_t(int64_t *, _Constant unsigned int)">;
+def sc_w : RISCVBuiltin<"int(int, int *, _Constant unsigned int)">;
+def sc_d : RISCVBuiltin<"int64_t(int64_t, int64_t *, _Constant unsigned int)">;
+} // Features = "zalrsc"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 37d0c478e0330..db48c69e10c86 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21769,6 +21769,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
 ID = Intrinsic::riscv_sm3p1;
 break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
+  // Zalrsc
+  case RISCV::BI__builtin_riscv_lr_w:
+ID = Intrinsic::riscv_lr_w;
+break;
+  case RISCV::BI__builtin_riscv_lr_d:
+ID = Intrinsic::riscv_lr_d;
+break;
+  case RISCV::BI__builtin_riscv_sc_w:
+ID = Intrinsic::riscv_sc_w;
+break;
+  case RISCV::BI__builtin_riscv_sc_d:
+ID = Intrinsic::riscv_sc_d;
+break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
 llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index d3090e488306f..cf2fbf1893772 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomics.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h 
b/clang/lib/Headers/riscv_atomics.h
new file mode 100644
index 0..35db57fe36131
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomics.h
@@ -0,0 +1,36 @@
+/*=== riscv_atomics.h - RISC-V atomics intrinsics --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===--

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/94578

>From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Thu, 6 Jun 2024 13:48:34 +0800
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/include/clang/Basic/BuiltinsRISCV.td|  18 ++
 clang/lib/CodeGen/CGBuiltin.cpp   |  22 ++
 clang/lib/Headers/CMakeLists.txt  |   1 +
 clang/lib/Headers/riscv_atomics.h |  36 +++
 clang/lib/Sema/SemaRISCV.cpp  |  10 +-
 .../RISCV/atomics-intrinsics/zalrsc-error.c   |  13 +
 .../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 222 ++
 .../CodeGen/RISCV/atomics-intrinsics/zawrs.c  |  42 
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  32 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoA.td  |  25 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td |   5 +-
 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll|  74 ++
 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll|  74 ++
 llvm/test/CodeGen/RISCV/zawrs.ll  |  33 +++
 14 files changed, 605 insertions(+), 2 deletions(-)
 create mode 100644 clang/lib/Headers/riscv_atomics.h
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zawrs.ll

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td 
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..458c755179417 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,21 @@ let Features = "zihintntl", Attributes = 
[CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
+
+//===--===//
+// Zalrsc extension.
+//===--===//
+let Features = "zalrsc" in {
+def lr_w : RISCVBuiltin<"int(int *, _Constant unsigned int)">;
+def lr_d : RISCVBuiltin<"int64_t(int64_t *, _Constant unsigned int)">;
+def sc_w : RISCVBuiltin<"int(int, int *, _Constant unsigned int)">;
+def sc_d : RISCVBuiltin<"int64_t(int64_t, int64_t *, _Constant unsigned int)">;
+} // Features = "zalrsc"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 37d0c478e0330..db48c69e10c86 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21769,6 +21769,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
 ID = Intrinsic::riscv_sm3p1;
 break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
+  // Zalrsc
+  case RISCV::BI__builtin_riscv_lr_w:
+ID = Intrinsic::riscv_lr_w;
+break;
+  case RISCV::BI__builtin_riscv_lr_d:
+ID = Intrinsic::riscv_lr_d;
+break;
+  case RISCV::BI__builtin_riscv_sc_w:
+ID = Intrinsic::riscv_sc_w;
+break;
+  case RISCV::BI__builtin_riscv_sc_d:
+ID = Intrinsic::riscv_sc_d;
+break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
 llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index d3090e488306f..cf2fbf1893772 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomics.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h 
b/clang/lib/Headers/riscv_atomics.h
new file mode 100644
index 0..35db57fe36131
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomics.h
@@ -0,0 +1,36 @@
+/*=== riscv_atomics.h - RISC-V atomics intrinsics --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===--

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp unassigned 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp unassigned 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp ready_for_review 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/94578

>From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Thu, 6 Jun 2024 13:48:34 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/include/clang/Basic/BuiltinsRISCV.td|  18 ++
 clang/lib/CodeGen/CGBuiltin.cpp   |  22 ++
 clang/lib/Headers/CMakeLists.txt  |   1 +
 clang/lib/Headers/riscv_atomics.h |  36 +++
 clang/lib/Sema/SemaRISCV.cpp  |  10 +-
 .../RISCV/atomics-intrinsics/zalrsc-error.c   |  13 +
 .../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 222 ++
 .../CodeGen/RISCV/atomics-intrinsics/zawrs.c  |  42 
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  32 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoA.td  |  25 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td |   5 +-
 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll|  74 ++
 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll|  74 ++
 llvm/test/CodeGen/RISCV/zawrs.ll  |  33 +++
 14 files changed, 605 insertions(+), 2 deletions(-)
 create mode 100644 clang/lib/Headers/riscv_atomics.h
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zawrs.ll

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td 
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..458c755179417 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,21 @@ let Features = "zihintntl", Attributes = 
[CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
+
+//===--===//
+// Zalrsc extension.
+//===--===//
+let Features = "zalrsc" in {
+def lr_w : RISCVBuiltin<"int(int *, _Constant unsigned int)">;
+def lr_d : RISCVBuiltin<"int64_t(int64_t *, _Constant unsigned int)">;
+def sc_w : RISCVBuiltin<"int(int, int *, _Constant unsigned int)">;
+def sc_d : RISCVBuiltin<"int64_t(int64_t, int64_t *, _Constant unsigned int)">;
+} // Features = "zalrsc"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 37d0c478e0330..db48c69e10c86 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21769,6 +21769,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
 ID = Intrinsic::riscv_sm3p1;
 break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
+  // Zalrsc
+  case RISCV::BI__builtin_riscv_lr_w:
+ID = Intrinsic::riscv_lr_w;
+break;
+  case RISCV::BI__builtin_riscv_lr_d:
+ID = Intrinsic::riscv_lr_d;
+break;
+  case RISCV::BI__builtin_riscv_sc_w:
+ID = Intrinsic::riscv_sc_w;
+break;
+  case RISCV::BI__builtin_riscv_sc_d:
+ID = Intrinsic::riscv_sc_d;
+break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
 llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index d3090e488306f..cf2fbf1893772 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomics.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h 
b/clang/lib/Headers/riscv_atomics.h
new file mode 100644
index 0..35db57fe36131
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomics.h
@@ -0,0 +1,36 @@
+/*=== riscv_atomics.h - RISC-V atomics intrinsics --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===--

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp converted_to_draft 
https://github.com/llvm/llvm-project/pull/94578
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[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/94578

`riscv_atomics.h` contains all builtins for atomics.


>From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Thu, 6 Jun 2024 13:48:34 +0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
 =?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6-beta.1
---
 clang/include/clang/Basic/BuiltinsRISCV.td|  18 ++
 clang/lib/CodeGen/CGBuiltin.cpp   |  22 ++
 clang/lib/Headers/CMakeLists.txt  |   1 +
 clang/lib/Headers/riscv_atomics.h |  36 +++
 clang/lib/Sema/SemaRISCV.cpp  |  10 +-
 .../RISCV/atomics-intrinsics/zalrsc-error.c   |  13 +
 .../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 222 ++
 .../CodeGen/RISCV/atomics-intrinsics/zawrs.c  |  42 
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  32 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoA.td  |  25 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoZa.td |   5 +-
 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll|  74 ++
 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll|  74 ++
 llvm/test/CodeGen/RISCV/zawrs.ll  |  33 +++
 14 files changed, 605 insertions(+), 2 deletions(-)
 create mode 100644 clang/lib/Headers/riscv_atomics.h
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
 create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/zawrs.ll

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td 
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..458c755179417 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,21 @@ let Features = "zihintntl", Attributes = 
[CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
+
+//===--===//
+// Zalrsc extension.
+//===--===//
+let Features = "zalrsc" in {
+def lr_w : RISCVBuiltin<"int(int *, _Constant unsigned int)">;
+def lr_d : RISCVBuiltin<"int64_t(int64_t *, _Constant unsigned int)">;
+def sc_w : RISCVBuiltin<"int(int, int *, _Constant unsigned int)">;
+def sc_d : RISCVBuiltin<"int64_t(int64_t, int64_t *, _Constant unsigned int)">;
+} // Features = "zalrsc"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 37d0c478e0330..db48c69e10c86 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21769,6 +21769,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
 ID = Intrinsic::riscv_sm3p1;
 break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
+  // Zalrsc
+  case RISCV::BI__builtin_riscv_lr_w:
+ID = Intrinsic::riscv_lr_w;
+break;
+  case RISCV::BI__builtin_riscv_lr_d:
+ID = Intrinsic::riscv_lr_d;
+break;
+  case RISCV::BI__builtin_riscv_sc_w:
+ID = Intrinsic::riscv_sc_w;
+break;
+  case RISCV::BI__builtin_riscv_sc_d:
+ID = Intrinsic::riscv_sc_d;
+break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
 llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index d3090e488306f..cf2fbf1893772 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomics.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h 
b/clang/lib/Headers/riscv_atomics.h
new file mode 100644
index 0..35db57fe36131
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomics.h
@@ -0,0 +1,36 @@
+/*=== riscv_atomics.h - RISC-V atomics intrinsics --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---

[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)

[Pengcheng Wang via cfe-commits]

@@ -381,3 +381,14 @@ def XIANGSHAN_NANHU : 
RISCVProcessorModel<"xiangshan-nanhu",
 TuneZExtHFusion,
 TuneZExtWFusion,
 TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+   NoSchedModel,

wangpc-pp wrote:

Indent here.

https://github.com/llvm/llvm-project/pull/94564
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[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

Spacemit K1 is the name of the product/SoC or whatever you call it. The 
processor definitions in the RISCV backend are focusing on the CPU core.
For Spacemit K1, its name should be `X60`? I don't know……

https://github.com/llvm/llvm-project/pull/94564
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

> Filed https://gitlab.kitware.com/cmake/cmake/-/issues/26031

So this is a cmake bug, not clang's, right?


https://github.com/llvm/llvm-project/pull/90373
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

[Pengcheng Wang via cfe-commits]

@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

wangpc-pp wrote:

> Remove this from `CombineIntoExts` may cause `__riscv_b` become less useful I 
> think?

Yeah, but I think @topperc's concern makes sense as well. Will binutils 
complain or just ignore unknown extensions?

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

[Pengcheng Wang via cfe-commits]

@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

wangpc-pp wrote:

I removed this part.
We can support combination of B extension in a separate patch if we need it.

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From ac2c10240160783ebbd65332230c8c294fef2442 Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c|  5 -
 .../test/Preprocessor/riscv-target-features.c | 20 +++
 llvm/docs/RISCVUsage.rst  |  1 +
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/test/CodeGen/RISCV/attributes.ll |  4 
 .../TargetParser/RISCVISAInfoTest.cpp |  9 ++---
 7 files changed, 36 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ddf617bbb6237..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 09b9ad0a160bb..5d578a02b20fb 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,25 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// CHECK-COMBINE-INTO-B: __riscv_b 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 35115e67ecf92..ef06f80c747f9 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 393b97efa5470..2aee464cdaf2d 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -142,6 +142,7 @@ Changes to the RISC-V Backend
 * Zaamo and Zalrsc are no longer experimental.
 * Processors that enable post reg-alloc scheduling (PostMachineScheduler) by 
default should use the `UsePostRAScheduler` subtarget feature. Setting 
`PostRAScheduler = 1` in the scheduler model will have no effect on the 
enabling of the PostMachineScheduler.
 * Zabha is no longer experimental.
+* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9bf06850483d8..011edca019fd6 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureStdExtB
+: RISCVExtension<"b", 1, 0,
+ "'B' (the collection of the Zba, Zbb, Zbs extensions)",
+ 

[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

> What kind of detail are you looking for?

Mainly about the commands of cmake building. Does this failure bind to a 
buildbot?
And can @AaronBallman @vitalybuka @vgvassilev help me to figure this out?

https://github.com/llvm/llvm-project/pull/90373
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[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/94318
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[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

This seems to be a breaking change, do we need to create issue in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc?

https://github.com/llvm/llvm-project/pull/94318
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

> This broke building clang on Windows with PGO:
> 
> ```
> FAILED: bin/clang-repl.exe lib/clang-repl.lib 
> cmd.exe /C "cmd.exe /C "D:\task_171745452431588\fetches\cmake\bin\cmake.exe 
> -E __create_def 
> D:\task_171745452431588\fetches\llvm-project\build\stage2\build\tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir\.\exports.def
>  
> D:\task_171745452431588\fetches\llvm-project\build\stage2\build\tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir\.\exports.def.objs
>  --nm=D:\task_171745452431588\fetches\clang\bin\llvm-nm.exe && cd 
> D:\task_171745452431588\fetches\llvm-project\build\stage2\build" && 
> D:\task_171745452431588\fetches\cmake\bin\cmake.exe -E vs_link_exe 
> --intdir=tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir 
> --rc="D:\task_171745452431588\fetches\vs\Windows 
> Kits\10\bin\10.0.22621.0\x64\rc.exe" 
> --mt="D:\task_171745452431588\fetches\vs\Windows 
> Kits\10\bin\10.0.22621.0\x64\mt.exe" --manifests  -- 
> D:\task_171745452431588\fetches\clang\bin\lld-link.exe /nologo 
> @CMakeFiles\clang-repl.rsp  /out:bin\clang-repl.exe 
> /implib:lib\clang-repl.lib /pdb:bin\clang-repl.pdb /version:0.0 /machine:x64 
> /STACK:1000 
> /libpath:"D:/task_171745452431588/fetches/clang/lib/clang/19/lib/windows" 
> /INCREMENTAL:NO /subsystem:console   /EXPORT:??_7type_info@@6B@ 
> /EXPORT:?__type_info_root_node@@3U__type_info_node@@A 
> /EXPORT:?nothrow@std@@3Unothrow_t@1@B /EXPORT:_Init_thread_abort 
> /EXPORT:_Init_thread_epoch /EXPORT:_Init_thread_footer 
> /EXPORT:_Init_thread_header /EXPORT:_tls_index /EXPORT:??2@YAPEAX_K@Z 
> /EXPORT:??3@YAXPEAX@Z /EXPORT:??_U@YAPEAX_K@Z /EXPORT:??_V@YAXPEAX@Z 
> /EXPORT:??3@YAXPEAX_K@Z 
> /DEF:"D:/task_171745452431588/fetches/llvm-project/build/stage2/build/tools/clang/tools/clang-repl/clang-repl.def"
>   -Wl,--long-plt 
> /DEF:tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir\.\exports.def  && 
> cd ."
> LINK: command "D:\task_171745452431588\fetches\clang\bin\lld-link.exe /nologo 
> @CMakeFiles\clang-repl.rsp /out:bin\clang-repl.exe /implib:lib\clang-repl.lib 
> /pdb:bin\clang-repl.pdb /version:0.0 /machine:x64 /STACK:1000 
> /libpath:D:/task_171745452431588/fetches/clang/lib/clang/19/lib/windows 
> /INCREMENTAL:NO /subsystem:console /EXPORT:??_7type_info@@6B@ 
> /EXPORT:?__type_info_root_node@@3U__type_info_node@@A 
> /EXPORT:?nothrow@std@@3Unothrow_t@1@B /EXPORT:_Init_thread_abort 
> /EXPORT:_Init_thread_epoch /EXPORT:_Init_thread_footer 
> /EXPORT:_Init_thread_header /EXPORT:_tls_index /EXPORT:??2@YAPEAX_K@Z 
> /EXPORT:??3@YAXPEAX@Z /EXPORT:??_U@YAPEAX_K@Z /EXPORT:??_V@YAXPEAX@Z 
> /EXPORT:??3@YAXPEAX_K@Z 
> /DEF:D:/task_171745452431588/fetches/llvm-project/build/stage2/build/tools/clang/tools/clang-repl/clang-repl.def
>  -Wl,--long-plt 
> /DEF:tools\clang\tools\clang-repl\CMakeFiles\clang-repl.dir\.\exports.def 
> /MANIFEST /MANIFESTFILE:bin\clang-repl.exe.manifest" failed (exit code 1) 
> with the following output:
> lld-link: error: : undefined symbol: __profc_??$?0$$BY03DUdesc
> lld-link: error: : undefined symbol: __profc_??$?0$$BY04DW4OptionHidden
> lld-link: error: : undefined symbol: __profc_??$?0$$BY09DW4OptionHidden
> lld-link: error: : undefined symbol: __profc_??$?0$$BY0BC
> lld-link: error: : undefined symbol: __profc_??$?0$$BY0N
> lld-link: error: : undefined symbol: __profc_??$?0W4FormattingFlags
> lld-link: error: : undefined symbol: __profc_??$?4$$BY05D
> lld-link: error: : undefined symbol: __profc_??$?6PEBD
> lld-link: error: : undefined symbol: __profc_??$_Emplace_reallocate
> lld-link: error: : undefined symbol: __profc_??$_Reallocate_for
> lld-link: error: : undefined symbol: __profc_??$_Reallocate_grow_by
> lld-link: error: : undefined symbol: __profc_??$_Traits_find 
> lld-link: error: : undefined symbol: __profc_??$_Traits_rfind
> lld-link: error: : undefined symbol: __profc_??$_Uninitialized_move
> lld-link: error: : undefined symbol: __profc_??$addValue
> lld-link: error: : undefined symbol: __profc_??$handleErrors 
> lld-link: error: : undefined symbol: __profc_??$setValue
> lld-link: error: : undefined symbol: __profc_??0?$OptionValueCopy
> lld-link: error: : undefined symbol: __profc_??0Completion
> lld-link: error: : undefined symbol: __profc_??0ErrorList
> lld-link: error: too many errors emitted, stopping now (use /errorlimit:0 to 
> see all errors)
> ```

I don't have such environment, can you provide more details? And it seems these 
undefined symbols are not symbols for `delete`.

https://github.com/llvm/llvm-project/pull/90373
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[clang] [llvm] [RISCV] Add Smcsrind and Sscsrind extension (PR #93952)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

> Specification link: https://github.com/riscvarchive/riscv-indirect-csr-access

You may need to update link to 
https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc.

https://github.com/llvm/llvm-project/pull/93952
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

[Pengcheng Wang via cfe-commits]

@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"},  {"zks"},   {"zvkn"},

wangpc-pp wrote:

@kito-cheng WDYT?

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

Ping. The B extension has been ratified and I hava rebased this PR.

https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Add B extension (PR #76893)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/76893

>From a780efe3e297fe59c5521ea5387dda12905a4423 Mon Sep 17 00:00:00 2001
From: wangpc 
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension

It seems that we have `B` extension again: https://github.com/riscv/riscv-b

According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
 clang/test/Driver/riscv-arch.c|  5 -
 .../test/Preprocessor/riscv-target-features.c | 20 +++
 llvm/docs/RISCVUsage.rst  |  1 +
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  4 ++--
 llvm/test/CodeGen/RISCV/attributes.ll | 18 ++---
 .../TargetParser/RISCVISAInfoTest.cpp |  9 ++---
 8 files changed, 45 insertions(+), 21 deletions(-)

diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ddf617bbb6237..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
 // RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 0865add7e8fb8..ff3f31ec67c1c 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
 // CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,25 @@
 // CHECK-A-EXT: __riscv_a 2001000{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ib -x c -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 100{{$}}
+// CHECK-B-EXT: __riscv_zba 100{{$}}
+// CHECK-B-EXT: __riscv_zbb 100{{$}}
+// CHECK-B-EXT: __riscv_zbs 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64i_zba_zbb_zbs -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-B %s
+// CHECK-COMBINE-INTO-B: __riscv_b 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ic -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5ecee2a480f7d..34c2b967a4111 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
  Extension Status
    
=
  ``A`` Supported
+ ``B`` Supported
  ``C`` Supported
  ``D`` Supported
  ``F`` Supported
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 1e1ccb495c366..6e96545c739e3 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -132,6 +132,7 @@ Changes to the RISC-V Backend
 * Added smstateen extension to -march. CSR names for smstateen were already 
supported.
 * Zaamo and Zalrsc are no longer experimental.
 * Processors that enable post reg-alloc scheduling (PostMachineScheduler) by 
default should use the `UsePostRAScheduler` subtarget feature. Setting 
`PostRAScheduler = 1` in the scheduler model will have no effect on the 
enabling of the PostMachineScheduler.
+* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a78d78946be31..6acb147330d62 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 
 // Bitmanip Extensions for Cryptography Extensions
 
+def FeatureSt

[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

Thanks @vitalybuka for fixing the remain issues.
It has been about 2 days since this PR was merged and there is no other issue, 
I think we finally make sized deallocation default this time! Cheers!

https://github.com/llvm/llvm-project/pull/90373
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

Thanks @vitalybuka! After some investigations, I think this PR just uncovered 
the existed ASAN problem.
```cpp
#if !defined(__cpp_sized_deallocation) || __cpp_sized_deallocation < 201309L
#  define _LIBCPP_HAS_NO_LANGUAGE_SIZED_DEALLOCATION
#endif

#if !defined(_LIBCPP_BUILDING_LIBRARY) && _LIBCPP_STD_VER < 14 && 
defined(_LIBCPP_HAS_NO_LANGUAGE_SIZED_DEALLOCATION)
#  define _LIBCPP_HAS_NO_LIBRARY_SIZED_DEALLOCATION
#endif

#if defined(_LIBCPP_HAS_NO_LIBRARY_SIZED_DEALLOCATION) || 
defined(_LIBCPP_HAS_NO_LANGUAGE_SIZED_DEALLOCATION)
#  define _LIBCPP_HAS_NO_SIZED_DEALLOCATION
#endif

template 
_LIBCPP_HIDE_FROM_ABI void __do_deallocate_handle_size(void* __ptr, size_t 
__size, _Args... __args) {
#ifdef _LIBCPP_HAS_NO_SIZED_DEALLOCATION
  (void)__size;
  return std::__libcpp_operator_delete(__ptr, __args...);
#else
  return std::__libcpp_operator_delete(__ptr, __size, __args...);
#endif
}
```
The `__do_deallocate_handle_size` ignored the `__size` before this PR.

https://github.com/llvm/llvm-project/pull/90373
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

> > Based on my rough understanding, this is expected?
> 
> What do you mean?
> 
> Isn't this test needs to be updated or disabled?

I think this ASAN failure is not caused by this PR because these memorys are 
allocated/deallocated by `memory_resource` directly, **there is nothing about 
`new`/`delete`**. We allocate 50 bytes via `void* ret = r1.allocate(50);` and 
deallocate 1 byte via `r1.deallocate(ret, 1);` and that's the reason why ASAN 
failed, because the size of the allocated type (50 bytes) and the size of the 
deallocated type (1 byte) are really not matched.

I don't know if this is what we want to test, if so, we may add `// 
UNSUPPORTED: asan` to skip this test in ASAN builds.
cc @ldionne @Quuxplusone

https://github.com/llvm/llvm-project/pull/90373
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

> This one is broken https://lab.llvm.org/buildbot/#/builders/168/builds/20461

The broken case is:
```cpp
void test_allocate_deallocate() {
  std::pmr::memory_resource& r1 = *std::pmr::new_delete_resource();

  globalMemCounter.reset();

  void* ret = r1.allocate(50);
  assert(ret);
  
ASSERT_WITH_LIBRARY_INTERNAL_ALLOCATIONS(globalMemCounter.checkOutstandingNewEq(1));
  
ASSERT_WITH_LIBRARY_INTERNAL_ALLOCATIONS(globalMemCounter.checkLastNewSizeEq(50));

  r1.deallocate(ret, 1);
  assert(globalMemCounter.checkOutstandingNewEq(0));
  
ASSERT_WITH_LIBRARY_INTERNAL_ALLOCATIONS(globalMemCounter.checkDeleteCalledEq(1));
}
```
The errors are:
```
# .---command stderr
# | =
# | ==3452201==ERROR: AddressSanitizer: new-delete-type-mismatch on 
0x50600020 in thread T0:
# |   object passed to delete has wrong type:
# |   size of the allocated type:   50 bytes;
# |   size of the deallocated type: 1 bytes.
# | #0 0x565094abbd02  
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14ad02)
# | #1 0x565094abe168  
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14d168)
# | #2 0x565094abd941  
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14c941)
# | #3 0x565094abda24  
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14ca24)
# | #4 0x7f8643c2814f  (/lib/x86_64-linux-gnu/libc.so.6+0x2814f) (BuildId: 
b20cbdb62d7717c13dc61a48b7b2e673a7edf233)
# | #5 0x7f8643c28208  (/lib/x86_64-linux-gnu/libc.so.6+0x28208) (BuildId: 
b20cbdb62d7717c13dc61a48b7b2e673a7edf233)
# | #6 0x5650949dbed4  
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x6aed4)
# | 
# | 0x50600020 is located 0 bytes inside of 50-byte region 
[0x50600020,0x50600052)
# | allocated by thread T0 here:
# | #0 0x565094abb09d  
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14a09d)
# | #1 0x565094abe098  
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14d098)
# | #2 0x565094abd83f  
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14c83f)
# | #3 0x565094abda24  
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14ca24)
# | #4 0x7f8643c2814f  (/lib/x86_64-linux-gnu/libc.so.6+0x2814f) (BuildId: 
b20cbdb62d7717c13dc61a48b7b2e673a7edf233)
# | 
# | SUMMARY: AddressSanitizer: new-delete-type-mismatch 
(/b/sanitizer-x86_64-linux-bootstrap-asan/build/libcxx_build_asan/test/std/utilities/utility/mem.res/mem.res.global/Output/new_delete_resource.pass.cpp.dir/t.tmp.exe+0x14ad02)
 
# | ==3452201==HINT: if you don't care about these errors you may set 
ASAN_OPTIONS=new_delete_type_mismatch=0
# | ==3452201==ABORTING
# `-
# error: command failed with exit status: 1
```

Based on my rough understanding, this is expected? Because we allocate 50 bytes 
via `void* ret = r1.allocate(50);` and deallocate 1 byte via 
`r1.deallocate(ret, 1);`.

https://github.com/llvm/llvm-project/pull/90373
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp closed 
https://github.com/llvm/llvm-project/pull/90373
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[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

[Pengcheng Wang via cfe-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/90373

>From a18f57e23c0d4fd23647eb2ef610352e402b45f6 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang 
Date: Fri, 26 Apr 2024 16:59:12 +0800
Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards

Since C++14 has been released for about nine years and most standard
libraries have implemented sized deallocation functions, it's time to
make this feature default again.

This is another try of https://reviews.llvm.org/D112921.

The original commit cf5a8b4 was reverted by 2e5035a due to some
failures (see #83774).

Fixes #60061
---
 .../clangd/unittests/FindTargetTests.cpp  |   4 +-
 .../checkers/misc/new-delete-overloads.cpp|  10 -
 clang/docs/ReleaseNotes.rst   |   5 +
 clang/include/clang/Driver/Options.td |   8 +-
 clang/lib/Driver/ToolChains/Clang.cpp |  13 +-
 clang/lib/Driver/ToolChains/Darwin.cpp|  58 -
 clang/lib/Driver/ToolChains/Darwin.h  |   4 +
 clang/lib/Driver/ToolChains/ZOS.cpp   |   6 +
 clang/test/AST/ast-dump-expr-json.cpp |   2 +-
 clang/test/AST/ast-dump-expr.cpp  |   2 +-
 clang/test/AST/ast-dump-stmt-json.cpp | 244 +-
 clang/test/Analysis/cxxnewexpr-callback.cpp   |   4 +-
 .../basic.stc.dynamic.deallocation/p2.cpp |   2 +-
 clang/test/CXX/drs/cwg292.cpp |  17 +-
 .../test/CXX/expr/expr.unary/expr.new/p14.cpp |   2 +-
 .../CodeGenCXX/cxx1y-sized-deallocation.cpp   |  10 +-
 .../CodeGenCXX/cxx1z-aligned-allocation.cpp   |   6 +-
 .../CodeGenCXX/cxx2a-destroying-delete.cpp|   4 +-
 clang/test/CodeGenCXX/delete-two-arg.cpp  |   4 +-
 clang/test/CodeGenCXX/delete.cpp  |  12 +-
 clang/test/CodeGenCXX/dllimport.cpp   |   4 +-
 clang/test/CodeGenCXX/new.cpp |   6 +-
 .../coro-aligned-alloc-2.cpp  |   2 -
 .../CodeGenCoroutines/coro-aligned-alloc.cpp  |   6 +-
 clang/test/CodeGenCoroutines/coro-alloc.cpp   |   6 +-
 clang/test/CodeGenCoroutines/coro-cleanup.cpp |   6 +-
 clang/test/CodeGenCoroutines/coro-dealloc.cpp |   2 -
 clang/test/CodeGenCoroutines/coro-gro.cpp |   3 +-
 clang/test/CodeGenCoroutines/pr56919.cpp  |   9 +-
 clang/test/Lexer/cxx-features.cpp |  20 +-
 clang/test/PCH/cxx1z-aligned-alloc.cpp|  10 +-
 clang/test/SemaCXX/MicrosoftExtensions.cpp|   8 +-
 .../SemaCXX/builtin-operator-new-delete.cpp   |   2 +-
 .../test/SemaCXX/cxx1y-sized-deallocation.cpp |   2 +-
 .../unavailable_aligned_allocation.cpp|  15 +-
 clang/tools/clang-repl/CMakeLists.txt |  43 +++
 clang/unittests/Interpreter/CMakeLists.txt|  43 +++
 .../StaticAnalyzer/CallEventTest.cpp  |   2 +-
 clang/www/cxx_status.html |  11 +-
 .../support.dynamic/libcpp_deallocate.sh.cpp  |   3 +
 .../sized_delete_array14.pass.cpp |   8 +-
 .../new.delete.single/sized_delete14.pass.cpp |   8 +-
 42 files changed, 523 insertions(+), 113 deletions(-)

diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp 
b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
index 0b2273f0a9a6e..3220a5a6a9825 100644
--- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp
@@ -836,7 +836,9 @@ TEST_F(TargetDeclTest, OverloadExpr) {
   [[delete]] x;
 }
   )cpp";
-  EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept");
+  // Sized deallocation is enabled by default in C++14 onwards.
+  EXPECT_DECLS("CXXDeleteExpr",
+   "void operator delete(void *, unsigned long) noexcept");
 }
 
 TEST_F(TargetDeclTest, DependentExprs) {
diff --git 
a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp 
b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
index 78f021144b2e1..f86fe8a4c5b14 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
@@ -12,16 +12,6 @@ struct S {
 // CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has 
no matching declaration of 'operator delete' at the same scope
 void *operator new(size_t size) noexcept(false);
 
-struct T {
-  // Sized deallocations are not enabled by default, and so this new/delete 
pair
-  // does not match. However, we expect only one warning, for the new, because
-  // the operator delete is a placement delete and we do not warn on 
mismatching
-  // placement operations.
-  // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new' 
has no matching declaration of 'operator delete' at the same scope
-  void *operator new(size_t size) noexcept;
-  void operator delete(void *ptr, size_t) noexcept; // ok only if sized 
deallocation is enabled
-};
-
 struct U {
   void *operator new(size_t size) noexcept;
   void operator delete(void *ptr) n

[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

[Pengcheng Wang via cfe-commits]

wangpc-pp wrote:

Please review this PR as all noticable issues have been fixed I think.

https://github.com/llvm/llvm-project/pull/90373
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