subject:"\\\\\\\[PATCH 2\\\\\\\/3\\\\\\\] drm\\\\\\\/radeon\\\\\\\: Make SI support in Radeon conditional"

RE: [PATCH 2/3] drm/radeon: Make SI support in Radeon conditional

2017-04-12 Thread Li, Samuel

My understanding is that SI support in AMDGPU is limited. 
So maybe here it can be the other way around, that by default SI support in 
AMDGPU shall be disabled.

Sam


-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Felix 
Kuehling
Sent: Friday, April 07, 2017 4:16 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix <felix.kuehl...@amd.com>
Subject: [PATCH 2/3] drm/radeon: Make SI support in Radeon conditional

Advertise SI PCI IDs only when they are not supported by amdgpu.
Use the CONFIG_DRM_AMDGPU_SI to check so that a single option in the kernel 
config keeps both drivers in sync.

This is the simplest possible change. A more complete solution may want to 
conditionally disable more SI-specific code in the Radeon driver.

Signed-off-by: Felix Kuehling <felix.kuehl...@amd.com>
---
 drivers/gpu/drm/radeon/Kconfig  |  12 +++
 drivers/gpu/drm/radeon/radeon_drv.c |   3 +
 include/drm/drm_pciids.h| 146 ++--
 3 files changed, 89 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig 
index 86bbac8..2e66198 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,3 +1,15 @@
+config DRM_RADEON_FORCE_SI
+   bool "Enable radeon support for SI parts even when amdgpu supports it"
+   depends on DRM_RADEON && DRM_AMDGPU_SI
+   default n
+   help
+ Choose this option if you want to enable support for SI ASICs
+ in the radeon driver even when CONFIG_DRM_AMDGPU_SI is enabled.
+
+ This option is meant for experimentation and testing. In a
+ production system only one driver should claim support for the
+ same ASIC.
+
 config DRM_RADEON_FORCE_CIK
bool "Enable radeon support for CIK parts even when amdgpu supports it"
depends on DRM_RADEON && DRM_AMDGPU_CIK diff --git 
a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index fda6411..235c324 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -305,6 +305,9 @@ static inline void radeon_unregister_atpx_handler(void) {}  
#if !defined(CONFIG_DRM_AMDGPU_CIK) || defined(CONFIG_DRM_RADEON_FORCE_CIK)
radeon_CIK_PCI_IDS,
 #endif
+#if !defined(CONFIG_DRM_AMDGPU_SI) || defined(CONFIG_DRM_RADEON_FORCE_SI)
+   radeon_CIK_PCI_IDS,
+#endif
radeon_PCI_IDS
 };
 
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index 
cf17901..b42179f 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -1,3 +1,77 @@
+#define radeon_SI_PCI_IDS \
+   {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6819, PCI_ANY_ID, PC

[PATCH 2/3] drm/radeon: Make SI support in Radeon conditional

2017-04-07 Thread Felix Kuehling

Advertise SI PCI IDs only when they are not supported by amdgpu.
Use the CONFIG_DRM_AMDGPU_SI to check so that a single option in
the kernel config keeps both drivers in sync.

This is the simplest possible change. A more complete solution
may want to conditionally disable more SI-specific code in the
Radeon driver.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/radeon/Kconfig  |  12 +++
 drivers/gpu/drm/radeon/radeon_drv.c |   3 +
 include/drm/drm_pciids.h| 146 ++--
 3 files changed, 89 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 86bbac8..2e66198 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,3 +1,15 @@
+config DRM_RADEON_FORCE_SI
+   bool "Enable radeon support for SI parts even when amdgpu supports it"
+   depends on DRM_RADEON && DRM_AMDGPU_SI
+   default n
+   help
+ Choose this option if you want to enable support for SI ASICs
+ in the radeon driver even when CONFIG_DRM_AMDGPU_SI is enabled.
+
+ This option is meant for experimentation and testing. In a
+ production system only one driver should claim support for the
+ same ASIC.
+
 config DRM_RADEON_FORCE_CIK
bool "Enable radeon support for CIK parts even when amdgpu supports it"
depends on DRM_RADEON && DRM_AMDGPU_CIK
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index fda6411..235c324 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -305,6 +305,9 @@ static inline void radeon_unregister_atpx_handler(void) {}
 #if !defined(CONFIG_DRM_AMDGPU_CIK) || defined(CONFIG_DRM_RADEON_FORCE_CIK)
radeon_CIK_PCI_IDS,
 #endif
+#if !defined(CONFIG_DRM_AMDGPU_SI) || defined(CONFIG_DRM_RADEON_FORCE_SI)
+   radeon_CIK_PCI_IDS,
+#endif
radeon_PCI_IDS
 };
 
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index cf17901..b42179f 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -1,3 +1,77 @@
+#define radeon_SI_PCI_IDS \
+   {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+   {0x1002, 0x6824, PCI_ANY_ID,

RE: [PATCH 2/3] drm/radeon: Make SI support in Radeon conditional

[PATCH 2/3] drm/radeon: Make SI support in Radeon conditional

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