Re: [PATCH 3/3] drm/amd/powerplay: update didt configs

2017-07-28 Thread Alex Deucher
On Fri, Jul 28, 2017 at 5:59 AM, Huang Rui  wrote:
> On Fri, Jul 28, 2017 at 04:01:01PM +0800, Evan Quan wrote:
>> Change-Id: I1506f4c6e9320a1e90a89be55368328cbaab7844
>> Signed-off-by: Evan Quan 
>
> Reviewed-by: Huang Rui 

Reviewed-by: Alex Deucher 

>
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
>> index fbafc84..e7fa670 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
>> @@ -543,7 +543,7 @@ static const struct vega10_didt_config_reg 
>> SEEDCCtrlForceStallConfig_Vega10[] =
>>   * 
>> -
>>   */
>>   /* SQ */
>> - {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,  
>>  DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
>> 0x0001 },
>> + {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,  
>>  DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
>> 0x },
>>   {   ixDIDT_SQ_EDC_CTRL,
>> DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,   
>> DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
>>   {   ixDIDT_SQ_EDC_CTRL,
>> DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
>> DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
>>   {   ixDIDT_SQ_EDC_CTRL,
>> DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,  
>> DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
>> @@ -556,7 +556,7 @@ static const struct vega10_didt_config_reg 
>> SEEDCCtrlForceStallConfig_Vega10[] =
>>   {   ixDIDT_SQ_EDC_CTRL,
>> DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, 
>> DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,  0x0001 },
>>
>>   /* TD */
>> - {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,  
>>  DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
>> 0x0001 },
>> + {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,  
>>  DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
>> 0x },
>>   {   ixDIDT_TD_EDC_CTRL,
>> DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,   
>> DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
>>   {   ixDIDT_TD_EDC_CTRL,
>> DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
>> DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
>>   {   ixDIDT_TD_EDC_CTRL,
>> DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,  
>> DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
>> @@ -1208,7 +1208,7 @@ static int 
>> vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
>>   if (0 != result)
>>   return result;
>>
>> - vega10_didt_set_mask(hwmgr, true);
>> + vega10_didt_set_mask(hwmgr, false);
>>
>>   cgs_enter_safe_mode(hwmgr->device, false);
>>
>> --
>> 2.7.4
>>
>> ___
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Re: [PATCH 3/3] drm/amd/powerplay: update didt configs

2017-07-28 Thread Huang Rui
On Fri, Jul 28, 2017 at 04:01:01PM +0800, Evan Quan wrote:
> Change-Id: I1506f4c6e9320a1e90a89be55368328cbaab7844
> Signed-off-by: Evan Quan 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> index fbafc84..e7fa670 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> @@ -543,7 +543,7 @@ static const struct vega10_didt_config_reg 
> SEEDCCtrlForceStallConfig_Vega10[] =
>   * 
> -
>   */
>   /* SQ */
> - {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
> DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
> 0x0001 },
> + {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
> DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
> 0x },
>   {   ixDIDT_SQ_EDC_CTRL,
> DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,   
> DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
>   {   ixDIDT_SQ_EDC_CTRL,
> DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
> DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
>   {   ixDIDT_SQ_EDC_CTRL,
> DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,  
> DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
> @@ -556,7 +556,7 @@ static const struct vega10_didt_config_reg 
> SEEDCCtrlForceStallConfig_Vega10[] =
>   {   ixDIDT_SQ_EDC_CTRL,
> DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, 
> DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,  0x0001 },
>  
>   /* TD */
> - {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
> DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
> 0x0001 },
> + {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
> DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
> 0x },
>   {   ixDIDT_TD_EDC_CTRL,
> DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,   
> DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
>   {   ixDIDT_TD_EDC_CTRL,
> DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
> DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
>   {   ixDIDT_TD_EDC_CTRL,
> DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,  
> DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
> @@ -1208,7 +1208,7 @@ static int 
> vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
>   if (0 != result)
>   return result;
>  
> - vega10_didt_set_mask(hwmgr, true);
> + vega10_didt_set_mask(hwmgr, false);
>  
>   cgs_enter_safe_mode(hwmgr->device, false);
>  
> -- 
> 2.7.4
> 
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[PATCH 3/3] drm/amd/powerplay: update didt configs

2017-07-28 Thread Evan Quan
Change-Id: I1506f4c6e9320a1e90a89be55368328cbaab7844
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index fbafc84..e7fa670 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -543,7 +543,7 @@ static const struct vega10_didt_config_reg 
SEEDCCtrlForceStallConfig_Vega10[] =
  * 
-
  */
/* SQ */
-   {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
0x0001 },
+   {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,   
DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,  
DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
@@ -556,7 +556,7 @@ static const struct vega10_didt_config_reg 
SEEDCCtrlForceStallConfig_Vega10[] =
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, 
DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,  0x0001 },
 
/* TD */
-   {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
0x0001 },
+   {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,   
DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,  
DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
@@ -1208,7 +1208,7 @@ static int vega10_enable_se_edc_force_stall_config(struct 
pp_hwmgr *hwmgr)
if (0 != result)
return result;
 
-   vega10_didt_set_mask(hwmgr, true);
+   vega10_didt_set_mask(hwmgr, false);
 
cgs_enter_safe_mode(hwmgr->device, false);
 
-- 
2.7.4

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[PATCH 3/3] drm/amd/powerplay: update didt configs

2017-07-28 Thread Evan Quan
Change-Id: I1506f4c6e9320a1e90a89be55368328cbaab7844
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index fbafc84..e7fa670 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -543,7 +543,7 @@ static const struct vega10_didt_config_reg 
SEEDCCtrlForceStallConfig_Vega10[] =
  * 
-
  */
/* SQ */
-   {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
0x0001 },
+   {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,   
DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,  
DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
@@ -556,7 +556,7 @@ static const struct vega10_didt_config_reg 
SEEDCCtrlForceStallConfig_Vega10[] =
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, 
DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,  0x0001 },
 
/* TD */
-   {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
0x0001 },
+   {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,   
DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,  
DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
@@ -1208,7 +1208,7 @@ static int vega10_enable_se_edc_force_stall_config(struct 
pp_hwmgr *hwmgr)
if (0 != result)
return result;
 
-   vega10_didt_set_mask(hwmgr, true);
+   vega10_didt_set_mask(hwmgr, false);
 
cgs_enter_safe_mode(hwmgr->device, false);
 
-- 
2.7.4

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