RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2
[AMD Official Use Only - Internal Distribution Only] Yes, we are not 100% confident on the sequence of SETUP_VMR command in guest driver, although it indeed happens after PMFW loading in GPUV driver. I think now the concern was removed now. The current sequence should work in guest driver as well, although they have further discussion on whether removing SETUP_VMR command or not... Please commit your patch. And thanks for the effort to get this landed and validated on various ASICs. Regards, Hawking -Original Message- From: Quan, Evan Sent: Tuesday, February 25, 2020 11:39 To: Zhang, Hawking ; amd-gfx@lists.freedesktop.org; Min, Frank Cc: Feng, Kenneth Subject: RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2 Hi Hawking, Do you mean SRIOV may need this change also? Currently this covers bare-metal case only(SRIOV still follows old firmwares loading sequence). Regards, Evan -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 7:34 PM To: Quan, Evan ; amd-gfx@lists.freedesktop.org; Min, Frank Cc: Feng, Kenneth Subject: RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2 [AMD Official Use Only - Internal Distribution Only] The patch looks good for bare-metal case now. Frank is still on the way to clean up our concern on SETUP_VMR command (i.e. SETUP_TMR for bare-metal case). After that settled, please push the patch with my RB. Thanks. Regards, Hawking -Original Message- From: Quan, Evan Sent: Monday, February 24, 2020 18:36 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Feng, Kenneth ; Quan, Evan Subject: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2 For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. V2: skip possible SMU firmware reloading Change-Id: I8986ddb4d9ffe63ed0823d1dce8d9d52812a1240 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 65 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 + 2 files changed, 61 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 51839ab02b84..d33f74100094 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -38,6 +38,39 @@ static void psp_set_funcs(struct amdgpu_device *adev); +/* + * Due to DF Cstate management centralized to PMFW, the firmware + * loading sequence will be updated as below: + * - Load KDB + * - Load SYS_DRV + * - Load tOS + * - Load PMFW + * - Setup TMR + * - Load other non-psp fw + * - Load ASD + * - Load XGMI/RAS/HDCP/DTM TA if any + * + * This new sequence is required for + * - Arcturus + * - Navi12 and onwards + */ +static void psp_check_pmfw_centralized_cstate_management(struct +psp_context *psp) { + struct amdgpu_device *adev = psp->adev; + + psp->pmfw_centralized_cstate_management = false; + + if (amdgpu_sriov_vf(adev)) + return; + + if (adev->flags & AMD_IS_APU) + return; + + if ((adev->asic_type == CHIP_ARCTURUS) || + (adev->asic_type >= CHIP_NAVI12)) + psp->pmfw_centralized_cstate_management = true; } + static int psp_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -75,6 +108,8 @@ static int psp_early_init(void *handle) psp->adev = adev; + psp_check_pmfw_centralized_cstate_management(psp); + return 0; } @@ -1116,10 +1151,17 @@ static int psp_hw_start(struct psp_context *psp) return ret; } - ret = psp_tmr_load(psp); - if (ret) { - DRM_ERROR("PSP load tmr failed!\n"); - return ret; + /* +* For those ASICs with DF Cstate management centralized +* to PMFW, TMR setup should be performed after PMFW +* loaded and before other non-psp firmware loaded. +*/ + if (!psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } } return 0; @@ -1316,7 +1358,8 @@ static int psp_np_fw_load(struct psp_context *psp) struct amdgpu_firmware_info *ucode; struct amdgpu_device* adev = psp->adev; - if (psp->autoload_supported) { + if (psp->autoload_supported || + psp->pmfw_centralized_cstate_management) { ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; if (!ucode->fw || amdgpu_sriov_vf(adev)) goto out; @@ -1326,6 +1369,14 @@ static int psp_np_fw_load(struct psp_context *psp) re
RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2
Hi Hawking, Do you mean SRIOV may need this change also? Currently this covers bare-metal case only(SRIOV still follows old firmwares loading sequence). Regards, Evan -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 7:34 PM To: Quan, Evan ; amd-gfx@lists.freedesktop.org; Min, Frank Cc: Feng, Kenneth Subject: RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2 [AMD Official Use Only - Internal Distribution Only] The patch looks good for bare-metal case now. Frank is still on the way to clean up our concern on SETUP_VMR command (i.e. SETUP_TMR for bare-metal case). After that settled, please push the patch with my RB. Thanks. Regards, Hawking -Original Message- From: Quan, Evan Sent: Monday, February 24, 2020 18:36 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Feng, Kenneth ; Quan, Evan Subject: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2 For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. V2: skip possible SMU firmware reloading Change-Id: I8986ddb4d9ffe63ed0823d1dce8d9d52812a1240 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 65 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 + 2 files changed, 61 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 51839ab02b84..d33f74100094 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -38,6 +38,39 @@ static void psp_set_funcs(struct amdgpu_device *adev); +/* + * Due to DF Cstate management centralized to PMFW, the firmware + * loading sequence will be updated as below: + * - Load KDB + * - Load SYS_DRV + * - Load tOS + * - Load PMFW + * - Setup TMR + * - Load other non-psp fw + * - Load ASD + * - Load XGMI/RAS/HDCP/DTM TA if any + * + * This new sequence is required for + * - Arcturus + * - Navi12 and onwards + */ +static void psp_check_pmfw_centralized_cstate_management(struct +psp_context *psp) { + struct amdgpu_device *adev = psp->adev; + + psp->pmfw_centralized_cstate_management = false; + + if (amdgpu_sriov_vf(adev)) + return; + + if (adev->flags & AMD_IS_APU) + return; + + if ((adev->asic_type == CHIP_ARCTURUS) || + (adev->asic_type >= CHIP_NAVI12)) + psp->pmfw_centralized_cstate_management = true; } + static int psp_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -75,6 +108,8 @@ static int psp_early_init(void *handle) psp->adev = adev; + psp_check_pmfw_centralized_cstate_management(psp); + return 0; } @@ -1116,10 +1151,17 @@ static int psp_hw_start(struct psp_context *psp) return ret; } - ret = psp_tmr_load(psp); - if (ret) { - DRM_ERROR("PSP load tmr failed!\n"); - return ret; + /* +* For those ASICs with DF Cstate management centralized +* to PMFW, TMR setup should be performed after PMFW +* loaded and before other non-psp firmware loaded. +*/ + if (!psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } } return 0; @@ -1316,7 +1358,8 @@ static int psp_np_fw_load(struct psp_context *psp) struct amdgpu_firmware_info *ucode; struct amdgpu_device* adev = psp->adev; - if (psp->autoload_supported) { + if (psp->autoload_supported || + psp->pmfw_centralized_cstate_management) { ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; if (!ucode->fw || amdgpu_sriov_vf(adev)) goto out; @@ -1326,6 +1369,14 @@ static int psp_np_fw_load(struct psp_context *psp) return ret; } + if (psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } + } + out: for (i = 0; i < adev->firmware.max_ucodes; i++) { ucode = &adev->firmware.ucode[i]; @@ -1333,7 +1384,9 @@ static int psp_np_fw_load(struct psp_context *psp) continue; if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && - (psp_smu_reload_quirk(psp) || psp->autoload_supported)) + (psp_smu_reload_quirk(psp) || +psp->autoload_supported || +
RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2
[AMD Official Use Only - Internal Distribution Only] The patch looks good for bare-metal case now. Frank is still on the way to clean up our concern on SETUP_VMR command (i.e. SETUP_TMR for bare-metal case). After that settled, please push the patch with my RB. Thanks. Regards, Hawking -Original Message- From: Quan, Evan Sent: Monday, February 24, 2020 18:36 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Feng, Kenneth ; Quan, Evan Subject: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2 For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. V2: skip possible SMU firmware reloading Change-Id: I8986ddb4d9ffe63ed0823d1dce8d9d52812a1240 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 65 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 + 2 files changed, 61 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 51839ab02b84..d33f74100094 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -38,6 +38,39 @@ static void psp_set_funcs(struct amdgpu_device *adev); +/* + * Due to DF Cstate management centralized to PMFW, the firmware + * loading sequence will be updated as below: + * - Load KDB + * - Load SYS_DRV + * - Load tOS + * - Load PMFW + * - Setup TMR + * - Load other non-psp fw + * - Load ASD + * - Load XGMI/RAS/HDCP/DTM TA if any + * + * This new sequence is required for + * - Arcturus + * - Navi12 and onwards + */ +static void psp_check_pmfw_centralized_cstate_management(struct +psp_context *psp) { + struct amdgpu_device *adev = psp->adev; + + psp->pmfw_centralized_cstate_management = false; + + if (amdgpu_sriov_vf(adev)) + return; + + if (adev->flags & AMD_IS_APU) + return; + + if ((adev->asic_type == CHIP_ARCTURUS) || + (adev->asic_type >= CHIP_NAVI12)) + psp->pmfw_centralized_cstate_management = true; } + static int psp_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -75,6 +108,8 @@ static int psp_early_init(void *handle) psp->adev = adev; + psp_check_pmfw_centralized_cstate_management(psp); + return 0; } @@ -1116,10 +1151,17 @@ static int psp_hw_start(struct psp_context *psp) return ret; } - ret = psp_tmr_load(psp); - if (ret) { - DRM_ERROR("PSP load tmr failed!\n"); - return ret; + /* +* For those ASICs with DF Cstate management centralized +* to PMFW, TMR setup should be performed after PMFW +* loaded and before other non-psp firmware loaded. +*/ + if (!psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } } return 0; @@ -1316,7 +1358,8 @@ static int psp_np_fw_load(struct psp_context *psp) struct amdgpu_firmware_info *ucode; struct amdgpu_device* adev = psp->adev; - if (psp->autoload_supported) { + if (psp->autoload_supported || + psp->pmfw_centralized_cstate_management) { ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; if (!ucode->fw || amdgpu_sriov_vf(adev)) goto out; @@ -1326,6 +1369,14 @@ static int psp_np_fw_load(struct psp_context *psp) return ret; } + if (psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } + } + out: for (i = 0; i < adev->firmware.max_ucodes; i++) { ucode = &adev->firmware.ucode[i]; @@ -1333,7 +1384,9 @@ static int psp_np_fw_load(struct psp_context *psp) continue; if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && - (psp_smu_reload_quirk(psp) || psp->autoload_supported)) + (psp_smu_reload_quirk(psp) || +psp->autoload_supported || +psp->pmfw_centralized_cstate_management)) continue; if (amdgpu_sriov_vf(adev) && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index c77e1abb538a..37fa184f27f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -264,6 +264,8 @@ struct psp_context atomic_tfence_value; /* flag to mark whether gfx fw autoload is supported or not */
RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence
Thanks. Will update that in V2. Only Arcturus was affected since Navi1x was already protected by autoload_supported. As I know, psp will skip smu fw loading if SMU is already alive. So, there should be no reloading. But there should be a skip in driver. Regards, Evan -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 6:19 PM To: Quan, Evan ; amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth Subject: RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence [AMD Official Use Only - Internal Distribution Only] Sorry just for Navi12. Arcturus should be fine as it doesn't support autoload. Regards, Hawking -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 18:18 To: Quan, Evan ; 'amd-gfx@lists.freedesktop.org' Cc: Feng, Kenneth Subject: RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence [AMD Official Use Only - Internal Distribution Only] That's saying I suspect the PMFW was loaded twice with the patch for Arcturus and Navi12. Regards, Hawking -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 18:16 To: Quan, Evan ; amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth Subject: RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence [AMD Official Use Only - Internal Distribution Only] Can you double check the following logic after your setup the TMR in psp_np_fw_load? For Arcturus and Navi12, it should be skipped as well. if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && (psp_smu_reload_quirk(psp) || psp->autoload_supported)) continue; Regards, Hawking -Original Message- From: Quan, Evan Sent: Monday, February 24, 2020 17:24 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Feng, Kenneth ; Quan, Evan Subject: [PATCH] drm/amdgpu: update psp firmwares loading sequence For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. Change-Id: I8986ddb4d9ffe63ed0823d1dce8d9d52812a1240 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 61 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 + 2 files changed, 58 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 51839ab02b84..ef800ad68e1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -38,6 +38,39 @@ static void psp_set_funcs(struct amdgpu_device *adev); +/* + * Due to DF Cstate management centralized to PMFW, the firmware + * loading sequence will be updated as below: + * - Load KDB + * - Load SYS_DRV + * - Load tOS + * - Load PMFW + * - Setup TMR + * - Load other non-psp fw + * - Load ASD + * - Load XGMI/RAS/HDCP/DTM TA if any + * + * This new sequence is required for + * - Arcturus + * - Navi12 and onwards + */ +static void psp_check_pmfw_centralized_cstate_management(struct +psp_context *psp) { + struct amdgpu_device *adev = psp->adev; + + psp->pmfw_centralized_cstate_management = false; + + if (amdgpu_sriov_vf(adev)) + return; + + if (adev->flags & AMD_IS_APU) + return; + + if ((adev->asic_type == CHIP_ARCTURUS) || + (adev->asic_type >= CHIP_NAVI12)) + psp->pmfw_centralized_cstate_management = true; } + static int psp_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -75,6 +108,8 @@ static int psp_early_init(void *handle) psp->adev = adev; + psp_check_pmfw_centralized_cstate_management(psp); + return 0; } @@ -1116,10 +1151,17 @@ static int psp_hw_start(struct psp_context *psp) return ret; } - ret = psp_tmr_load(psp); - if (ret) { - DRM_ERROR("PSP load tmr failed!\n"); - return ret; + /* +* For those ASICs with DF Cstate management centralized +* to PMFW, TMR setup should be performed after PMFW +* loaded and before other non-psp firmware loaded. +*/ + if (!psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } } return 0; @@ -1316,7 +1358,8 @@ static int psp_np_fw_load(struct psp_context *psp) struct amdgpu_firmware_info *ucode; struct amdgpu_device* adev = psp->adev; - if (psp->autoload_supported) { + if (psp->autoload_supported || + psp->pmfw_centralized_cstate_management) { ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; if (!ucode->fw || amdgpu_sriov_vf(adev))
RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence
[AMD Official Use Only - Internal Distribution Only] Sorry just for Navi12. Arcturus should be fine as it doesn't support autoload. Regards, Hawking -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 18:18 To: Quan, Evan ; 'amd-gfx@lists.freedesktop.org' Cc: Feng, Kenneth Subject: RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence [AMD Official Use Only - Internal Distribution Only] That's saying I suspect the PMFW was loaded twice with the patch for Arcturus and Navi12. Regards, Hawking -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 18:16 To: Quan, Evan ; amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth Subject: RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence [AMD Official Use Only - Internal Distribution Only] Can you double check the following logic after your setup the TMR in psp_np_fw_load? For Arcturus and Navi12, it should be skipped as well. if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && (psp_smu_reload_quirk(psp) || psp->autoload_supported)) continue; Regards, Hawking -Original Message- From: Quan, Evan Sent: Monday, February 24, 2020 17:24 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Feng, Kenneth ; Quan, Evan Subject: [PATCH] drm/amdgpu: update psp firmwares loading sequence For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. Change-Id: I8986ddb4d9ffe63ed0823d1dce8d9d52812a1240 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 61 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 + 2 files changed, 58 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 51839ab02b84..ef800ad68e1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -38,6 +38,39 @@ static void psp_set_funcs(struct amdgpu_device *adev); +/* + * Due to DF Cstate management centralized to PMFW, the firmware + * loading sequence will be updated as below: + * - Load KDB + * - Load SYS_DRV + * - Load tOS + * - Load PMFW + * - Setup TMR + * - Load other non-psp fw + * - Load ASD + * - Load XGMI/RAS/HDCP/DTM TA if any + * + * This new sequence is required for + * - Arcturus + * - Navi12 and onwards + */ +static void psp_check_pmfw_centralized_cstate_management(struct +psp_context *psp) { + struct amdgpu_device *adev = psp->adev; + + psp->pmfw_centralized_cstate_management = false; + + if (amdgpu_sriov_vf(adev)) + return; + + if (adev->flags & AMD_IS_APU) + return; + + if ((adev->asic_type == CHIP_ARCTURUS) || + (adev->asic_type >= CHIP_NAVI12)) + psp->pmfw_centralized_cstate_management = true; } + static int psp_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -75,6 +108,8 @@ static int psp_early_init(void *handle) psp->adev = adev; + psp_check_pmfw_centralized_cstate_management(psp); + return 0; } @@ -1116,10 +1151,17 @@ static int psp_hw_start(struct psp_context *psp) return ret; } - ret = psp_tmr_load(psp); - if (ret) { - DRM_ERROR("PSP load tmr failed!\n"); - return ret; + /* +* For those ASICs with DF Cstate management centralized +* to PMFW, TMR setup should be performed after PMFW +* loaded and before other non-psp firmware loaded. +*/ + if (!psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } } return 0; @@ -1316,7 +1358,8 @@ static int psp_np_fw_load(struct psp_context *psp) struct amdgpu_firmware_info *ucode; struct amdgpu_device* adev = psp->adev; - if (psp->autoload_supported) { + if (psp->autoload_supported || + psp->pmfw_centralized_cstate_management) { ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; if (!ucode->fw || amdgpu_sriov_vf(adev)) goto out; @@ -1326,6 +1369,14 @@ static int psp_np_fw_load(struct psp_context *psp) return ret; } + if (psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } + } + out: for (i = 0; i < adev->firmware.max_ucodes; i++) {
RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence
[AMD Official Use Only - Internal Distribution Only] That's saying I suspect the PMFW was loaded twice with the patch for Arcturus and Navi12. Regards, Hawking -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 18:16 To: Quan, Evan ; amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth Subject: RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence [AMD Official Use Only - Internal Distribution Only] Can you double check the following logic after your setup the TMR in psp_np_fw_load? For Arcturus and Navi12, it should be skipped as well. if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && (psp_smu_reload_quirk(psp) || psp->autoload_supported)) continue; Regards, Hawking -Original Message- From: Quan, Evan Sent: Monday, February 24, 2020 17:24 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Feng, Kenneth ; Quan, Evan Subject: [PATCH] drm/amdgpu: update psp firmwares loading sequence For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. Change-Id: I8986ddb4d9ffe63ed0823d1dce8d9d52812a1240 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 61 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 + 2 files changed, 58 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 51839ab02b84..ef800ad68e1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -38,6 +38,39 @@ static void psp_set_funcs(struct amdgpu_device *adev); +/* + * Due to DF Cstate management centralized to PMFW, the firmware + * loading sequence will be updated as below: + * - Load KDB + * - Load SYS_DRV + * - Load tOS + * - Load PMFW + * - Setup TMR + * - Load other non-psp fw + * - Load ASD + * - Load XGMI/RAS/HDCP/DTM TA if any + * + * This new sequence is required for + * - Arcturus + * - Navi12 and onwards + */ +static void psp_check_pmfw_centralized_cstate_management(struct +psp_context *psp) { + struct amdgpu_device *adev = psp->adev; + + psp->pmfw_centralized_cstate_management = false; + + if (amdgpu_sriov_vf(adev)) + return; + + if (adev->flags & AMD_IS_APU) + return; + + if ((adev->asic_type == CHIP_ARCTURUS) || + (adev->asic_type >= CHIP_NAVI12)) + psp->pmfw_centralized_cstate_management = true; } + static int psp_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -75,6 +108,8 @@ static int psp_early_init(void *handle) psp->adev = adev; + psp_check_pmfw_centralized_cstate_management(psp); + return 0; } @@ -1116,10 +1151,17 @@ static int psp_hw_start(struct psp_context *psp) return ret; } - ret = psp_tmr_load(psp); - if (ret) { - DRM_ERROR("PSP load tmr failed!\n"); - return ret; + /* +* For those ASICs with DF Cstate management centralized +* to PMFW, TMR setup should be performed after PMFW +* loaded and before other non-psp firmware loaded. +*/ + if (!psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } } return 0; @@ -1316,7 +1358,8 @@ static int psp_np_fw_load(struct psp_context *psp) struct amdgpu_firmware_info *ucode; struct amdgpu_device* adev = psp->adev; - if (psp->autoload_supported) { + if (psp->autoload_supported || + psp->pmfw_centralized_cstate_management) { ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; if (!ucode->fw || amdgpu_sriov_vf(adev)) goto out; @@ -1326,6 +1369,14 @@ static int psp_np_fw_load(struct psp_context *psp) return ret; } + if (psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } + } + out: for (i = 0; i < adev->firmware.max_ucodes; i++) { ucode = &adev->firmware.ucode[i]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index c77e1abb538a..37fa184f27f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -264,6 +264,8 @@ struct psp_context atomic_tfence_value; /* flag to mark whether gfx
RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence
[AMD Official Use Only - Internal Distribution Only] Can you double check the following logic after your setup the TMR in psp_np_fw_load? For Arcturus and Navi12, it should be skipped as well. if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && (psp_smu_reload_quirk(psp) || psp->autoload_supported)) continue; Regards, Hawking -Original Message- From: Quan, Evan Sent: Monday, February 24, 2020 17:24 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Feng, Kenneth ; Quan, Evan Subject: [PATCH] drm/amdgpu: update psp firmwares loading sequence For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. Change-Id: I8986ddb4d9ffe63ed0823d1dce8d9d52812a1240 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 61 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 + 2 files changed, 58 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 51839ab02b84..ef800ad68e1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -38,6 +38,39 @@ static void psp_set_funcs(struct amdgpu_device *adev); +/* + * Due to DF Cstate management centralized to PMFW, the firmware + * loading sequence will be updated as below: + * - Load KDB + * - Load SYS_DRV + * - Load tOS + * - Load PMFW + * - Setup TMR + * - Load other non-psp fw + * - Load ASD + * - Load XGMI/RAS/HDCP/DTM TA if any + * + * This new sequence is required for + * - Arcturus + * - Navi12 and onwards + */ +static void psp_check_pmfw_centralized_cstate_management(struct +psp_context *psp) { + struct amdgpu_device *adev = psp->adev; + + psp->pmfw_centralized_cstate_management = false; + + if (amdgpu_sriov_vf(adev)) + return; + + if (adev->flags & AMD_IS_APU) + return; + + if ((adev->asic_type == CHIP_ARCTURUS) || + (adev->asic_type >= CHIP_NAVI12)) + psp->pmfw_centralized_cstate_management = true; } + static int psp_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -75,6 +108,8 @@ static int psp_early_init(void *handle) psp->adev = adev; + psp_check_pmfw_centralized_cstate_management(psp); + return 0; } @@ -1116,10 +1151,17 @@ static int psp_hw_start(struct psp_context *psp) return ret; } - ret = psp_tmr_load(psp); - if (ret) { - DRM_ERROR("PSP load tmr failed!\n"); - return ret; + /* +* For those ASICs with DF Cstate management centralized +* to PMFW, TMR setup should be performed after PMFW +* loaded and before other non-psp firmware loaded. +*/ + if (!psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } } return 0; @@ -1316,7 +1358,8 @@ static int psp_np_fw_load(struct psp_context *psp) struct amdgpu_firmware_info *ucode; struct amdgpu_device* adev = psp->adev; - if (psp->autoload_supported) { + if (psp->autoload_supported || + psp->pmfw_centralized_cstate_management) { ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; if (!ucode->fw || amdgpu_sriov_vf(adev)) goto out; @@ -1326,6 +1369,14 @@ static int psp_np_fw_load(struct psp_context *psp) return ret; } + if (psp->pmfw_centralized_cstate_management) { + ret = psp_tmr_load(psp); + if (ret) { + DRM_ERROR("PSP load tmr failed!\n"); + return ret; + } + } + out: for (i = 0; i < adev->firmware.max_ucodes; i++) { ucode = &adev->firmware.ucode[i]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index c77e1abb538a..37fa184f27f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -264,6 +264,8 @@ struct psp_context atomic_tfence_value; /* flag to mark whether gfx fw autoload is supported or not */ boolautoload_supported; + /* flag to mark whether df cstate management centralized to PMFW */ + boolpmfw_centralized_cstate_management; /* xgmi ta firmware and buffer */ const struct firmware *ta_fw; -- 2.25.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx