[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/106914
>From be771da74a7663d56cdf850c10b4daa47c087bcc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 1 Sep 2024 09:35:34 -0700
Subject: [PATCH 1/3] [RISCV][VCIX] Precommit test
---
llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll | 22
1 file changed, 22 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
new file mode 100644
index 00..4ceb189ab6a46f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+; VCIX instructions can not reorder between each other.
+define void @test_reorder( %vreg) {
+; CHECK-LABEL: test_reorder:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:#APP
+; CHECK-NEXT:sf.vc.vv 3, 0, v8, v8
+; CHECK-EMPTY:
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:vsetivli zero, 0, e64, m1, ta, ma
+; CHECK-NEXT:sf.vc.iv 0, 0, v8, 0
+; CHECK-NEXT:ret
+entry:
+ call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen
0, %vreg, iXLen 0, iXLen 0)
+ call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;",
"=r,^vr,~{memory},~{vl},~{vcix_state}"( %vreg)
+ ret void
+}
>From 4e5bcccbbcd67770f52829a7966f1b260a39a165 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 1 Sep 2024 09:39:44 -0700
Subject: [PATCH 2/3] [RISCV][VCIX] Add vcix_state to GNU inline assembly
register set
Resolved https://github.com/llvm/llvm-project/issues/106700.
This enables inline asm to have vcix_state to be a clobbered register
thus disable reordering between VCIX intrinsics and inline asm.
---
clang/lib/Basic/Targets/RISCV.cpp| 2 +-
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 4
llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll | 6 +++---
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index b89109e7725d44..2ecff0648e6ce4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
};
// clang-format on
return llvm::ArrayRef(GCCRegNames);
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 5725d8eda88ced..d9e02f640893d9 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -666,3 +666,7 @@ def SSP: RISCVReg<0, "ssp">;
// Dummy SiFive VCIX state register
def SF_VCIX_STATE : RISCVReg<0, "sf.vcix_state">;
+def : RISCVRegisterClass<[XLenVT], 32, (add SF_VCIX_STATE)> {
+ let RegInfos = XLenRI;
+ let isAllocatable = 0;
+}
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
index 4ceb189ab6a46f..667c4ec628cf3a 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
@@ -8,15 +8,15 @@
define void @test_reorder( %vreg) {
; CHECK-LABEL: test_reorder:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetivli zero, 0, e64, m1, ta, ma
+; CHECK-NEXT:sf.vc.iv 0, 0, v8, 0
; CHECK-NEXT:#APP
; CHECK-NEXT:sf.vc.vv 3, 0, v8, v8
; CHECK-EMPTY:
; CHECK-NEXT:#NO_APP
-; CHECK-NEXT:vsetivli zero, 0, e64, m1, ta, ma
-; CHECK-NEXT:sf.vc.iv 0, 0, v8, 0
; CHECK-NEXT:ret
entry:
call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen
0, %vreg, iXLen 0, iXLen 0)
- call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;",
"=r,^vr,~{memory},~{vl},~{vcix_state}"( %vreg)
+ call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;",
"=r,^vr,~{memory},~{vl},~{sf_vcix_state}"( %vreg)
ret void
}
>From 5370538764c70e938681d8a320ac95bfb501f1c9 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Mon, 23 Sep 2024 00:10:58 -0700
Subject: [PATCH 3/3] fixup! [RISCV][VCIX] Add vcix_state to GNU inline
assembly register set
---
clang/lib/Basic/Targets/RISCV.cpp| 2 +-
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 6 ++
llvm/lib/Target/RISCV/RISCVRegisterInfo.h| 2 ++
llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll | 2 +-
4 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 2e
[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
4vtomat wrote:
Sure, let me add it!
https://github.com/llvm/llvm-project/pull/106914
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[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
4vtomat wrote:
I think here is the root cause:
https://github.com/llvm/llvm-project/blob/1e3a24d2e4eb63c17b962161ae6588d1b2c178f8/llvm/include/llvm/CodeGen/TargetRegisterInfo.h#L1106
Maybe we should overwrite this function for RISCV?
What do you think @jrtc27 @kito-cheng ?
https://github.com/llvm/llvm-project/pull/106914
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[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
4vtomat wrote:
```
#include
#include
int foo(__rvv_uint64m1_t vreg) {
auto vl = __riscv_vsetvl_e64m1(1);
// This VCIX instruction gets scheduled after the asm block below.
__riscv_sf_vc_iv_se_u64m1(0, 0, vreg, 0, vl);
asm volatile(
R"(
vsetivli zero, 2, e64, m1, ta, ma
sf.vc.vv 0x3, 0x0, %[vreg], %[vreg];
)"
: "=r"(vl)
: [vreg]"vr"(vreg)
: "memory", "vl", "sf_vcix_state");
return 0;
}
```
Use the code above as an example, it compiles to the llvm:
```
define dso_local noundef signext i32 @_Z3foou16__rvv_uint64m1_t( %vreg) local_unnamed_addr #0 {
entry:
%0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 3, i64 0)
tail call void @llvm.riscv.sf.vc.iv.se.i64.nxv1i64.i64.i64(i64 0, i64 0,
%vreg, i64 0, i64 %0)
%1 = tail call i64 asm sideeffect "\0Avsetivli zero, 2, e64, m1,
ta, ma\0Asf.vc.vv 0x3, 0x0, $1, $1;\0A ",
"=r,^vr,~{memory},~{vl},~{sf_vcix_state}"( %vreg)
ret i32 0
}
```
if we change `sf_vcix_state` to `sf.vcix_state`, the code doesn't work as
expected, the instruction is still reordered, so I doubt that the name here is
the defining name of the register in `RISCVRegisterInfo.td` rather than the
actually name of the register.
https://github.com/llvm/llvm-project/pull/106914
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[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
@@ -317,38 +323,45 @@ ABIArgInfo
RISCVABIInfo::coerceAndExpandFPCCEligibleStruct(
// Fixed-length RVV vectors are represented as scalable vectors in function
// args/return and must be coerced from fixed vectors.
-ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {
+ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty,
+ unsigned ArgABIVLen) const {
assert(Ty->isVectorType() && "expected vector type!");
const auto *VT = Ty->castAs();
assert(VT->getElementType()->isBuiltinType() && "expected builtin type!");
- auto VScale =
- getContext().getTargetInfo().getVScaleRange(getContext().getLangOpts());
-
unsigned NumElts = VT->getNumElements();
- llvm::Type *EltType;
- if (VT->getVectorKind() == VectorKind::RVVFixedLengthMask) {
-NumElts *= 8;
-EltType = llvm::Type::getInt1Ty(getVMContext());
+ llvm::ScalableVectorType *ResType;
+ llvm::Type *EltType = CGT.ConvertType(VT->getElementType());
+
+ if (ArgABIVLen == 0) {
+// RVV fixed-length vector
+auto VScale =
+
getContext().getTargetInfo().getVScaleRange(getContext().getLangOpts());
+
+if (VT->getVectorKind() == VectorKind::RVVFixedLengthMask) {
+ NumElts *= 8;
+ EltType = llvm::Type::getInt1Ty(getVMContext());
+}
+
+// The MinNumElts is simplified from equation:
+// NumElts / VScale =
+// (EltSize * NumElts / (VScale * RVVBitsPerBlock))
+//* (RVVBitsPerBlock / EltSize)
+ResType = llvm::ScalableVectorType::get(EltType, NumElts / VScale->first);
} else {
-assert(VT->getVectorKind() == VectorKind::RVVFixedLengthData &&
- "Unexpected vector kind");
-EltType = CGT.ConvertType(VT->getElementType());
+// Generic vector
+ResType = llvm::ScalableVectorType::get(
+EltType, NumElts * llvm::RISCV::RVVBitsPerBlock / ArgABIVLen);
4vtomat wrote:
> Do we need to protect this division from returning 0?
@kito-cheng How do we handle this, pass by scalar?
https://github.com/llvm/llvm-project/pull/100346
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[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
4vtomat wrote:
This is machine instruction name lol, if we use `sf.vcix_state`, it can't
recognize.
https://github.com/llvm/llvm-project/pull/106914
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[clang] [clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp. NFC (PR #106485)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/106485 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/106914
>From 32126871d3dae79edaaa03bd1760790ca8a42e84 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 1 Sep 2024 09:35:34 -0700
Subject: [PATCH 1/2] [RISCV][VCIX] Precommit test
---
llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll | 22
1 file changed, 22 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
new file mode 100644
index 00..4ceb189ab6a46f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+; VCIX instructions can not reorder between each other.
+define void @test_reorder( %vreg) {
+; CHECK-LABEL: test_reorder:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:#APP
+; CHECK-NEXT:sf.vc.vv 3, 0, v8, v8
+; CHECK-EMPTY:
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:vsetivli zero, 0, e64, m1, ta, ma
+; CHECK-NEXT:sf.vc.iv 0, 0, v8, 0
+; CHECK-NEXT:ret
+entry:
+ call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen
0, %vreg, iXLen 0, iXLen 0)
+ call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;",
"=r,^vr,~{memory},~{vl},~{vcix_state}"( %vreg)
+ ret void
+}
>From c8ae503c94192d2560fc516b133a1b7a6aef8a71 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 1 Sep 2024 09:39:44 -0700
Subject: [PATCH 2/2] [RISCV][VCIX] Add vcix_state to GNU inline assembly
register set
Resolved https://github.com/llvm/llvm-project/issues/106700.
This enables inline asm to have vcix_state to be a clobbered register
thus disable reordering between VCIX intrinsics and inline asm.
---
clang/lib/Basic/Targets/RISCV.cpp| 2 +-
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 4
llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll | 6 +++---
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index b89109e7725d44..2ecff0648e6ce4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
};
// clang-format on
return llvm::ArrayRef(GCCRegNames);
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index ce9f9e39154c2b..1d78f992d7a830 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -666,3 +666,7 @@ def SSP: RISCVReg<0, "ssp">;
// Dummy SiFive VCIX state register
def SF_VCIX_STATE : RISCVReg<0, "sf_vcix_state">;
+def : RISCVRegisterClass<[XLenVT], 32, (add SF_VCIX_STATE)> {
+ let RegInfos = XLenRI;
+ let isAllocatable = 0;
+}
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
index 4ceb189ab6a46f..667c4ec628cf3a 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
@@ -8,15 +8,15 @@
define void @test_reorder( %vreg) {
; CHECK-LABEL: test_reorder:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetivli zero, 0, e64, m1, ta, ma
+; CHECK-NEXT:sf.vc.iv 0, 0, v8, 0
; CHECK-NEXT:#APP
; CHECK-NEXT:sf.vc.vv 3, 0, v8, v8
; CHECK-EMPTY:
; CHECK-NEXT:#NO_APP
-; CHECK-NEXT:vsetivli zero, 0, e64, m1, ta, ma
-; CHECK-NEXT:sf.vc.iv 0, 0, v8, 0
; CHECK-NEXT:ret
entry:
call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen
0, %vreg, iXLen 0, iXLen 0)
- call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;",
"=r,^vr,~{memory},~{vl},~{vcix_state}"( %vreg)
+ call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;",
"=r,^vr,~{memory},~{vl},~{sf_vcix_state}"( %vreg)
ret void
}
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[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
4vtomat wrote: > > Do you mean change the current vcix_state register to sf.vcix_state? > > Yes, because it's SiFive specific register, other vendor may add other status > register like VCIX in future, so I would like to add prefix to make sure all > further similar stuff will follow same rule if possible Sure! I will do it in another patch since it's separate thing than this patch. https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
4vtomat wrote: > I would suggest it should prefix with a vendor prefix, either `sf.vcix_state` > or `sifive.vcix_state`, also go `riscv-c-api-doc` or > `riscv-toolchain-conventions` :) Do you mean change the current `vcix_state` register to `sf.vcix_state`? https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
@@ -664,5 +664,9 @@ def FRM: RISCVReg<0, "frm">;
// Shadow Stack register
def SSP: RISCVReg<0, "ssp">;
-// Dummy VCIX state register
+// Dummy VCIX state register and its register class
def VCIX_STATE : RISCVReg<0, "vcix_state">;
+def : RISCVRegisterClass<[XLenVT], 32, (add VCIX_STATE)> {
4vtomat wrote:
In `getRegForInlineAsmConstraint` if there would be no value in `AssignedRegs`
when calling `getRegistersForValue` for the `vcix_state` constraint, thus it
would be deprecated when constructing selectionDAG.
https://github.com/llvm/llvm-project/pull/106914
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[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/106914
[RISCV][VCIX] Add vcix_state to GNU inline assembly register set
Resolved https://github.com/llvm/llvm-project/issues/106700.
This enables inline asm to have vcix_state to be a clobbered register
thus disable reordering between VCIX intrinsics and inline asm.
>From 21f4687b58544bd08e8b6a4b76326fe956d87854 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 1 Sep 2024 09:35:34 -0700
Subject: [PATCH 1/2] [RISCV][VCIX] Precommit test
---
llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll | 22
1 file changed, 22 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
new file mode 100644
index 00..4ceb189ab6a46f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+; VCIX instructions can not reorder between each other.
+define void @test_reorder( %vreg) {
+; CHECK-LABEL: test_reorder:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:#APP
+; CHECK-NEXT:sf.vc.vv 3, 0, v8, v8
+; CHECK-EMPTY:
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:vsetivli zero, 0, e64, m1, ta, ma
+; CHECK-NEXT:sf.vc.iv 0, 0, v8, 0
+; CHECK-NEXT:ret
+entry:
+ call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen
0, %vreg, iXLen 0, iXLen 0)
+ call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;",
"=r,^vr,~{memory},~{vl},~{vcix_state}"( %vreg)
+ ret void
+}
>From 5f821a28b760efa20514a9080da1ae1127529138 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 1 Sep 2024 09:39:44 -0700
Subject: [PATCH 2/2] [RISCV][VCIX] Add vcix_state to GNU inline assembly
register set
Resolved https://github.com/llvm/llvm-project/issues/106700.
This enables inline asm to have vcix_state to be a clobbered register
thus disable reordering between VCIX intrinsics and inline asm.
---
clang/lib/Basic/Targets/RISCV.cpp| 2 +-
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 6 +-
llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll | 4 ++--
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index b89109e7725d44..da6ecfb4e4022b 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "vcix_state"
};
// clang-format on
return llvm::ArrayRef(GCCRegNames);
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 4d5c0a7bef9416..03f05c0baea3b0 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -664,5 +664,9 @@ def FRM: RISCVReg<0, "frm">;
// Shadow Stack register
def SSP: RISCVReg<0, "ssp">;
-// Dummy VCIX state register
+// Dummy VCIX state register and its register class
def VCIX_STATE : RISCVReg<0, "vcix_state">;
+def : RISCVRegisterClass<[XLenVT], 32, (add VCIX_STATE)> {
+ let RegInfos = XLenRI;
+ let isAllocatable = 0;
+}
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
index 4ceb189ab6a46f..0013461d873281 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
@@ -8,12 +8,12 @@
define void @test_reorder( %vreg) {
; CHECK-LABEL: test_reorder:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsetivli zero, 0, e64, m1, ta, ma
+; CHECK-NEXT:sf.vc.iv 0, 0, v8, 0
; CHECK-NEXT:#APP
; CHECK-NEXT:sf.vc.vv 3, 0, v8, v8
; CHECK-EMPTY:
; CHECK-NEXT:#NO_APP
-; CHECK-NEXT:vsetivli zero, 0, e64, m1, ta, ma
-; CHECK-NEXT:sf.vc.iv 0, 0, v8, 0
; CHECK-NEXT:ret
entry:
call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen
0, %vreg, iXLen 0, iXLen 0)
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[clang] [clang][RISCV] Remove `experimental` for vector crypto intrinsics (PR #106359)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/106359 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp. NFC (PR #106485)
@@ -733,7 +733,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
if (ElemSize == 64 && !TI.hasFeature("zvknhb"))
return Diag(TheCall->getBeginLoc(),
diag::err_riscv_builtin_requires_extension)
- << /* IsExtension */ true << TheCall->getSourceRange() << "zvknb";
+ << /* IsExtension */ true << TheCall->getSourceRange() <<
"zvknhb";
4vtomat wrote:
I think we can't, since the `RequiredFeatures` in `riscv_vector.td` already
blocks the intrinsic generation, I guess we don't even need this check, do we?
https://github.com/llvm/llvm-project/pull/106485
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[clang] [clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp. NFC (PR #106485)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/106485
None
>From 71c66235e06faa0a793f829276991832ce5e487c Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 28 Aug 2024 20:21:59 -0700
Subject: [PATCH] [clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp.
NFC
---
clang/lib/Sema/SemaRISCV.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index abf8e4ac2f3e8a..56d6f12fbc6e4a 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -733,7 +733,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
if (ElemSize == 64 && !TI.hasFeature("zvknhb"))
return Diag(TheCall->getBeginLoc(),
diag::err_riscv_builtin_requires_extension)
- << /* IsExtension */ true << TheCall->getSourceRange() << "zvknb";
+ << /* IsExtension */ true << TheCall->getSourceRange() <<
"zvknhb";
return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Op1Type,
ElemSize * 4) ||
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[clang] [clang][RISCV] Remove `experimental` for vector crypto intrinsics (PR #106359)
4vtomat wrote: > Do we still need this? > > ``` > def Experimental >: SubtargetFeature<"experimental", "HasExperimental", > "true", "Experimental intrinsics">; > ``` I guess we do in case there is any other extension that encounter the same situation lol~ https://github.com/llvm/llvm-project/pull/106359 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Remove `experimental` for vector crypto intrinsics (PR #106359)
https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/106359 The C intrinsic spec is ratified: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234. >From 59157100eac32981821eb15bce55d58f5f964bac Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Wed, 28 Aug 2024 03:32:43 -0700 Subject: [PATCH] [clang][RISCV] Remove `experimental` for vector crypto intrinsics The C intrinsic spec is ratified: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234. --- clang/include/clang/Basic/riscv_vector.td | 18 +- .../non-policy/non-overloaded/vaesdf.c | 1 - .../non-policy/non-overloaded/vaesdm.c | 1 - .../non-policy/non-overloaded/vaesef.c | 1 - .../non-policy/non-overloaded/vaesem.c | 1 - .../non-policy/non-overloaded/vaeskf1.c| 1 - .../non-policy/non-overloaded/vaeskf2.c| 1 - .../non-policy/non-overloaded/vaesz.c | 1 - .../non-policy/non-overloaded/vandn.c | 1 - .../non-policy/non-overloaded/vbrev.c | 1 - .../non-policy/non-overloaded/vbrev8.c | 1 - .../non-policy/non-overloaded/vclmul.c | 1 - .../non-policy/non-overloaded/vclmulh.c| 1 - .../non-policy/non-overloaded/vclz.c | 1 - .../non-policy/non-overloaded/vcpopv.c | 1 - .../non-policy/non-overloaded/vctz.c | 1 - .../non-policy/non-overloaded/vghsh.c | 1 - .../non-policy/non-overloaded/vgmul.c | 1 - .../non-policy/non-overloaded/vrev8.c | 1 - .../non-policy/non-overloaded/vrol.c | 1 - .../non-policy/non-overloaded/vror.c | 1 - .../non-policy/non-overloaded/vsha2ch.c| 1 - .../non-policy/non-overloaded/vsha2cl.c| 1 - .../non-policy/non-overloaded/vsha2ms.c| 1 - .../non-policy/non-overloaded/vsm3c.c | 1 - .../non-policy/non-overloaded/vsm3me.c | 1 - .../non-policy/non-overloaded/vsm4k.c | 1 - .../non-policy/non-overloaded/vsm4r.c | 1 - .../non-policy/non-overloaded/vwsll.c | 1 - .../non-policy/overloaded/vaesdf.c | 1 - .../non-policy/overloaded/vaesdm.c | 1 - .../non-policy/overloaded/vaesef.c | 1 - .../non-policy/overloaded/vaesem.c | 1 - .../non-policy/overloaded/vaeskf1.c| 1 - .../non-policy/overloaded/vaeskf2.c| 1 - .../non-policy/overloaded/vaesz.c | 1 - .../non-policy/overloaded/vandn.c | 1 - .../non-policy/overloaded/vbrev.c | 1 - .../non-policy/overloaded/vbrev8.c | 1 - .../non-policy/overloaded/vclmul.c | 1 - .../non-policy/overloaded/vclmulh.c| 1 - .../non-policy/overloaded/vclz.c | 1 - .../non-policy/overloaded/vcpopv.c | 1 - .../non-policy/overloaded/vctz.c | 1 - .../non-policy/overloaded/vghsh.c | 1 - .../non-policy/overloaded/vgmul.c | 1 - .../non-policy/overloaded/vrev8.c | 1 - .../non-policy/overloaded/vrol.c | 1 - .../non-policy/overloaded/vror.c | 1 - .../non-policy/overloaded/vsha2ch.c| 1 - .../non-policy/overloaded/vsha2cl.c| 1 - .../non-policy/overloaded/vsha2ms.c| 1 - .../non-policy/overloaded/vsm3c.c | 1 - .../non-policy/overloaded/vsm3me.c | 1 - .../non-policy/overloaded/vsm4k.c | 1 - .../non-policy/overloaded/vsm4r.c | 1 - .../non-policy/overloaded/vwsll.c | 1 - .../policy/non-overloaded/vaesdf.c | 1 - .../policy/non-overloaded/vaesdm.c | 1 - .../policy/non-overloaded/vaesef.c | 1 - .../policy/non-overloaded/vaesem.c | 1 - .../policy/non-overloaded/vaeskf1.c| 1 - .../policy/non-overloaded/vaeskf2.c| 1 - .../policy/non-overloaded/vaesz.c | 1 - .../policy/non-overloaded/vandn.c | 1 - .../policy/non-overloaded/vbrev.c | 1 - .../policy/non-overloaded/vbrev8.c | 1 - .../policy/non-overloaded/vclmul.c | 1 - .../policy/non-overloaded/vclmulh.c| 1 - .../policy/non-overloaded/vclz.c | 1 - .../policy/non-overloaded/vcpopv.c | 1 - .../policy/non-overloaded/vctz.c | 1 - .../policy/non-overloaded/vghsh.c | 1 - .../policy/non-overloaded/vgmul.c | 1 - .../policy/non-overloaded/vrev8.c | 1 - .../policy/non-overloaded/vrol.c | 1 - .../policy/non-overloaded/vror.c | 1 - .../policy/non-overloaded/vsha2ch.c| 1 - .../policy/non-overloaded/vsha2cl.c| 1 - .../policy/non-overloaded/vsha2ms.c| 1 - .../policy/non-overloaded/vsm3c.c | 1 - .../policy/non-overloaded/vs
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/100346
>From 15161b0b7637d52b6285624a4bf9f52a6664082c Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 21 Jul 2024 09:49:11 -0700
Subject: [PATCH 1/6] [RISCV][VLS] Support RISCV VLS calling convention
This patch adds a function attribute `riscv_vls_cc` for RISCV VLS calling
convention which takes 0 or 1 argument, the argument is the `ABI_VLEN`
which is the `VLEN` for passing the fixed-vector arguments, it wraps the
argument as a scalable vector(VLA) using the `ABI_VLEN` and uses the
corresponding mechanism to handle it. The range of `ABI_VLEN` is [32, 65536],
if not specified, the default value is 128.
An option `-mriscv-abi-vlen=N` is also added to specify the `ABI_VLEN`
globally, it's used for every functions are being compiled, however if
both function attribute and option are specified, the function attribute
has higher priority than the option which means the function attribute
overwrites the `ABI_VLEN` specified by the option.
Here is an example of VLS argument passing:
Non-VLS call:
```
void original_call(__attribute__((vector_size(16))) int arg) {}
=>
define void @original_call(i128 noundef %arg) {
entry:
...
ret void
}
```
VLS call:
```
void __attribute__((riscv_vls_cc(256)))
vls_call(__attribute__((vector_size(16))) int arg) {}
=>
define riscv_vls_cc void @vls_call( %arg) {
entry:
...
ret void
}
}
```
The first Non-VLS call passes generic vector argument of 16 bytes by
flattened integer.
On the contrary, the VLS call uses `ABI_VLEN=256` which wraps the
vector to where the number of scalable vector elements
is calaulated by: `ORIG_ELTS * RVV_BITS_PER_BLOCK / ABI_VLEN`.
Note: ORIG_ELTS = Vector Size / Type Size = 128 / 32 = 4.
---
clang/include/clang-c/Index.h | 1 +
clang/include/clang/AST/Type.h| 26 +--
clang/include/clang/AST/TypeProperties.td | 7 +-
clang/include/clang/Basic/Attr.td | 8 ++
clang/include/clang/Basic/AttrDocs.td | 11 +++
clang/include/clang/Basic/Specifiers.h| 1 +
clang/include/clang/CodeGen/CGFunctionInfo.h | 9 ++-
clang/include/clang/Driver/Options.td | 2 +
clang/lib/AST/ASTContext.cpp | 2 +
clang/lib/AST/ItaniumMangle.cpp | 1 +
clang/lib/AST/Type.cpp| 2 +
clang/lib/AST/TypePrinter.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.cpp | 1 +
clang/lib/CodeGen/CGCall.cpp | 5 ++
clang/lib/CodeGen/CGDebugInfo.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 73 ---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp| 4 +
clang/lib/Sema/SemaDeclAttr.cpp | 30 +++-
clang/lib/Sema/SemaType.cpp | 17 -
.../RISCV/riscv-vector-callingconv-llvm-ir.c | 24 ++
.../riscv-vector-callingconv-llvm-ir.cpp | 14
.../CodeGen/RISCV/riscv-vector-callingconv.c | 16
.../RISCV/riscv-vector-callingconv.cpp| 17 +
clang/tools/libclang/CXType.cpp | 1 +
llvm/include/llvm/AsmParser/LLToken.h | 1 +
llvm/include/llvm/BinaryFormat/Dwarf.def | 1 +
llvm/include/llvm/IR/CallingConv.h| 3 +
llvm/lib/AsmParser/LLLexer.cpp| 1 +
llvm/lib/AsmParser/LLParser.cpp | 4 +
llvm/lib/IR/AsmWriter.cpp | 3 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 9 +++
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 1 +
33 files changed, 265 insertions(+), 39 deletions(-)
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index 115f5ab090f96e..159f21846fc3b2 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -3005,6 +3005,7 @@ enum CXCallingConv {
CXCallingConv_M68kRTD = 19,
CXCallingConv_PreserveNone = 20,
CXCallingConv_RISCVVectorCall = 21,
+ CXCallingConv_RISCVVLSCall = 22,
CXCallingConv_Invalid = 100,
CXCallingConv_Unexposed = 200
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 72723c7c56e078..bb3956b1d2094c 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -1942,7 +1942,7 @@ class alignas(TypeAlignment) Type : public
ExtQualsTypeCommonBase {
/// Extra information which affects how the function is called, like
/// regparm and the calling convention.
LLVM_PREFERRED_TYPE(CallingConv)
-unsigned ExtInfo : 13;
+unsigned ExtInfo : 17;
/// The ref-qualifier associated with a \c FunctionProtoType.
///
@@ -4395,6 +4395,8 @@ class FunctionType : public Type {
// | CC
|noreturn|produces|nocallersavedregs|regparm|nocfcheck|cmsenscall|
// |0 .. 4| 5|6 | 7 |8 .. 10|11 |12
|
+// |RISCV-ABI-VLEN|
+// |13..17|
//
// r
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
@@ -2206,6 +2206,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
<< A->getSpelling() << Val;
}
}
+
+ if (Arg *A = Args.getLastArg(options::OPT_mriscv_abi_vlen_EQ)) {
+StringRef ABIVLenStr = A->getValue();
+unsigned ABIVLen;
+const Driver &D = getToolChain().getDriver();
+if (ABIVLenStr.getAsInteger(10, ABIVLen) || ABIVLen < 128 ||
4vtomat wrote:
Correct, it supports 32 and 64 also, I'll correct it.
https://github.com/llvm/llvm-project/pull/100346
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[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)
@@ -754,6 +754,17 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, AssemblerPredicate<(all_of FeatureStdExtZvbc), "'Zvbc' (Vector Carryless Multiplication)">; +def FeatureStdExtZvbc32e +: RISCVExperimentalExtension<"zvbc32e", 0, 7, + "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)">; +def HasStdExtZvbc32e : Predicate<"Subtarget->hasStdExtZvbc32e()">, 4vtomat wrote: Does this have any user? https://github.com/llvm/llvm-project/pull/103709 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)
@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint =
NoConstraint in {
SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
} // Predicates = [HasStdExtZvkg]
+let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {
4vtomat wrote:
I guess the spec didn't state that for `.vv` version?
https://github.com/llvm/llvm-project/pull/103709
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[clang] [RISCV][clang] Remove bfloat base type in non-zvfbfmin vcreate (PR #102146)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/102146 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add missing `zvfbfmin` to `vget_v` intrinsic (PR #102149)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/102149 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add missing `zvfbfmin` to `vget_v` intrinsic (PR #102149)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/102149
It's missing in the patch supporting `zvfbfmin` intrinsics.
>From 17cbf0b868699a04639c49acf4bbf383e70e85ca Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 6 Aug 2024 07:06:13 -0700
Subject: [PATCH] [RISCV][clang] Add missing `zvfbfmin` to `vget_v` intrinsic
It's missing in the patch supporting `zvfbfmin` intrinsics.
---
clang/include/clang/Basic/riscv_vector.td | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index dda2dcb9f4ff6..69ac87297149c 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2547,12 +2547,16 @@ let HasMasked = false, HasVL = false, IRName = "" in {
}
}] in {
foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)",
"(SFixedLog2LMUL:2)"] in {
- def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfdy",
dst_lmul # "v">;
+ def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfd",
dst_lmul # "v">;
+ let RequiredFeatures = ["Zvfbfmin"] in
+def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "y",
dst_lmul # "v">;
def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil",
dst_lmul # "Uv">;
}
foreach nf = NFList in {
defvar T = "(Tuple:" # nf # ")";
- def : RVVBuiltin;
+ def : RVVBuiltin;
+ let RequiredFeatures = ["Zvfbfmin"] in
+def : RVVBuiltin;
def : RVVBuiltin;
}
}
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[clang] [RISCV][clang] Remove bfloat base type in non-zvfbfmin vcreate (PR #102146)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/102146
None
>From 9ca5156a494d7f88ea80a960e2515142ae867ba8 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 6 Aug 2024 06:56:48 -0700
Subject: [PATCH] [RISCV][clang] Remove bfloat base type in non-zvfbfmin
vcreate
---
clang/include/clang/Basic/riscv_vector.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index dda2dcb9f4ff6..2a1bebecf3d3d 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2633,7 +2633,7 @@ let HasMasked = false, HasVL = false, IRName = "" in {
defvar T = "(Tuple:" # nf # ")";
defvar V = VString.S;
defvar UV = VString.S;
-def : RVVBuiltin;
+def : RVVBuiltin;
let RequiredFeatures = ["Zvfbfmin"] in
def : RVVBuiltin;
def : RVVBuiltin;
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[clang] [RISCV][sema] Correct the requirement of `vf[n|w]cvt.x[|u].f` intrinsics (PR #101811)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/101811 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support `vrgather` and `vcompress` for `zvfhmin` and `zvfbfmin` (PR #101633)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/101633 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support bf16 vmv.v.v and vmerge.vvm intrinsics with `zvfbfmin` (PR #101611)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/101611 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][sema] Correct the requirement of `vf[n|w]cvt.x[|u].f` intrinsics (PR #101811)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/101811
Fix https://github.com/llvm/llvm-project/issues/101526
`vf[n|w]cvt.x[|u].f` for f16 needs `zvfh` instead of `zvfhmin`, current approach
is not able to detect this. Ultimately we need to add `zvfh` to RequiredFeatures
to check other intrinsics instead, the type check should be done in
checkRVVTypeSupport.
>From 1ffab9fdd26c9fd3e6524a26ca23cbd5535da377 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 3 Aug 2024 03:28:25 -0700
Subject: [PATCH] [RISCV][sema] Correct the requirement of `vf[n|w]cvt.x[|u].f`
intrinsics
Fix https://github.com/llvm/llvm-project/issues/101526
`vf[n|w]cvt.x[|u].f` for f16 needs `zvfh` instead of `zvfhmin`, current approach
is not able to detect this. Ultimately we need to add `zvfh` to RequiredFeatures
to check other intrinsics instead, the type check should be done in
checkRVVTypeSupport.
---
clang/include/clang/Basic/riscv_vector.td | 48 ---
.../clang/Basic/riscv_vector_common.td| 4 +-
.../clang/Support/RISCVVIntrinsicUtils.h | 3 +-
clang/lib/Sema/SemaRISCV.cpp | 6 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 1 +
5 files changed, 53 insertions(+), 9 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 0cab4b8067f0d..662771d640b69 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1912,8 +1912,18 @@ def vfcvt_rtz_x_f_v :
RVVConvToSignedBuiltin<"vfcvt_rtz_x">;
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">;
def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
- def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
- def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
+ def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "si", "vfwcvt_f">;
+ def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "si", "vfwcvt_f">;
+ let RequiredFeatures = ["Zvfh"] in {
+let Name = "vfwcvt_f_xu_v",
+IRName = "vfwcvt_f_xu_v",
+MaskedIRName = "vfwcvt_f_xu_v_mask" in
+ def : RVVConvBuiltin<"Fw", "FwUv", "c", "vfwcvt_f">;
+let Name = "vfwcvt_f_x_v",
+IRName = "vfwcvt_f_x_v",
+MaskedIRName = "vfwcvt_f_x_v_mask" in
+ def : RVVConvBuiltin<"Fw", "Fwv", "c", "vfwcvt_f">;
+ }
def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">;
let RequiredFeatures = ["Zvfhmin"] in
def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> {
@@ -1927,6 +1937,16 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_xu_f_w : RVVConvToNarrowingUnsignedBuiltin<"vfncvt_rtz_xu">;
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
+ let RequiredFeatures = ["Zvfh"] in {
+let Name = "vfncvt_rtz_xu_f_w",
+IRName = "vfncvt_rtz_xu_f_w",
+MaskedIRName = "vfncvt_rtz_xu_f_w_mask" in
+ def : RVVConvBuiltin<"Uv", "UvFw", "c", "vfncvt_rtz_xu">;
+let Name = "vfncvt_rtz_x_f_w",
+IRName = "vfncvt_rtz_x_f_w",
+MaskedIRName = "vfncvt_rtz_x_f_w_mask" in
+ def : RVVConvBuiltin<"Iv", "IvFw", "c", "vfncvt_rtz_x">;
+ }
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
@@ -2005,10 +2025,18 @@ let ManualCodegen = [{
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
let OverloadedName = "vfncvt_x" in
defm :
- RVVConvBuiltinSet<"vfncvt_x_f_w", "csi", [["Iv", "IvFwu"]]>;
+ RVVConvBuiltinSet<"vfncvt_x_f_w", "si", [["Iv", "IvFwu"]]>;
let OverloadedName = "vfncvt_xu" in
defm :
- RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
+ RVVConvBuiltinSet<"vfncvt_xu_f_w", "si", [["Uv", "UvFwu"]]>;
+ let RequiredFeatures = ["Zvfh"] in {
+let OverloadedName = "vfncvt_x" in
+ defm :
+RVVConvBuiltinSet<"vfncvt_x_f_w", "c", [["Iv", "IvFwu"]]>;
+let OverloadedName = "vfncvt_xu" in
+ defm :
+RVVConvBuiltinSet<"vfncvt_xu_f_w", "c", [["Uv", "UvFwu"]]>;
+ }
let OverloadedName = "vfncvt_f" in {
defm :
RVVConvBuiltinSet<"vfncvt_f_x_w", "xf", [["v", "vIwu"]]>;
@@ -2055,10 +2083,18 @@ let ManualCodegen = [{
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
let OverloadedName = "vfncvt_x" in
defm :
-RVVConvBuiltinSet<"vfncvt_x_f_w", "csi", [["Iv", "IvFw"]]>;
+RVVConvBuiltinSet<"vfncvt_x_f_w", "si", [["Iv", "IvFw"]]>;
let OverloadedName = "vfncvt_xu" in
defm :
-RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFw"]]>;
+RVVConvBuiltinSet<"vfncvt_xu_f_w", "si", [["Uv", "UvFw"]]>;
+let RequiredFeatures = ["Zvfh"] in {
+ let OverloadedName = "vfncvt_x" in
+defm :
+ RVVConvBuiltinSet<"vfncvt_x_f_w", "c", [["Iv", "IvF
[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
4vtomat wrote: This has been resolved by: https://github.com/llvm/llvm-project/pull/101733 https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Use FP type as the base type for some int->f conversions. (PR #101733)
https://github.com/4vtomat approved this pull request. LGTM~ https://github.com/llvm/llvm-project/pull/101733 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][NFC] Remove unneeded defining name of `vundefined` (PR #101643)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/101643 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][NFC] Remove unneeded defining name of `vundefined` (PR #101643)
4vtomat wrote: > I don't think this will be better. We may keep these names so that these code > can be self-explanatory. Yeah, it's reasonable to me. https://github.com/llvm/llvm-project/pull/101643 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Remove unused base type in `vfncvt` (PR #101646)
4vtomat wrote: > Make sense to me. > (Do we have a way to test these generated builtins?) I think we don't since the intrinsics are generated on demand during runtime. https://github.com/llvm/llvm-project/pull/101646 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Remove unused base type in `vfncvt` (PR #101646)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/101646
We don't have `fp8` type supported yet.
>From ff5083431d41d22c50725638b084bfb2532dad74 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 2 Aug 2024 03:04:18 -0700
Subject: [PATCH] [RISCV][clang] Remove unused base type in `vfncvt`
We don't have `fp8` type supported yet.
---
clang/include/clang/Basic/riscv_vector.td | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index a0820e2093bc2..4841792c91d4a 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2011,9 +2011,9 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"vfncvt_f_x_w", "si", [["Fv", "Fvwu"]]>;
defm :
- RVVConvBuiltinSet<"vfncvt_f_xu_w", "csi", [["Fv", "FvUwu"]]>;
+ RVVConvBuiltinSet<"vfncvt_f_xu_w", "si", [["Fv", "FvUwu"]]>;
}
let OverloadedName = "vfncvt_f" in {
defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vwu"]]>;
@@ -2061,9 +2061,9 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFw"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
-RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvw"]]>;
+RVVConvBuiltinSet<"vfncvt_f_x_w", "si", [["Fv", "Fvw"]]>;
defm :
-RVVConvBuiltinSet<"vfncvt_f_xu_w", "csi", [["Fv", "FvUw"]]>;
+RVVConvBuiltinSet<"vfncvt_f_xu_w", "si", [["Fv", "FvUw"]]>;
}
let OverloadedName = "vfncvt_f" in {
defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vw"]]>;
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[clang] [RISCV][NFC] Remove unneeded defining name of `vundefined` (PR #101643)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/101643
`vundefined` doesn't have corresponding named IR, instead it generates
`poison` value, we already define the `Name` for C intrinsics, so we
don't need the defining name at all.
>From df6b40a85ca89259751583b66429d59e92f4fe6d Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 2 Aug 2024 02:15:33 -0700
Subject: [PATCH] [RISCV][NFC] Remove unneeded defining name of `vundefined`
`vundefined` doesn't have corresponding named IR, instead it generates
`poison` value, we already define the `Name` for C intrinsics, so we
don't need the defining name at all.
---
clang/include/clang/Basic/riscv_vector.td | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index a0820e2093bc2..13d2efb4e6109 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2407,10 +2407,10 @@ let HasMasked = false, HasVL = false, IRName = "" in {
ManualCodegen = [{
return llvm::PoisonValue::get(ResultType);
}] in {
-def vundefined : RVVBuiltin<"v", "v", "csilxfd">;
+def : RVVBuiltin<"v", "v", "csilxfd">;
let RequiredFeatures = ["Zvfbfmin"] in
- def vundefined_bf16 : RVVBuiltin<"v", "v", "y">;
-def vundefined_u : RVVBuiltin<"Uv", "Uv", "csil">;
+ def : RVVBuiltin<"v", "v", "y">;
+def : RVVBuiltin<"Uv", "Uv", "csil">;
foreach nf = NFList in {
let NF = nf in {
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[clang] [llvm] [RISCV] Support `vrgather` and `vcompress` for `zvfhmin` and `zvfbfmin` (PR #101633)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/101633 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
@@ -2011,9 +2021,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"vfncvt_f_x_w", "ci", [["Fv", "Fvwu"]]>;
4vtomat wrote:
Yeah, I think we are not able to handle this in current approach, I'll have
another PR to use the `RequiredFeatures` and remove current type checking
approach.
https://github.com/llvm/llvm-project/pull/101608
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[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
@@ -2011,9 +2021,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"vfncvt_f_x_w", "ci", [["Fv", "Fvwu"]]>;
4vtomat wrote:
So we don't need to support `fp->int` conversion in `zvfbfmin` which is in this
example: https://godbolt.org/z/Khfx8j6jW right?
https://github.com/llvm/llvm-project/pull/101608
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[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
@@ -2011,9 +2021,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"vfncvt_f_x_w", "ci", [["Fv", "Fvwu"]]>;
4vtomat wrote:
I'm a bit confused, the
[spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#184-zvfhmin-vector-extension-for-minimal-half-precision-floating-point)
says `When the Zvfhmin extension is implemented, the vfwcvt.f.f.v and
vfncvt.f.f.w instructions become defined when SEW=16. `. Does it mean we
`zvfhmin` only supports those 2 version of conversion, or it means those 2
version are included?
https://github.com/llvm/llvm-project/pull/101608
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[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
@@ -1912,8 +1912,12 @@ def vfcvt_rtz_x_f_v :
RVVConvToSignedBuiltin<"vfcvt_rtz_x">;
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">;
def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
- def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
- def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
+ def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "si", "vfwcvt_f">;
+ def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "si", "vfwcvt_f">;
+ let RequiredFeatures = ["Zvfh"], OverloadedName = "vfwcvt_f" in {
+defm : RVVConvBuiltinSet<"vfwcvt_f_xu_v", "c", [["Fw", "FwUv"]]>;
4vtomat wrote:
`Name`, `IRName`, `MaskedIRName` uses `NAME` which is the defining name as
default, but "si" case already used for defining name, if we use the same name
for defining the "c" case, it would be multiple definition.
https://github.com/llvm/llvm-project/pull/101608
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[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
@@ -2011,9 +2021,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"vfncvt_f_x_w", "ci", [["Fv", "Fvwu"]]>;
4vtomat wrote:
This is `int->f` conversion, I think the `f->int` version is already handled by
current approach, isn't it?
https://github.com/llvm/llvm-project/pull/101608
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[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
@@ -2011,9 +2021,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
let OverloadedName = "vfncvt_f" in {
defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
+ RVVConvBuiltinSet<"vfncvt_f_x_w", "ci", [["Fv", "Fvwu"]]>;
4vtomat wrote:
I think we don't need to support `c` here, since we don't have `f8` supported
yet.
https://github.com/llvm/llvm-project/pull/101608
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
4vtomat wrote: > What about vfncvt and vfwcvt? Added! https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][sema] Correct the requirement of `vf[|n|w]cvt.f.*` intrinsics (PR #101608)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][sema] Correct the requirement of `vfcvt.f.*` intrinsics (PR #101608)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][sema] Correct the requirement of `vfcvt.f.*` intrinsics (PR #101608)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/101608
>From 47a757769f5f1a25861227167c8409dd53875eaa Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 1 Aug 2024 20:21:01 -0700
Subject: [PATCH 1/2] [RISCV][sema] Correct the requirement of
`vf[|n|w]cvt.f.*` intrinsics
Fix https://github.com/llvm/llvm-project/issues/101526
`vf[|n|w]cvt.f.*` for f16 needs `zvfh` instead of `zvfhmin`, current approach
is not able to detect this. Ultimately we need to add `zvfh` to RequiredFeatures
to check other intrinsics instead, the type check should be done in
checkRVVTypeSupport.
---
clang/include/clang/Basic/riscv_vector.td | 20 +++
.../clang/Support/RISCVVIntrinsicUtils.h | 3 ++-
clang/lib/Sema/SemaRISCV.cpp | 6 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 1 +
4 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index a0820e2093bc2..93617b3e28429 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1987,9 +1987,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfcvt_xu_f_v", "xfd", [["Uv", "Uvvu"]]>;
let OverloadedName = "vfcvt_f" in {
defm :
-RVVConvBuiltinSet<"vfcvt_f_x_v", "sil", [["Fv", "Fvvu"]]>;
+RVVConvBuiltinSet<"vfcvt_f_x_v", "il", [["Fv", "Fvvu"]]>;
defm :
-RVVConvBuiltinSet<"vfcvt_f_xu_v", "sil", [["Fv", "FvUvu"]]>;
+RVVConvBuiltinSet<"vfcvt_f_xu_v", "il", [["Fv", "FvUvu"]]>;
+ let RequiredFeatures = ["Zvfh"] in {
+defm :
+ RVVConvBuiltinSet<"vfcvt_f_x_v", "s", [["Fv", "Fvvu"]]>;
+defm :
+ RVVConvBuiltinSet<"vfcvt_f_xu_v", "s", [["Fv", "FvUvu"]]>;
+ }
}
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
@@ -2037,9 +2043,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfcvt_xu_f_v", "xfd", [["Uv", "Uvv"]]>;
let OverloadedName = "vfcvt_f" in {
defm :
- RVVConvBuiltinSet<"vfcvt_f_x_v", "sil", [["Fv", "Fvv"]]>;
+ RVVConvBuiltinSet<"vfcvt_f_x_v", "il", [["Fv", "Fvv"]]>;
defm :
- RVVConvBuiltinSet<"vfcvt_f_xu_v", "sil", [["Fv", "FvUv"]]>;
+ RVVConvBuiltinSet<"vfcvt_f_xu_v", "il", [["Fv", "FvUv"]]>;
+let RequiredFeatures = ["Zvfh"] in {
+ defm :
+RVVConvBuiltinSet<"vfcvt_f_x_v", "s", [["Fv", "Fvv"]]>;
+ defm :
+RVVConvBuiltinSet<"vfcvt_f_xu_v", "s", [["Fv", "FvUv"]]>;
+}
}
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index b4ff61784126e..9a6a2092eb996 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -502,7 +502,8 @@ enum RVVRequire : uint32_t {
RVV_REQ_Zvksh = 1 << 15,
RVV_REQ_Zvfbfwma = 1 << 16,
RVV_REQ_Zvfbfmin = 1 << 17,
- RVV_REQ_Experimental = 1 << 18,
+ RVV_REQ_Zvfh = 1 << 18,
+ RVV_REQ_Experimental = 1 << 19,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Experimental)
};
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index f1c7c0516e671..abf8e4ac2f3e8 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -222,6 +222,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
{"zvksh", RVV_REQ_Zvksh},
{"zvfbfwma", RVV_REQ_Zvfbfwma},
{"zvfbfmin", RVV_REQ_Zvfbfmin},
+ {"zvfh", RVV_REQ_Zvfh},
{"experimental", RVV_REQ_Experimental}};
// Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
@@ -280,6 +281,11 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
continue;
+ // TODO: Remove the check below and use RequiredFeatures in
+ // riscv_vector.td to check the intrinsics instead, the type check should
+ // be done in checkRVVTypeSupport. This check also not able to work on
the
+ // intrinsics that have Float16 but the BaseType is not Float16 such as
+ // `vfcvt_f_x_v`.
if (BaseType == BasicType::Float16) {
if ((Record.RequiredExtensions & RVV_REQ_Zvfhmin) == RVV_REQ_Zvfhmin) {
if (!TI.hasFeature("zvfhmin"))
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index 7f3cb70c97d09..ef7159fae9fd2 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -670,6 +670,7 @@ void RVVEmitter::createRVVIntrinsics(
.Case("Zvksh", RVV_REQ_Zvksh)
.Case("Zvfbfwma", RVV_REQ_Zvfbfwma)
.Case("Zvfbfmin", RVV_REQ_Zvfbfmin)
+ .Case("Zvfh", RVV_REQ_Zvfh)
.Case("Experimental", RVV_REQ_Experimental)
.Default(RVV_REQ_None);
assert(RequireExt != RVV_
[clang] [RISCV][sema] Correct the requirement of `vfcvt.f.*` intrinsics (PR #101608)
4vtomat wrote: Reword https://github.com/llvm/llvm-project/pull/101608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][sema] Correct the requirement of `vfcvt.f.*` intrinsics (PR #101608)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/101608
>From e12d3e8d28bc9d26bf3f5425841c00d95840a8f2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 1 Aug 2024 20:21:01 -0700
Subject: [PATCH 1/2] [RISCV][sema] Correct the requirement of `vfcvt.f.*`
intrinsics
Fix https://github.com/llvm/llvm-project/issues/101526
`vfcvt.f.*` needs `zvfh` instead of `zvfhmin`, current approach is not
able to detect this. Ultimately we need to add `zvfh` to RequiredFeatures
to check the intrinsics instead, the type check should be done in
checkRVVTypeSupport.
---
clang/include/clang/Basic/riscv_vector.td | 20 +++
.../clang/Support/RISCVVIntrinsicUtils.h | 3 ++-
clang/lib/Sema/SemaRISCV.cpp | 6 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 1 +
4 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index a0820e2093bc2..93617b3e28429 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1987,9 +1987,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfcvt_xu_f_v", "xfd", [["Uv", "Uvvu"]]>;
let OverloadedName = "vfcvt_f" in {
defm :
-RVVConvBuiltinSet<"vfcvt_f_x_v", "sil", [["Fv", "Fvvu"]]>;
+RVVConvBuiltinSet<"vfcvt_f_x_v", "il", [["Fv", "Fvvu"]]>;
defm :
-RVVConvBuiltinSet<"vfcvt_f_xu_v", "sil", [["Fv", "FvUvu"]]>;
+RVVConvBuiltinSet<"vfcvt_f_xu_v", "il", [["Fv", "FvUvu"]]>;
+ let RequiredFeatures = ["Zvfh"] in {
+defm :
+ RVVConvBuiltinSet<"vfcvt_f_x_v", "s", [["Fv", "Fvvu"]]>;
+defm :
+ RVVConvBuiltinSet<"vfcvt_f_xu_v", "s", [["Fv", "FvUvu"]]>;
+ }
}
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
@@ -2037,9 +2043,15 @@ let ManualCodegen = [{
RVVConvBuiltinSet<"vfcvt_xu_f_v", "xfd", [["Uv", "Uvv"]]>;
let OverloadedName = "vfcvt_f" in {
defm :
- RVVConvBuiltinSet<"vfcvt_f_x_v", "sil", [["Fv", "Fvv"]]>;
+ RVVConvBuiltinSet<"vfcvt_f_x_v", "il", [["Fv", "Fvv"]]>;
defm :
- RVVConvBuiltinSet<"vfcvt_f_xu_v", "sil", [["Fv", "FvUv"]]>;
+ RVVConvBuiltinSet<"vfcvt_f_xu_v", "il", [["Fv", "FvUv"]]>;
+let RequiredFeatures = ["Zvfh"] in {
+ defm :
+RVVConvBuiltinSet<"vfcvt_f_x_v", "s", [["Fv", "Fvv"]]>;
+ defm :
+RVVConvBuiltinSet<"vfcvt_f_xu_v", "s", [["Fv", "FvUv"]]>;
+}
}
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index b4ff61784126e..9a6a2092eb996 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -502,7 +502,8 @@ enum RVVRequire : uint32_t {
RVV_REQ_Zvksh = 1 << 15,
RVV_REQ_Zvfbfwma = 1 << 16,
RVV_REQ_Zvfbfmin = 1 << 17,
- RVV_REQ_Experimental = 1 << 18,
+ RVV_REQ_Zvfh = 1 << 18,
+ RVV_REQ_Experimental = 1 << 19,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Experimental)
};
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index f1c7c0516e671..abf8e4ac2f3e8 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -222,6 +222,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
{"zvksh", RVV_REQ_Zvksh},
{"zvfbfwma", RVV_REQ_Zvfbfwma},
{"zvfbfmin", RVV_REQ_Zvfbfmin},
+ {"zvfh", RVV_REQ_Zvfh},
{"experimental", RVV_REQ_Experimental}};
// Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
@@ -280,6 +281,11 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
continue;
+ // TODO: Remove the check below and use RequiredFeatures in
+ // riscv_vector.td to check the intrinsics instead, the type check should
+ // be done in checkRVVTypeSupport. This check also not able to work on
the
+ // intrinsics that have Float16 but the BaseType is not Float16 such as
+ // `vfcvt_f_x_v`.
if (BaseType == BasicType::Float16) {
if ((Record.RequiredExtensions & RVV_REQ_Zvfhmin) == RVV_REQ_Zvfhmin) {
if (!TI.hasFeature("zvfhmin"))
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index 7f3cb70c97d09..ef7159fae9fd2 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -670,6 +670,7 @@ void RVVEmitter::createRVVIntrinsics(
.Case("Zvksh", RVV_REQ_Zvksh)
.Case("Zvfbfwma", RVV_REQ_Zvfbfwma)
.Case("Zvfbfmin", RVV_REQ_Zvfbfmin)
+ .Case("Zvfh", RVV_REQ_Zvfh)
.Case("Experimental", RVV_REQ_Experimental)
.Default(RVV_REQ_None);
assert(RequireExt != RVV_REQ_None && "Unrecogniz
[clang] [llvm] [RISCV] Support bf16 vmv.v.v and vmerge.vvm intrinsics with `zvfbfmin` (PR #101611)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/101611
>From 53a18518189239643fade3cb6c636ebf1e4351da Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 1 Aug 2024 21:05:12 -0700
Subject: [PATCH 1/2] [RISCV] Support bf16 vmv.v.v and vmerge.vvm intrinsics
with `zvfbfmin`
These two intrinsics are supported for f16 with `zvfhmin`, also support
them in bf16 to make it aligned to f16.
---
clang/include/clang/Basic/riscv_vector.td | 6 ++
.../non-policy/non-overloaded/vmerge.c| 61 +-
.../non-policy/overloaded/vmerge.c| 62 ++-
.../policy/non-overloaded/vmerge.c| 62 ++-
.../policy/overloaded/vmerge.c| 62 ++-
.../Target/RISCV/RISCVInstrInfoVPseudos.td| 8 +++
6 files changed, 257 insertions(+), 4 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index a0820e2093bc2..e4e936f914f6f 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1378,6 +1378,9 @@ let HasMasked = false,
let RequiredFeatures = ["Zvfhmin"] in
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "x",
[["v", "v", "vv"]]>;
+let RequiredFeatures = ["Zvfbfmin"] in
+ defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "y",
+[["v", "v", "vv"]]>;
let SupportOverloading = false in
defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil",
[["x", "v", "ve"],
@@ -1890,6 +1893,9 @@ let HasMasked = false,
let RequiredFeatures = ["Zvfhmin"] in
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "x",
[["vvm", "v", "vvvm"]]>;
+ let RequiredFeatures = ["Zvfbfmin"] in
+defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "y",
+ [["vvm", "v", "vvvm"]]>;
defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
[["vfm", "v", "vvem"]]>;
}
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
index fb41a07cccec0..d2eb01c70950e 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
@@ -1,7 +1,7 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
-// RUN: -target-feature +zvfhmin -disable-O0-optnone \
+// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin
-disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
@@ -1037,3 +1037,62 @@ vfloat64m8_t test_vmerge_vvm_f64m8(vfloat64m8_t op1,
vfloat64m8_t op2, vbool8_t
return __riscv_vmerge_vvm_f64m8(op1, op2, mask, vl);
}
+// CHECK-RV64-LABEL: define dso_local
@test_vmerge_vvm_bf16mf4
+// CHECK-RV64-SAME: ( [[OP1:%.*]],
[[OP2:%.*]], [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]]
{
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vmerge.nxv1bf16.nxv1bf16.i64( poison, [[OP1]], [[OP2]],
[[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret [[TMP0]]
+//
+vbfloat16mf4_t test_vmerge_vvm_bf16mf4(vbfloat16mf4_t op1, vbfloat16mf4_t op2,
vbool64_t mask, size_t vl) {
+ return __riscv_vmerge_vvm_bf16mf4(op1, op2, mask, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local
@test_vmerge_vvm_bf16mf2
+// CHECK-RV64-SAME: ( [[OP1:%.*]],
[[OP2:%.*]], [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]]
{
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vmerge.nxv2bf16.nxv2bf16.i64( poison, [[OP1]], [[OP2]],
[[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret [[TMP0]]
+//
+vbfloat16mf2_t test_vmerge_vvm_bf16mf2(vbfloat16mf2_t op1, vbfloat16mf2_t op2,
vbool32_t mask, size_t vl) {
+ return __riscv_vmerge_vvm_bf16mf2(op1, op2, mask, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local
@test_vmerge_vvm_bf16m1
+// CHECK-RV64-SAME: ( [[OP1:%.*]],
[[OP2:%.*]], [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]]
{
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vmerge.nxv4bf16.nxv4bf16.i64( poison, [[OP1]], [[OP2]],
[[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret [[TMP0]]
+//
+vbfloat16m1_t test_vmerge_vvm_bf16m1(vbfloat16m1_t op1, vbfloat16m1_t op2,
vbool16_t mask, size_t vl) {
+ return __riscv_vmerge_vvm_bf16m1(op1, op2, mask, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local
@test_vmerge_vvm_bf16m2
+// CHECK-RV64-SAME: ( [[OP1:%.*]],
[[OP2:%.*]], [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[A
[clang] [llvm] [RISCV] Support bf16 vmv.v.v and vmerge.vvm intrinsics with `zvfbfmin` (PR #101611)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/101611
These two intrinsics are supported for f16 with `zvfhmin`, also support
them in bf16 to make it aligned to f16.
>From 53a18518189239643fade3cb6c636ebf1e4351da Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 1 Aug 2024 21:05:12 -0700
Subject: [PATCH] [RISCV] Support bf16 vmv.v.v and vmerge.vvm intrinsics with
`zvfbfmin`
These two intrinsics are supported for f16 with `zvfhmin`, also support
them in bf16 to make it aligned to f16.
---
clang/include/clang/Basic/riscv_vector.td | 6 ++
.../non-policy/non-overloaded/vmerge.c| 61 +-
.../non-policy/overloaded/vmerge.c| 62 ++-
.../policy/non-overloaded/vmerge.c| 62 ++-
.../policy/overloaded/vmerge.c| 62 ++-
.../Target/RISCV/RISCVInstrInfoVPseudos.td| 8 +++
6 files changed, 257 insertions(+), 4 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index a0820e2093bc2..e4e936f914f6f 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1378,6 +1378,9 @@ let HasMasked = false,
let RequiredFeatures = ["Zvfhmin"] in
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "x",
[["v", "v", "vv"]]>;
+let RequiredFeatures = ["Zvfbfmin"] in
+ defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "y",
+[["v", "v", "vv"]]>;
let SupportOverloading = false in
defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil",
[["x", "v", "ve"],
@@ -1890,6 +1893,9 @@ let HasMasked = false,
let RequiredFeatures = ["Zvfhmin"] in
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "x",
[["vvm", "v", "vvvm"]]>;
+ let RequiredFeatures = ["Zvfbfmin"] in
+defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "y",
+ [["vvm", "v", "vvvm"]]>;
defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
[["vfm", "v", "vvem"]]>;
}
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
index fb41a07cccec0..d2eb01c70950e 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
@@ -1,7 +1,7 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
-// RUN: -target-feature +zvfhmin -disable-O0-optnone \
+// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin
-disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
@@ -1037,3 +1037,62 @@ vfloat64m8_t test_vmerge_vvm_f64m8(vfloat64m8_t op1,
vfloat64m8_t op2, vbool8_t
return __riscv_vmerge_vvm_f64m8(op1, op2, mask, vl);
}
+// CHECK-RV64-LABEL: define dso_local
@test_vmerge_vvm_bf16mf4
+// CHECK-RV64-SAME: ( [[OP1:%.*]],
[[OP2:%.*]], [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]]
{
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vmerge.nxv1bf16.nxv1bf16.i64( poison, [[OP1]], [[OP2]],
[[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret [[TMP0]]
+//
+vbfloat16mf4_t test_vmerge_vvm_bf16mf4(vbfloat16mf4_t op1, vbfloat16mf4_t op2,
vbool64_t mask, size_t vl) {
+ return __riscv_vmerge_vvm_bf16mf4(op1, op2, mask, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local
@test_vmerge_vvm_bf16mf2
+// CHECK-RV64-SAME: ( [[OP1:%.*]],
[[OP2:%.*]], [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]]
{
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vmerge.nxv2bf16.nxv2bf16.i64( poison, [[OP1]], [[OP2]],
[[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret [[TMP0]]
+//
+vbfloat16mf2_t test_vmerge_vvm_bf16mf2(vbfloat16mf2_t op1, vbfloat16mf2_t op2,
vbool32_t mask, size_t vl) {
+ return __riscv_vmerge_vvm_bf16mf2(op1, op2, mask, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local
@test_vmerge_vvm_bf16m1
+// CHECK-RV64-SAME: ( [[OP1:%.*]],
[[OP2:%.*]], [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]]
{
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vmerge.nxv4bf16.nxv4bf16.i64( poison, [[OP1]], [[OP2]],
[[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret [[TMP0]]
+//
+vbfloat16m1_t test_vmerge_vvm_bf16m1(vbfloat16m1_t op1, vbfloat16m1_t op2,
vbool16_t mask, size_t vl) {
+ return __riscv_vmerge_vvm_bf16m1(op1, op2, mask, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local
@test_vm
[clang] [RISCV] Use Zvhmin instead of Zvfh on RUN lines for some intrinsic tests. NFC (PR #101540)
https://github.com/4vtomat approved this pull request. LGTM~ https://github.com/llvm/llvm-project/pull/101540 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Use Zvhmin instead of Zvfh on RUN lines for some intrinsic tests (PR #101540)
4vtomat wrote: Do we want vget/vset/vcreate/vundefined use `zvfhmin` rather than `zvfh`? https://github.com/llvm/llvm-project/pull/101540 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/100346
>From 15161b0b7637d52b6285624a4bf9f52a6664082c Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 21 Jul 2024 09:49:11 -0700
Subject: [PATCH 1/5] [RISCV][VLS] Support RISCV VLS calling convention
This patch adds a function attribute `riscv_vls_cc` for RISCV VLS calling
convention which takes 0 or 1 argument, the argument is the `ABI_VLEN`
which is the `VLEN` for passing the fixed-vector arguments, it wraps the
argument as a scalable vector(VLA) using the `ABI_VLEN` and uses the
corresponding mechanism to handle it. The range of `ABI_VLEN` is [32, 65536],
if not specified, the default value is 128.
An option `-mriscv-abi-vlen=N` is also added to specify the `ABI_VLEN`
globally, it's used for every functions are being compiled, however if
both function attribute and option are specified, the function attribute
has higher priority than the option which means the function attribute
overwrites the `ABI_VLEN` specified by the option.
Here is an example of VLS argument passing:
Non-VLS call:
```
void original_call(__attribute__((vector_size(16))) int arg) {}
=>
define void @original_call(i128 noundef %arg) {
entry:
...
ret void
}
```
VLS call:
```
void __attribute__((riscv_vls_cc(256)))
vls_call(__attribute__((vector_size(16))) int arg) {}
=>
define riscv_vls_cc void @vls_call( %arg) {
entry:
...
ret void
}
}
```
The first Non-VLS call passes generic vector argument of 16 bytes by
flattened integer.
On the contrary, the VLS call uses `ABI_VLEN=256` which wraps the
vector to where the number of scalable vector elements
is calaulated by: `ORIG_ELTS * RVV_BITS_PER_BLOCK / ABI_VLEN`.
Note: ORIG_ELTS = Vector Size / Type Size = 128 / 32 = 4.
---
clang/include/clang-c/Index.h | 1 +
clang/include/clang/AST/Type.h| 26 +--
clang/include/clang/AST/TypeProperties.td | 7 +-
clang/include/clang/Basic/Attr.td | 8 ++
clang/include/clang/Basic/AttrDocs.td | 11 +++
clang/include/clang/Basic/Specifiers.h| 1 +
clang/include/clang/CodeGen/CGFunctionInfo.h | 9 ++-
clang/include/clang/Driver/Options.td | 2 +
clang/lib/AST/ASTContext.cpp | 2 +
clang/lib/AST/ItaniumMangle.cpp | 1 +
clang/lib/AST/Type.cpp| 2 +
clang/lib/AST/TypePrinter.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.cpp | 1 +
clang/lib/CodeGen/CGCall.cpp | 5 ++
clang/lib/CodeGen/CGDebugInfo.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 73 ---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp| 4 +
clang/lib/Sema/SemaDeclAttr.cpp | 30 +++-
clang/lib/Sema/SemaType.cpp | 17 -
.../RISCV/riscv-vector-callingconv-llvm-ir.c | 24 ++
.../riscv-vector-callingconv-llvm-ir.cpp | 14
.../CodeGen/RISCV/riscv-vector-callingconv.c | 16
.../RISCV/riscv-vector-callingconv.cpp| 17 +
clang/tools/libclang/CXType.cpp | 1 +
llvm/include/llvm/AsmParser/LLToken.h | 1 +
llvm/include/llvm/BinaryFormat/Dwarf.def | 1 +
llvm/include/llvm/IR/CallingConv.h| 3 +
llvm/lib/AsmParser/LLLexer.cpp| 1 +
llvm/lib/AsmParser/LLParser.cpp | 4 +
llvm/lib/IR/AsmWriter.cpp | 3 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 9 +++
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 1 +
33 files changed, 265 insertions(+), 39 deletions(-)
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index 115f5ab090f96..159f21846fc3b 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -3005,6 +3005,7 @@ enum CXCallingConv {
CXCallingConv_M68kRTD = 19,
CXCallingConv_PreserveNone = 20,
CXCallingConv_RISCVVectorCall = 21,
+ CXCallingConv_RISCVVLSCall = 22,
CXCallingConv_Invalid = 100,
CXCallingConv_Unexposed = 200
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 72723c7c56e07..bb3956b1d2094 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -1942,7 +1942,7 @@ class alignas(TypeAlignment) Type : public
ExtQualsTypeCommonBase {
/// Extra information which affects how the function is called, like
/// regparm and the calling convention.
LLVM_PREFERRED_TYPE(CallingConv)
-unsigned ExtInfo : 13;
+unsigned ExtInfo : 17;
/// The ref-qualifier associated with a \c FunctionProtoType.
///
@@ -4395,6 +4395,8 @@ class FunctionType : public Type {
// | CC
|noreturn|produces|nocallersavedregs|regparm|nocfcheck|cmsenscall|
// |0 .. 4| 5|6 | 7 |8 .. 10|11 |12
|
+// |RISCV-ABI-VLEN|
+// |13..17|
//
// regpa
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
@@ -4768,6 +4768,15 @@ static void handleCallConvAttr(Sema &S, Decl *D, const
ParsedAttr &AL) {
case ParsedAttr::AT_RISCVVectorCC:
D->addAttr(::new (S.Context) RISCVVectorCCAttr(S.Context, AL));
return;
+ case ParsedAttr::AT_RISCVVLSCC: {
+// If the riscv_abi_vlen doesn't have any argument, default ABI_VLEN is
128.
+unsigned VectorLength = 128;
+if (AL.getNumArgs() &&
+!S.checkUInt32Argument(AL, AL.getArgAsExpr(0), VectorLength))
+ return;
4vtomat wrote:
I guess no, I'll check it here.
https://github.com/llvm/llvm-project/pull/100346
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[clang] [NFC][clang] Fix typo of `riscv_rvv_vector_bits` in AttrDocs (PR #101046)
https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/101046 None >From 1d756559b956f24d144c6819d264df062ec7d2cb Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 29 Jul 2024 10:44:05 -0700 Subject: [PATCH] [NFC][clang] Fix typo of `riscv_rvv_vector_bits` in AttrDocs --- clang/include/clang/Basic/AttrDocs.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index b5d468eb5ec95..4b8d520d73893 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -2453,7 +2453,7 @@ For example: typedef vint8m1_t fixed_vint8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); #endif -Creates a type ``fixed_vint8m1_t_t`` that is a fixed-length variant of +Creates a type ``fixed_vint8m1_t`` that is a fixed-length variant of ``vint8m1_t`` that contains exactly 512 bits. Unlike ``vint8m1_t``, this type can be used in globals, structs, unions, and arrays, all of which are unsupported for sizeless types. ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/100346
>From 15161b0b7637d52b6285624a4bf9f52a6664082c Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 21 Jul 2024 09:49:11 -0700
Subject: [PATCH 1/4] [RISCV][VLS] Support RISCV VLS calling convention
This patch adds a function attribute `riscv_vls_cc` for RISCV VLS calling
convention which takes 0 or 1 argument, the argument is the `ABI_VLEN`
which is the `VLEN` for passing the fixed-vector arguments, it wraps the
argument as a scalable vector(VLA) using the `ABI_VLEN` and uses the
corresponding mechanism to handle it. The range of `ABI_VLEN` is [32, 65536],
if not specified, the default value is 128.
An option `-mriscv-abi-vlen=N` is also added to specify the `ABI_VLEN`
globally, it's used for every functions are being compiled, however if
both function attribute and option are specified, the function attribute
has higher priority than the option which means the function attribute
overwrites the `ABI_VLEN` specified by the option.
Here is an example of VLS argument passing:
Non-VLS call:
```
void original_call(__attribute__((vector_size(16))) int arg) {}
=>
define void @original_call(i128 noundef %arg) {
entry:
...
ret void
}
```
VLS call:
```
void __attribute__((riscv_vls_cc(256)))
vls_call(__attribute__((vector_size(16))) int arg) {}
=>
define riscv_vls_cc void @vls_call( %arg) {
entry:
...
ret void
}
}
```
The first Non-VLS call passes generic vector argument of 16 bytes by
flattened integer.
On the contrary, the VLS call uses `ABI_VLEN=256` which wraps the
vector to where the number of scalable vector elements
is calaulated by: `ORIG_ELTS * RVV_BITS_PER_BLOCK / ABI_VLEN`.
Note: ORIG_ELTS = Vector Size / Type Size = 128 / 32 = 4.
---
clang/include/clang-c/Index.h | 1 +
clang/include/clang/AST/Type.h| 26 +--
clang/include/clang/AST/TypeProperties.td | 7 +-
clang/include/clang/Basic/Attr.td | 8 ++
clang/include/clang/Basic/AttrDocs.td | 11 +++
clang/include/clang/Basic/Specifiers.h| 1 +
clang/include/clang/CodeGen/CGFunctionInfo.h | 9 ++-
clang/include/clang/Driver/Options.td | 2 +
clang/lib/AST/ASTContext.cpp | 2 +
clang/lib/AST/ItaniumMangle.cpp | 1 +
clang/lib/AST/Type.cpp| 2 +
clang/lib/AST/TypePrinter.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.cpp | 1 +
clang/lib/CodeGen/CGCall.cpp | 5 ++
clang/lib/CodeGen/CGDebugInfo.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 73 ---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp| 4 +
clang/lib/Sema/SemaDeclAttr.cpp | 30 +++-
clang/lib/Sema/SemaType.cpp | 17 -
.../RISCV/riscv-vector-callingconv-llvm-ir.c | 24 ++
.../riscv-vector-callingconv-llvm-ir.cpp | 14
.../CodeGen/RISCV/riscv-vector-callingconv.c | 16
.../RISCV/riscv-vector-callingconv.cpp| 17 +
clang/tools/libclang/CXType.cpp | 1 +
llvm/include/llvm/AsmParser/LLToken.h | 1 +
llvm/include/llvm/BinaryFormat/Dwarf.def | 1 +
llvm/include/llvm/IR/CallingConv.h| 3 +
llvm/lib/AsmParser/LLLexer.cpp| 1 +
llvm/lib/AsmParser/LLParser.cpp | 4 +
llvm/lib/IR/AsmWriter.cpp | 3 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 9 +++
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 1 +
33 files changed, 265 insertions(+), 39 deletions(-)
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index 115f5ab090f96..159f21846fc3b 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -3005,6 +3005,7 @@ enum CXCallingConv {
CXCallingConv_M68kRTD = 19,
CXCallingConv_PreserveNone = 20,
CXCallingConv_RISCVVectorCall = 21,
+ CXCallingConv_RISCVVLSCall = 22,
CXCallingConv_Invalid = 100,
CXCallingConv_Unexposed = 200
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 72723c7c56e07..bb3956b1d2094 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -1942,7 +1942,7 @@ class alignas(TypeAlignment) Type : public
ExtQualsTypeCommonBase {
/// Extra information which affects how the function is called, like
/// regparm and the calling convention.
LLVM_PREFERRED_TYPE(CallingConv)
-unsigned ExtInfo : 13;
+unsigned ExtInfo : 17;
/// The ref-qualifier associated with a \c FunctionProtoType.
///
@@ -4395,6 +4395,8 @@ class FunctionType : public Type {
// | CC
|noreturn|produces|nocallersavedregs|regparm|nocfcheck|cmsenscall|
// |0 .. 4| 5|6 | 7 |8 .. 10|11 |12
|
+// |RISCV-ABI-VLEN|
+// |13..17|
//
// regpa
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
@@ -1333,6 +1333,15 @@ def Experimental : SubtargetFeature<"experimental", "HasExperimental", "true", "Experimental intrinsics">; +def FeatureABIVLen32B 4vtomat wrote: Yeah, that's a good idea since the backend doesn't use them~ https://github.com/llvm/llvm-project/pull/100346 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
@@ -608,6 +608,9 @@ class CGFunctionInfo final /// Log 2 of the maximum vector width. unsigned MaxVectorWidth : 4; + /// Log2 of ABI_VLEN used in RISCV VLS calling convention. + unsigned Log2RISCVABIVLen : 4; 4vtomat wrote: Yes, we need 5 bits, thanks for finding out that! https://github.com/llvm/llvm-project/pull/100346 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/100346
>From dc4d11d0e9665f42b27de4bfb73c9756b007518d Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 21 Jul 2024 09:49:11 -0700
Subject: [PATCH 1/3] [RISCV][VLS] Support RISCV VLS calling convention
This patch adds a function attribute `riscv_vls_cc` for RISCV VLS calling
convention which takes 0 or 1 argument, the argument is the `ABI_VLEN`
which is the `VLEN` for passing the fixed-vector arguments, it wraps the
argument as a scalable vector(VLA) using the `ABI_VLEN` and uses the
corresponding mechanism to handle it. The range of `ABI_VLEN` is [32, 65536],
if not specified, the default value is 128.
An option `-mriscv-abi-vlen=N` is also added to specify the `ABI_VLEN`
globally, it's used for every functions are being compiled, however if
both function attribute and option are specified, the function attribute
has higher priority than the option which means the function attribute
overwrites the `ABI_VLEN` specified by the option.
Here is an example of VLS argument passing:
Non-VLS call:
```
void original_call(__attribute__((vector_size(16))) int arg) {}
=>
define void @original_call(i128 noundef %arg) {
entry:
...
ret void
}
```
VLS call:
```
void __attribute__((riscv_vls_cc(256)))
vls_call(__attribute__((vector_size(16))) int arg) {}
=>
define riscv_vls_cc void @vls_call( %arg) {
entry:
...
ret void
}
}
```
The first Non-VLS call passes generic vector argument of 16 bytes by
flattened integer.
On the contrary, the VLS call uses `ABI_VLEN=256` which wraps the
vector to where the number of scalable vector elements
is calaulated by: `ORIG_ELTS * RVV_BITS_PER_BLOCK / ABI_VLEN`.
Note: ORIG_ELTS = Vector Size / Type Size = 128 / 32 = 4.
---
clang/include/clang-c/Index.h | 1 +
clang/include/clang/AST/Type.h| 26 +--
clang/include/clang/AST/TypeProperties.td | 7 +-
clang/include/clang/Basic/Attr.td | 8 ++
clang/include/clang/Basic/AttrDocs.td | 11 +++
clang/include/clang/Basic/Specifiers.h| 1 +
clang/include/clang/CodeGen/CGFunctionInfo.h | 9 ++-
clang/include/clang/Driver/Options.td | 2 +
clang/lib/AST/ASTContext.cpp | 2 +
clang/lib/AST/ItaniumMangle.cpp | 1 +
clang/lib/AST/Type.cpp| 2 +
clang/lib/AST/TypePrinter.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.cpp | 1 +
clang/lib/CodeGen/CGCall.cpp | 5 ++
clang/lib/CodeGen/CGDebugInfo.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 73 ---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp| 4 +
clang/lib/Sema/SemaDeclAttr.cpp | 30 +++-
clang/lib/Sema/SemaType.cpp | 17 -
.../RISCV/riscv-vector-callingconv-llvm-ir.c | 24 ++
.../riscv-vector-callingconv-llvm-ir.cpp | 14
.../CodeGen/RISCV/riscv-vector-callingconv.c | 16
.../RISCV/riscv-vector-callingconv.cpp| 17 +
clang/tools/libclang/CXType.cpp | 1 +
llvm/include/llvm/AsmParser/LLToken.h | 1 +
llvm/include/llvm/BinaryFormat/Dwarf.def | 1 +
llvm/include/llvm/IR/CallingConv.h| 3 +
llvm/lib/AsmParser/LLLexer.cpp| 1 +
llvm/lib/AsmParser/LLParser.cpp | 4 +
llvm/lib/IR/AsmWriter.cpp | 3 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 9 +++
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 1 +
33 files changed, 265 insertions(+), 39 deletions(-)
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index 115f5ab090f96..159f21846fc3b 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -3005,6 +3005,7 @@ enum CXCallingConv {
CXCallingConv_M68kRTD = 19,
CXCallingConv_PreserveNone = 20,
CXCallingConv_RISCVVectorCall = 21,
+ CXCallingConv_RISCVVLSCall = 22,
CXCallingConv_Invalid = 100,
CXCallingConv_Unexposed = 200
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 25defea58c2dc..d1c6e629e296c 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -1942,7 +1942,7 @@ class alignas(TypeAlignment) Type : public
ExtQualsTypeCommonBase {
/// Extra information which affects how the function is called, like
/// regparm and the calling convention.
LLVM_PREFERRED_TYPE(CallingConv)
-unsigned ExtInfo : 13;
+unsigned ExtInfo : 17;
/// The ref-qualifier associated with a \c FunctionProtoType.
///
@@ -4395,6 +4395,8 @@ class FunctionType : public Type {
// | CC
|noreturn|produces|nocallersavedregs|regparm|nocfcheck|cmsenscall|
// |0 .. 4| 5|6 | 7 |8 .. 10|11 |12
|
+// |RISCV-ABI-VLEN|
+// |13..17|
//
// regpa
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
@@ -2281,6 +2282,9 @@ bool LLParser::parseOptionalCallingConv(unsigned &CC) {
case lltok::kw_riscv_vector_cc:
CC = CallingConv::RISCV_VectorCall;
break;
+ case lltok::kw_riscv_vls_cc:
+CC = CallingConv::RISCV_VLSCall;
4vtomat wrote:
Done!
https://github.com/llvm/llvm-project/pull/100346
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[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/100346
>From dc4d11d0e9665f42b27de4bfb73c9756b007518d Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 21 Jul 2024 09:49:11 -0700
Subject: [PATCH 1/2] [RISCV][VLS] Support RISCV VLS calling convention
This patch adds a function attribute `riscv_vls_cc` for RISCV VLS calling
convention which takes 0 or 1 argument, the argument is the `ABI_VLEN`
which is the `VLEN` for passing the fixed-vector arguments, it wraps the
argument as a scalable vector(VLA) using the `ABI_VLEN` and uses the
corresponding mechanism to handle it. The range of `ABI_VLEN` is [32, 65536],
if not specified, the default value is 128.
An option `-mriscv-abi-vlen=N` is also added to specify the `ABI_VLEN`
globally, it's used for every functions are being compiled, however if
both function attribute and option are specified, the function attribute
has higher priority than the option which means the function attribute
overwrites the `ABI_VLEN` specified by the option.
Here is an example of VLS argument passing:
Non-VLS call:
```
void original_call(__attribute__((vector_size(16))) int arg) {}
=>
define void @original_call(i128 noundef %arg) {
entry:
...
ret void
}
```
VLS call:
```
void __attribute__((riscv_vls_cc(256)))
vls_call(__attribute__((vector_size(16))) int arg) {}
=>
define riscv_vls_cc void @vls_call( %arg) {
entry:
...
ret void
}
}
```
The first Non-VLS call passes generic vector argument of 16 bytes by
flattened integer.
On the contrary, the VLS call uses `ABI_VLEN=256` which wraps the
vector to where the number of scalable vector elements
is calaulated by: `ORIG_ELTS * RVV_BITS_PER_BLOCK / ABI_VLEN`.
Note: ORIG_ELTS = Vector Size / Type Size = 128 / 32 = 4.
---
clang/include/clang-c/Index.h | 1 +
clang/include/clang/AST/Type.h| 26 +--
clang/include/clang/AST/TypeProperties.td | 7 +-
clang/include/clang/Basic/Attr.td | 8 ++
clang/include/clang/Basic/AttrDocs.td | 11 +++
clang/include/clang/Basic/Specifiers.h| 1 +
clang/include/clang/CodeGen/CGFunctionInfo.h | 9 ++-
clang/include/clang/Driver/Options.td | 2 +
clang/lib/AST/ASTContext.cpp | 2 +
clang/lib/AST/ItaniumMangle.cpp | 1 +
clang/lib/AST/Type.cpp| 2 +
clang/lib/AST/TypePrinter.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.cpp | 1 +
clang/lib/CodeGen/CGCall.cpp | 5 ++
clang/lib/CodeGen/CGDebugInfo.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 73 ---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp| 4 +
clang/lib/Sema/SemaDeclAttr.cpp | 30 +++-
clang/lib/Sema/SemaType.cpp | 17 -
.../RISCV/riscv-vector-callingconv-llvm-ir.c | 24 ++
.../riscv-vector-callingconv-llvm-ir.cpp | 14
.../CodeGen/RISCV/riscv-vector-callingconv.c | 16
.../RISCV/riscv-vector-callingconv.cpp| 17 +
clang/tools/libclang/CXType.cpp | 1 +
llvm/include/llvm/AsmParser/LLToken.h | 1 +
llvm/include/llvm/BinaryFormat/Dwarf.def | 1 +
llvm/include/llvm/IR/CallingConv.h| 3 +
llvm/lib/AsmParser/LLLexer.cpp| 1 +
llvm/lib/AsmParser/LLParser.cpp | 4 +
llvm/lib/IR/AsmWriter.cpp | 3 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 9 +++
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 1 +
33 files changed, 265 insertions(+), 39 deletions(-)
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index 115f5ab090f96..159f21846fc3b 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -3005,6 +3005,7 @@ enum CXCallingConv {
CXCallingConv_M68kRTD = 19,
CXCallingConv_PreserveNone = 20,
CXCallingConv_RISCVVectorCall = 21,
+ CXCallingConv_RISCVVLSCall = 22,
CXCallingConv_Invalid = 100,
CXCallingConv_Unexposed = 200
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 25defea58c2dc..d1c6e629e296c 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -1942,7 +1942,7 @@ class alignas(TypeAlignment) Type : public
ExtQualsTypeCommonBase {
/// Extra information which affects how the function is called, like
/// regparm and the calling convention.
LLVM_PREFERRED_TYPE(CallingConv)
-unsigned ExtInfo : 13;
+unsigned ExtInfo : 17;
/// The ref-qualifier associated with a \c FunctionProtoType.
///
@@ -4395,6 +4395,8 @@ class FunctionType : public Type {
// | CC
|noreturn|produces|nocallersavedregs|regparm|nocfcheck|cmsenscall|
// |0 .. 4| 5|6 | 7 |8 .. 10|11 |12
|
+// |RISCV-ABI-VLEN|
+// |13..17|
//
// regpa
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/100346 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/100346
This patch adds a function attribute `riscv_vls_cc` for RISCV VLS calling
convention which takes 0 or 1 argument, the argument is the `ABI_VLEN`
which is the `VLEN` for passing the fixed-vector arguments, it wraps the
argument as a scalable vector(VLA) using the `ABI_VLEN` and uses the
corresponding mechanism to handle it. The range of `ABI_VLEN` is [32, 65536],
if not specified, the default value is 128.
An option `-mriscv-abi-vlen=N` is also added to specify the `ABI_VLEN`
globally, it's used for every functions are being compiled, however if
both function attribute and option are specified, the function attribute
has higher priority than the option which means the function attribute
overwrites the `ABI_VLEN` specified by the option.
Here is an example of VLS argument passing:
Non-VLS call:
```
void original_call(__attribute__((vector_size(16))) int arg) {}
=>
define void @original_call(i128 noundef %arg) {
entry:
...
ret void
}
```
VLS call:
```
void __attribute__((riscv_vls_cc(256)))
vls_call(__attribute__((vector_size(16))) int arg) {}
=>
define riscv_vls_cc void @vls_call( %arg) {
entry:
...
ret void
}
}
```
The first Non-VLS call passes generic vector argument of 16 bytes by
flattened integer.
On the contrary, the VLS call uses `ABI_VLEN=256` which wraps the
vector to where the number of scalable vector elements
is calaulated by: `ORIG_ELTS * RVV_BITS_PER_BLOCK / ABI_VLEN`.
Note: ORIG_ELTS = Vector Size / Type Size = 128 / 32 = 4.
>From dc4d11d0e9665f42b27de4bfb73c9756b007518d Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 21 Jul 2024 09:49:11 -0700
Subject: [PATCH] [RISCV][VLS] Support RISCV VLS calling convention
This patch adds a function attribute `riscv_vls_cc` for RISCV VLS calling
convention which takes 0 or 1 argument, the argument is the `ABI_VLEN`
which is the `VLEN` for passing the fixed-vector arguments, it wraps the
argument as a scalable vector(VLA) using the `ABI_VLEN` and uses the
corresponding mechanism to handle it. The range of `ABI_VLEN` is [32, 65536],
if not specified, the default value is 128.
An option `-mriscv-abi-vlen=N` is also added to specify the `ABI_VLEN`
globally, it's used for every functions are being compiled, however if
both function attribute and option are specified, the function attribute
has higher priority than the option which means the function attribute
overwrites the `ABI_VLEN` specified by the option.
Here is an example of VLS argument passing:
Non-VLS call:
```
void original_call(__attribute__((vector_size(16))) int arg) {}
=>
define void @original_call(i128 noundef %arg) {
entry:
...
ret void
}
```
VLS call:
```
void __attribute__((riscv_vls_cc(256)))
vls_call(__attribute__((vector_size(16))) int arg) {}
=>
define riscv_vls_cc void @vls_call( %arg) {
entry:
...
ret void
}
}
```
The first Non-VLS call passes generic vector argument of 16 bytes by
flattened integer.
On the contrary, the VLS call uses `ABI_VLEN=256` which wraps the
vector to where the number of scalable vector elements
is calaulated by: `ORIG_ELTS * RVV_BITS_PER_BLOCK / ABI_VLEN`.
Note: ORIG_ELTS = Vector Size / Type Size = 128 / 32 = 4.
---
clang/include/clang-c/Index.h | 1 +
clang/include/clang/AST/Type.h| 26 +--
clang/include/clang/AST/TypeProperties.td | 7 +-
clang/include/clang/Basic/Attr.td | 8 ++
clang/include/clang/Basic/AttrDocs.td | 11 +++
clang/include/clang/Basic/Specifiers.h| 1 +
clang/include/clang/CodeGen/CGFunctionInfo.h | 9 ++-
clang/include/clang/Driver/Options.td | 2 +
clang/lib/AST/ASTContext.cpp | 2 +
clang/lib/AST/ItaniumMangle.cpp | 1 +
clang/lib/AST/Type.cpp| 2 +
clang/lib/AST/TypePrinter.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.cpp | 1 +
clang/lib/CodeGen/CGCall.cpp | 5 ++
clang/lib/CodeGen/CGDebugInfo.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 73 ---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp| 4 +
clang/lib/Sema/SemaDeclAttr.cpp | 30 +++-
clang/lib/Sema/SemaType.cpp | 17 -
.../RISCV/riscv-vector-callingconv-llvm-ir.c | 24 ++
.../riscv-vector-callingconv-llvm-ir.cpp | 14
.../CodeGen/RISCV/riscv-vector-callingconv.c | 16
.../RISCV/riscv-vector-callingconv.cpp| 17 +
clang/tools/libclang/CXType.cpp | 1 +
llvm/include/llvm/AsmParser/LLToken.h | 1 +
llvm/include/llvm/BinaryFormat/Dwarf.def | 1 +
llvm/include/llvm/IR/CallingConv.h| 3 +
llvm/lib/AsmParser/LLLexer.cpp| 1 +
llvm/lib/AsmParser/LLParser.cpp | 4 +
llvm/lib/IR/AsmWriter.cpp | 3 +
llvm/lib/Target/RISCV/RISCVFeatur
[clang] [ASTContext] Make the end of the switch case unreachable in `encodeTypeForFunctionPointerAuth` (PR #99763)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/99763 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [ASTContext] Make the end of the switch case unreachable in `encodeTypeForFunctionPointerAuth` (PR #99763)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/99763
>From 1ca71c8ed8b9f0cee9887ad81c03fd6a502f Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 20 Jul 2024 07:27:53 -0700
Subject: [PATCH] [ASTContext] Make the end of the switch case unreachable in
`encodeTypeForFunctionPointerAuth`
This prevent the warning from compiler.
---
clang/lib/AST/ASTContext.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 90bcbea072e39..b964d01805f48 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+llvm_unreachable("should never get here");
}
case Type::Record: {
const RecordDecl *RD = T->getAs()->getDecl();
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[clang] [ASTContext] Make the end of the switch case unreachable in `encodeTypeForFunctionPointerAuth` (PR #99763)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/99763 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [ASTContext] Make the end of the switch unreachable in `encodeTypeForFunctionPointerAuth` (PR #99763)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/99763 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/99763
>From f4292accb12bcd2dbe951079cf2601f867bb4f96 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 20 Jul 2024 07:27:53 -0700
Subject: [PATCH] [ASTContext] Make the end of the switch unreachable in
`encodeTypeForFunctionPointerAuth`
This prevent the warning from compiler.
---
clang/lib/AST/ASTContext.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 90bcbea072e39..b964d01805f48 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+llvm_unreachable("should never get here");
}
case Type::Record: {
const RecordDecl *RD = T->getAs()->getDecl();
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[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
4vtomat wrote:
I also agree with you that it should not reach the end of the case for
`Type::Builtin`.
https://github.com/llvm/llvm-project/pull/99763
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[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
4vtomat wrote:
Do you mean we should allow it to work if someone adds a new enum but doesn't
update the code?
That's why I added a break rather than unreachable haha~
btw, why we get an error if having `default` case on a fully covered switch?
https://github.com/llvm/llvm-project/pull/99763
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[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/99763
>From 97dff508a361bbab478735eb4bf186d698649acf Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 20 Jul 2024 07:27:53 -0700
Subject: [PATCH] [ASTContext] Add a default case to nested switch in
`encodeTypeForFunctionPointerAuth`
This prevent the warning from compiler.
---
clang/lib/AST/ASTContext.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 90bcbea072e39..87225b4702bd6 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -3285,6 +3285,8 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
case Type::Builtin: {
const auto *BTy = T->getAs();
switch (BTy->getKind()) {
+default:
+ llvm_unreachable("not yet implemented");
#define SIGNED_TYPE(Id, SingletonId)
\
case BuiltinType::Id:
\
OS << "i";
\
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[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
4vtomat wrote:
I guess it won't get into `Type::Record` if it fall through from
`Type::Builtin`, however I agree with you the intention of the code snippet.
Let me add a default case which is unreachable.
https://github.com/llvm/llvm-project/pull/99763
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[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
4vtomat wrote: > Ah, it looks like we had another set of these. I just filed #99901 after a > similar issue was reported in LLD. Thanks for filing this! https://github.com/llvm/llvm-project/pull/99763 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
4vtomat wrote:
I mean, it's not supposed to crash if the case is not presented in the original
semantic right?
https://github.com/llvm/llvm-project/pull/99763
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[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/99763 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
4vtomat wrote:
Would it break if the case is not presented if we change to
`llvm_unreachable()`?
https://github.com/llvm/llvm-project/pull/99763
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[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
4vtomat wrote: > Should we use unreachable If it's not possible to suppress the warning from > gcc? > > https://llvm.org/docs/CodingStandards.html#don-t-use-default-labels-in-fully-covered-switches-over-enumerations Maybe, but I just want to keep the original semantic here since if the case was not presented, it's supposed to fall through rather than fail. https://github.com/llvm/llvm-project/pull/99763 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [ASTContext] Add a break to nested switch in `encodeTypeForFunctionPointerAuth` (PR #99763)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/99763
This prevent the warning from compiler.
>From faf331e112ddd7ab6633f5fced55cceaef7065e0 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 20 Jul 2024 07:27:53 -0700
Subject: [PATCH] [ASTContext] Add a break to nested switch in
`encodeTypeForFunctionPointerAuth`
This prevent the warning from compiler.
---
clang/lib/AST/ASTContext.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 90bcbea072e39..9c7818e9dd80e 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -3363,6 +3363,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/RISCVVTypes.def"
llvm_unreachable("not yet implemented");
}
+break;
}
case Type::Record: {
const RecordDecl *RD = T->getAs()->getDecl();
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[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)
4vtomat wrote: > Could you give few more word on the description to mention we missed that in > the vector crpyto intrinsic proposal, and it's fixing but rather than > incompatible/breaking change for the intrinsic API? Updated description. We are missing `vcpop.v` in the rvv_intrinsic_doc, so I think we don't break anything lol~ https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
4vtomat wrote:
> FYI, the example code you shown doesn't compile anymore:
> https://godbolt.org/z/ooTWEGejf
>
> This feature is quite important, without it we can't compile in RVV by
> default in a lot of libraries, e.g. simdutf, flac, ...
I guess it should be `__attribute__((target("arch=+zve32x")))` rather then
`__attribute__((target("+zve32x")))`, sorry for misleading in the description,
let me fix it.
Btw, you can check the test case in this PR to see the correct usage.
https://github.com/llvm/llvm-project/pull/83674
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[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/91556 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/4] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
---
.../test/Preprocessor/riscv-target-features.c | 20 +--
llvm/lib/Target/RISCV/RISCVFeatures.td| 8
llvm/test/CodeGen/RISCV/attributes.ll | 16 +++
llvm/test/MC/RISCV/rv32zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv32zaamo-valid.s | 12 +--
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 12 +--
llvm/test/MC/RISCV/rv64zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv64zaamo-valid.s | 8
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 8
.../TargetParser/RISCVISAInfoTest.cpp | 4 ++--
12 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 913093bb51db6..ead9ac9b4063f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// CHECK-ZAAMO-EXT: __riscv_zaamo 2000{{$}}
+// CHECK-ZAAMO-EXT: __riscv_zaamo 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32ia_zabha1p0 -E -dM %s \
@@ -1578,13 +1578,13 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// CHECK-ZALRSC-EXT: __riscv_zalrsc 2000{{$}}
+// CHECK-ZALRSC-EXT: __riscv_zalrsc 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izfbfmin1p0 -E -dM %s \
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 89e1214f469da..b099496d18388 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -211,8 +211,8 @@ def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
"'Za128rs' (Reservation Set Size of
at Most 128 Bytes)">;
def FeatureStdExtZaamo
-: RISCVExperimentalExtension<"zaamo", 0, 2,
- "'Zaamo' (Atomic Memory Operations)">;
+: RISCVExtension<"zaamo", 1, 0,
+ "'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -242,8 +242,8 @@ def HasStdExtZalasr :
Predicate<"Subtarget->hasStdExtZalasr()">,
"'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
def FeatureStdExtZalrsc
-: RISCVExperimentalExtension<"zalrsc", 0, 2,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+: RISCVExtension<"zalrsc", 1, 0,
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 8f49f6648ad28..9fdd842e5dd37 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -112,10 +112,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-pref
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/3] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
---
.../test/Preprocessor/riscv-target-features.c | 20 +--
llvm/lib/Target/RISCV/RISCVFeatures.td| 8
llvm/test/CodeGen/RISCV/attributes.ll | 16 +++
llvm/test/MC/RISCV/rv32zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv32zaamo-valid.s | 12 +--
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 12 +--
llvm/test/MC/RISCV/rv64zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv64zaamo-valid.s | 8
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 8
.../TargetParser/RISCVISAInfoTest.cpp | 4 ++--
12 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 913093bb51db6..ead9ac9b4063f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// CHECK-ZAAMO-EXT: __riscv_zaamo 2000{{$}}
+// CHECK-ZAAMO-EXT: __riscv_zaamo 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32ia_zabha1p0 -E -dM %s \
@@ -1578,13 +1578,13 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// CHECK-ZALRSC-EXT: __riscv_zalrsc 2000{{$}}
+// CHECK-ZALRSC-EXT: __riscv_zalrsc 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izfbfmin1p0 -E -dM %s \
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 89e1214f469da..b099496d18388 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -211,8 +211,8 @@ def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
"'Za128rs' (Reservation Set Size of
at Most 128 Bytes)">;
def FeatureStdExtZaamo
-: RISCVExperimentalExtension<"zaamo", 0, 2,
- "'Zaamo' (Atomic Memory Operations)">;
+: RISCVExtension<"zaamo", 1, 0,
+ "'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -242,8 +242,8 @@ def HasStdExtZalasr :
Predicate<"Subtarget->hasStdExtZalasr()">,
"'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
def FeatureStdExtZalrsc
-: RISCVExperimentalExtension<"zalrsc", 0, 2,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+: RISCVExtension<"zalrsc", 1, 0,
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 8f49f6648ad28..9fdd842e5dd37 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -112,10 +112,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-pref
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
4vtomat wrote:
Oh, I see. Thanks for catching this!
https://github.com/llvm/llvm-project/pull/91556
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[clang] [RISCV] Remove unneeded multiply in RISCV CodeGenTypes (PR #92644)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/92644 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Remove unneeded multiply in RISCV CodeGenTypes (PR #92644)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/92644
The NumVectors other than 1 is handled by the code above.
>From 4dbcf6e577d5f1aea0cde72e3a5a7fd73620b2d9 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 18 May 2024 03:07:43 -0700
Subject: [PATCH] [RISCV] Remove unneeded multiply in RISCV CodeGenTypes
The NumVectors other than 1 is handled by the code above.
---
clang/lib/CodeGen/CodeGenTypes.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenTypes.cpp
b/clang/lib/CodeGen/CodeGenTypes.cpp
index e8d75eda029e6..0a926e4ac27fe 100644
--- a/clang/lib/CodeGen/CodeGenTypes.cpp
+++ b/clang/lib/CodeGen/CodeGenTypes.cpp
@@ -523,8 +523,7 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
return llvm::StructType::get(getLLVMContext(), EltTys);
}
return llvm::ScalableVectorType::get(ConvertType(Info.ElementType),
- Info.EC.getKnownMinValue() *
- Info.NumVectors);
+ Info.EC.getKnownMinValue());
}
#define WASM_REF_TYPE(Name, MangledName, Id, SingletonId, AS)
\
case BuiltinType::Id: {
\
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[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
4vtomat wrote: > > > Need to update RISCVUsage.rst and ReleaseNotes.rst > > > > > > Is it going to be cherry-picked to release branch? > > No. We just try to update the ReleaseNotes proactively for LLVM 19. Got it! https://github.com/llvm/llvm-project/pull/91556 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/2] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
---
.../test/Preprocessor/riscv-target-features.c | 20 +--
llvm/lib/Target/RISCV/RISCVFeatures.td| 8
llvm/test/CodeGen/RISCV/attributes.ll | 16 +++
llvm/test/MC/RISCV/rv32zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv32zaamo-valid.s | 12 +--
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 12 +--
llvm/test/MC/RISCV/rv64zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv64zaamo-valid.s | 8
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 8
.../TargetParser/RISCVISAInfoTest.cpp | 4 ++--
12 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 913093bb51db6..ead9ac9b4063f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// CHECK-ZAAMO-EXT: __riscv_zaamo 2000{{$}}
+// CHECK-ZAAMO-EXT: __riscv_zaamo 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32ia_zabha1p0 -E -dM %s \
@@ -1578,13 +1578,13 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// CHECK-ZALRSC-EXT: __riscv_zalrsc 2000{{$}}
+// CHECK-ZALRSC-EXT: __riscv_zalrsc 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izfbfmin1p0 -E -dM %s \
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 89e1214f469da..b099496d18388 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -211,8 +211,8 @@ def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
"'Za128rs' (Reservation Set Size of
at Most 128 Bytes)">;
def FeatureStdExtZaamo
-: RISCVExperimentalExtension<"zaamo", 0, 2,
- "'Zaamo' (Atomic Memory Operations)">;
+: RISCVExtension<"zaamo", 1, 0,
+ "'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -242,8 +242,8 @@ def HasStdExtZalasr :
Predicate<"Subtarget->hasStdExtZalasr()">,
"'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
def FeatureStdExtZalrsc
-: RISCVExperimentalExtension<"zalrsc", 0, 2,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+: RISCVExtension<"zalrsc", 1, 0,
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 8f49f6648ad28..9fdd842e5dd37 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -112,10 +112,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-pref
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
4vtomat wrote: > Need to update RISCVUsage.rst and ReleaseNotes.rst Is it going to be cherry-picked to release branch? https://github.com/llvm/llvm-project/pull/91556 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
