Re: [coreboot] $7 cheap FT232H board as EHCI debug dongle for coreboot - would it work?

[Georg Wicherski]

On 03/05/2018 11:36 AM, Kyösti Mälkki wrote:
> Not likely those PCBs have gone through much testing on assembly line,
> how about 4...

Have a couple of these:  and none
of them failed me thus far. Also using them successfully for Coreboot
early debugging, thanks to Kyösti's help!

-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Broadwell IGD (on Auron_Paine)

[Georg Wicherski]

On 10/19/2015 09:15 PM, Stefan Reinauer wrote:
> it seems that the refcode binary was not running. Can you verify that
> it was part of the image and gets executed?

Of course, good find.

The reference code blob was actually in the CBFS but unfortunately the
code to run it was disabled if no such blob was directly provided to
KConfig.

 now actually works on my
Auron_Paine and correctly boots with framebuffer into a payload.


There is one remaining issue, when using GRUB2 as payload and using the
at_keyboard terminal_input, the machine resets. The last debug print I
can see from GRUB2 is from term/at_keyboard.c:367 with current_set=0, so
I suppose the crasher is the write_mode(1) a few lines down.

Is this a GRUB2 issue or Coreboot issue (the at_keyboard is related to
the EC, maybe not properly initialized)?


Thanks for all involved so far!
G

-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Broadwell IGD (on Auron_Paine)

[Georg Wicherski]

On 10/23/2015 02:44 PM, Georg Wicherski wrote:
> There is one remaining issue, when using GRUB2 as payload and using the
> at_keyboard terminal_input, the machine resets. The last debug print I
> can see from GRUB2 is from term/at_keyboard.c:367 with current_set=0, so
> I suppose the crasher is the write_mode(1) a few lines down.
> 
> Is this a GRUB2 issue or Coreboot issue (the at_keyboard is related to
> the EC, maybe not properly initialized)?

I should mention, I observed exactly the same bug/behavior on a Peppy
board (which is pretty close to the Auron_Paine).

Using a USB keyboard, I can happily edit stuff in GRUB2 and boot into
Linux 4.x (which then crashes in gpio_lynxpoint, but I can simply
blacklist that module for now).

-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Broadwell IGD (on Auron_Paine)

[Georg Wicherski]

Hi,

thanks to Marc Jones' SGD patch for the Auron board
(f3214d02482a4104d7276f06d6b326b2a54c4262), I was able to get my
Auron_Paine up to ramstage.

Unfortunately, the IGD code in soc/intel/broadwell/ appears to be
somewhat broken. Based off Aaron's guidance on IRC, I've pin-pointed the
issue to be within igd_setup_panel . The first gtt_read there seems to
hang already (BIOS_SPEW log attached). Find my current code with those
debug prints at . FWIW, I've
tested with some commenting-out, etc. that it's any gtt_read that
immediately causes a hang there. Also dumped the gtt_res, small excerpt
from the log:

--8<--
igd's gtt_res = { base=e000, size=100, limit=e0ff,
flags=6201 }
igd_init: waited for pre-graphics delay to pass
igd_init: went through early init
igd_init: RP1 graphics frequency is set
gtt_read(PCH_PORT_HOTPLUG)
--8<--

People on IRC mentioned that this is an issue that people may have run
into before on Broadwell, any suggestions on how to fix the hang there?


Thanks,
G
ÀUSB


coreboot-4.1-757-g354d2c3-dirty Thu Oct 15 17:53:02 UTC 2015 romstage 
starting...
PM1_STS:   0110
PM1_EN:
PM1_CNT:   
TCO_STS:    
GPE0_STS:  1ef86df0 147dcfdf 0005f240 
GPE0_EN:      
GEN_PMCON: 0200 2024 4206
Previous Sleep State: S5
CPU: Intel(R) Celeron(R) 3205U @ 1.50GHz
CPU: ID 306d4, Broadwell E0 or F0, ucode: 001f
CPU: AES NOT supported, TXT NOT supported, VT supported
MCH: device id 1604 (rev 08) is Broadwell E0
PCH: device id 9cc5 (rev 03) is Broadwell U Base
IGD: device id 1606 (rev 08) is Broadwell U GT1
CPU: frequency set to 1500 MHz
SPD: index 5 (GPIO47=1 GPIO9=0 GPIO13=1)
CBFS @ 40 size 3ff8c0
CBFS: Locating 'spd.bin'
CBFS: Found @ offset 25d00 size 1000
SPD: module type is DDR3
SPD: module part is HMT425S6AFR6A-PB  
SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb
SPD: device width 16 bits, bus width 64 bits
SPD: module size is 2048 MB (per channel)
ME: FW Partition Table  : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode  : NO
ME: Boot Options Present: NO
ME: Update In Progress  : NO
ME: Current Working State   : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code  : No Error
ME: Progress Phase  : BUP Phase
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State: Waiting for DID BIOS message
ME: HSIO Version: 8705 (CRC 0xfbc2)
No MRC cache found.
CBFS @ 40 size 3ff8c0
CBFS: Locating 'mrc.bin'
CBFS: Found @ offset 39ffc0 size 3669c
Starting Memory Reference Code
Initializing Policy
Installing common PPI
MRC: Starting...
Initializing Memory
MRC: Done.
MRC Version 2.4.0 Build 1
memcfg DDR3 clock 1600 MHz
memcfg channel assignment: A: 0, B  1, C  2
memcfg channel[0] config (00780008):
   enhanced interleave mode on
   rank interleave on
   DIMMA 2048 MB width x16 single rank, selected
   DIMMB 0 MB width x16 single rank
memcfg channel[1] config (0060):
   enhanced interleave mode on
   rank interleave on
   DIMMA 0 MB width x8 or x32 single rank, selected
   DIMMB 0 MB width x8 or x32 single rank
CBMEM:
IMD: root @ 7bfff000 254 entries.
IMD: root @ 7bffec00 62 entries.
External stage cache:
IMD: root @ 7c3ff000 254 entries.
IMD: root @ 7c3fec00 62 entries.
MRC data at ff7d0d9c 6246 bytes
Relocate MRC DATA from ff7d0d9c to 7bf7b000 (6246 bytes)
create cbmem for dimm information
TPM initialization.
TPM: Init
Found TPM SLB9635 TT 1.2 by Infineon
TPM: Open
TPM: Startup
TPM: command 0x99 returned 0x0
TPM: OK.
CBFS provider active.
CBFS @ 40 size 3ff8c0
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 3b200 size 1364a
'fallback/ramstage' located at offset: 43b238 size: 1364a
Decompressing stage fallback/ramstage @ 0x7bf3afc0 (241232 bytes)
Loading module at 7bf3b000 with entry 7bf3b000. filesize: 0x29e98 memsize: 
0x3ae10
Processing 2712 relocs. Offset value of 0x7be3b000
USB


coreboot-4.1-757-g354d2c3-dirty Thu Oct 15 17:53:02 UTC 2015 ramstage 
starting...
Moving GDT to 7bf39000...ok
Normal boot.
BS: BS_PRE_DEVICE times (us): entry 5 run 5 exit 4
BS: BS_DEV_INIT_CHIPS times (us): entry 5 run 8 exit 5
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: : enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:13.0: enabled 0
PCI: 00:14.0: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 0
PCI: 00:15.4: enabled 0
PCI: 00:15.5: enabled 0
PCI: 00:15.6: enabled 0
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:17.0: enabled 0
PCI: 00:19.0: enabled 0
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 0
PCI: 00:1c.2: enabled 0
PCI: 00:1c.3: enabled 0