Re: [edk2-devel] [edk2-platforms: PATCH v2 09/10] Marvell/Cn9132Db: Introduce board support
On Thu, Aug 15, 2019 at 04:54:13AM +0200, Marcin Wojtas wrote: > This patch introduces all necessary components required > for building EDK2 firmware for CN9132-DB setup A. Note > the ACPI is not yet available for this variant, due to > the current ICU (CP1xx interrupt controller) support > implementation. > > In order to build this variant, '-D CN9132' flag should be added. > Otherwise the default (CN9130) will be compiled. Same comment on commit message - don't forget to update if logic changed. > Signed-off-by: Marcin Wojtas > --- > Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | > 72 +++ > Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | > 15 ++- > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf | > 29 + > Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf | > 22 > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | > 4 + > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | > 135 > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | > 42 ++ > Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc | > 2 + > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | > 6 - > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi| > 20 ++- > 10 files changed, 333 insertions(+), 14 deletions(-) > create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc > create mode 100644 > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf > create mode 100644 > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c > > diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc > b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc > new file mode 100644 > index 000..a0b90fa > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc > @@ -0,0 +1,72 @@ > +## @file > +# Component description file for the CN9132 Development Board (variant A) > +# > +# Copyright (c) 2019 Marvell International Ltd. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > + > +# > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform > +# > + > +[PcdsFixedAtBuild.common] > + # CP115 count > + gMarvellTokenSpaceGuid.PcdMaxCpCount|3 > + > + # MPP > + gMarvellTokenSpaceGuid.PcdMppChipCount|4 > + > + # CP115 #2 MPP > + gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE > + gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF644 > + gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64 > + gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, > 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, > 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, > 0x0, 0x9, 0x9, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, > 0x0, 0x2, 0x2, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, > 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, > 0xE, 0xE, 0xE, 0xE } > + gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, > 0x0, 0x0, 0x0, 0x0 } > + > + # ComPhy > + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } > + # ComPhy1 > + # 0: PCIE0 5 Gbps > + # 1: PCIE0 5 Gbps > + # 2: SATA0 5 Gbps > + # 3: USB3_HOST15 Gbps > + # 4: SFI 10.31 Gbps > + # 5: PCIE2 5 Gbps > + gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), > $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)} > + gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), > $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } > + > + # UtmiPhy > + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, > 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), > $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), > $(UTMI_USB_HOST1) } > + > + # MDIO > + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } > + > + # PHY > + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } > + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE > + > + # NET > + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{
[edk2-devel] [edk2-platforms: PATCH v2 09/10] Marvell/Cn9132Db: Introduce board support
This patch introduces all necessary components required for building EDK2 firmware for CN9132-DB setup A. Note the ACPI is not yet available for this variant, due to the current ICU (CP1xx interrupt controller) support implementation. In order to build this variant, '-D CN9132' flag should be added. Otherwise the default (CN9130) will be compiled. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 72 +++ Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 15 ++- Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf | 29 + Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf | 22 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 4 + Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | 135 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 42 ++ Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc | 2 + Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 6 - Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi| 20 ++- 10 files changed, 333 insertions(+), 14 deletions(-) create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc new file mode 100644 index 000..a0b90fa --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc @@ -0,0 +1,72 @@ +## @file +# Component description file for the CN9132 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# + +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|3 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|4 + + # CP115 #2 MPP + gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF644 + gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x9, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0x0, 0x2, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } + # ComPhy1 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: SATA0 5 Gbps + # 3: USB3_HOST15 Gbps + # 4: SFI 10.31 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)} + gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_1), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_1), $(PHY_SPEED_1) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 } +