Re: [edk2] [PATCH edk2-platforms v1 05/16] Hisilicon/D06: Add more PCIe port INT-x support
On 2/12/2019 1:05 AM, Leif Lindholm wrote: > On Fri, Feb 01, 2019 at 09:34:25PM +0800, Ming Huang wrote: >> From: Jason Zhang >> >> Since NVMe riser width is 6*X4, need add the related >> port's INT-x support to match OS driver. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ming Huang >> --- >> Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 65 >> +++- >> 1 file changed, 50 insertions(+), 15 deletions(-) >> >> diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl >> b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl >> index 27fde2e09bfe..4d9d9d95be68 100644 >> --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl >> +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl >> @@ -41,11 +41,21 @@ Scope(_SB) >>// adding RPx INTx configure deponds on hardware board topology, >>// if UEFI enables RPx, RPy, RPz... related INTx configure >>// should be added >> + Package () {0x2,0,0,640}, // INT_A >> + Package () {0x2,1,0,641}, // INT_B >> + Package () {0x2,2,0,642}, // INT_C >> + Package () {0x2,3,0,643}, // INT_D >> + >>Package () {0x4,0,0,640}, // INT_A >>Package () {0x4,1,0,641}, // INT_B >>Package () {0x4,2,0,642}, // INT_C >>Package () {0x4,3,0,643}, // INT_D >> >> + Package () {0x6,0,0,640}, // INT_A >> + Package () {0x6,1,0,641}, // INT_B >> + Package () {0x6,2,0,642}, // INT_C >> + Package () {0x6,3,0,643}, // INT_D >> + >>Package () {0x8,0,0,640}, // INT_A >>Package () {0x8,1,0,641}, // INT_B >>Package () {0x8,2,0,642}, // INT_C >> @@ -56,6 +66,11 @@ Scope(_SB) >>Package () {0xC,2,0,642}, // INT_C >>Package () {0xC,3,0,643}, // INT_D >> >> + Package () {0xE,0,0,640}, // INT_A >> + Package () {0xE,1,0,641}, // INT_B >> + Package () {0xE,2,0,642}, // INT_C >> + Package () {0xE,3,0,643}, // INT_D >> + >>Package () {0x10,0,0,640}, // INT_A >>Package () {0x10,1,0,641}, // INT_B >>Package () {0x10,2,0,642}, // INT_C >> @@ -759,26 +774,46 @@ Device (PCI6) >> // adding RPx INTx configure deponds on hardware board topology, >> // if UEFI enables RPx, RPy, RPz... related INTx configure >> // should be added >> -Package () {0x04,0,0,640}, // INT_A >> -Package () {0x04,1,0,641}, // INT_B >> -Package () {0x04,2,0,642}, // INT_C >> -Package () {0x04,3,0,643}, // INT_D >> - >> -Package () {0x08,0,0,640}, // INT_A >> -Package () {0x08,1,0,641}, // INT_B >> -Package () {0x08,2,0,642}, // INT_C >> -Package () {0x08,3,0,643}, // INT_D >> - >> -Package () {0x0C,0,0,640}, // INT_A >> -Package () {0x0C,1,0,641}, // INT_B >> -Package () {0x0C,2,0,642}, // INT_C >> -Package () {0x0C,3,0,643}, // INT_D > > Please don't include the non-functional change of dropping the leading > 0 (0x0 -> 0x) here together with the functional change of adding new > entries. Please submit as a separate patch. Ok, do it in v2. > > / > Leif > >> +Package () {0x2,0,0,640}, // INT_A >> +Package () {0x2,1,0,641}, // INT_B >> +Package () {0x2,2,0,642}, // INT_C >> +Package () {0x2,3,0,643}, // INT_D >> + >> +Package () {0x4,0,0,640}, // INT_A >> +Package () {0x4,1,0,641}, // INT_B >> +Package () {0x4,2,0,642}, // INT_C >> +Package () {0x4,3,0,643}, // INT_D >> + >> +Package () {0x6,0,0,640}, // INT_A >> +Package () {0x6,1,0,641}, // INT_B >> +Package () {0x6,2,0,642}, // INT_C >> +Package () {0x6,3,0,643}, // INT_D >> + >> +Package () {0x8,0,0,640}, // INT_A >> +Package () {0x8,1,0,641}, // INT_B >> +Package () {0x8,2,0,642}, // INT_C >> +Package () {0x8,3,0,643}, // INT_D >> + >> +Package () {0xC,0,0,640}, // INT_A >> +Package () {0xC,1,0,641}, // INT_B >> +Package () {0xC,2,0,642}, // INT_C >> +Package () {0xC,3,0,643}, // INT_D >> + >> +Package () {0xE,0,0,640}, // INT_A >> +Package () {0xE,1,0,641}, // INT_B >> +Package () {0xE,2,0,642}, // INT_C >> +Package () {0xE,3,0,643}, // INT_D >> >> Package () {0x10,0,0,640}, // INT_A >> Package () {0x10F
Re: [edk2] [PATCH edk2-platforms v1 05/16] Hisilicon/D06: Add more PCIe port INT-x support
On Fri, Feb 01, 2019 at 09:34:25PM +0800, Ming Huang wrote: > From: Jason Zhang > > Since NVMe riser width is 6*X4, need add the related > port's INT-x support to match OS driver. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang > --- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 65 > +++- > 1 file changed, 50 insertions(+), 15 deletions(-) > > diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > index 27fde2e09bfe..4d9d9d95be68 100644 > --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > @@ -41,11 +41,21 @@ Scope(_SB) >// adding RPx INTx configure deponds on hardware board topology, >// if UEFI enables RPx, RPy, RPz... related INTx configure >// should be added > + Package () {0x2,0,0,640}, // INT_A > + Package () {0x2,1,0,641}, // INT_B > + Package () {0x2,2,0,642}, // INT_C > + Package () {0x2,3,0,643}, // INT_D > + >Package () {0x4,0,0,640}, // INT_A >Package () {0x4,1,0,641}, // INT_B >Package () {0x4,2,0,642}, // INT_C >Package () {0x4,3,0,643}, // INT_D > > + Package () {0x6,0,0,640}, // INT_A > + Package () {0x6,1,0,641}, // INT_B > + Package () {0x6,2,0,642}, // INT_C > + Package () {0x6,3,0,643}, // INT_D > + >Package () {0x8,0,0,640}, // INT_A >Package () {0x8,1,0,641}, // INT_B >Package () {0x8,2,0,642}, // INT_C > @@ -56,6 +66,11 @@ Scope(_SB) >Package () {0xC,2,0,642}, // INT_C >Package () {0xC,3,0,643}, // INT_D > > + Package () {0xE,0,0,640}, // INT_A > + Package () {0xE,1,0,641}, // INT_B > + Package () {0xE,2,0,642}, // INT_C > + Package () {0xE,3,0,643}, // INT_D > + >Package () {0x10,0,0,640}, // INT_A >Package () {0x10,1,0,641}, // INT_B >Package () {0x10,2,0,642}, // INT_C > @@ -759,26 +774,46 @@ Device (PCI6) > // adding RPx INTx configure deponds on hardware board topology, > // if UEFI enables RPx, RPy, RPz... related INTx configure > // should be added > -Package () {0x04,0,0,640}, // INT_A > -Package () {0x04,1,0,641}, // INT_B > -Package () {0x04,2,0,642}, // INT_C > -Package () {0x04,3,0,643}, // INT_D > - > -Package () {0x08,0,0,640}, // INT_A > -Package () {0x08,1,0,641}, // INT_B > -Package () {0x08,2,0,642}, // INT_C > -Package () {0x08,3,0,643}, // INT_D > - > -Package () {0x0C,0,0,640}, // INT_A > -Package () {0x0C,1,0,641}, // INT_B > -Package () {0x0C,2,0,642}, // INT_C > -Package () {0x0C,3,0,643}, // INT_D Please don't include the non-functional change of dropping the leading 0 (0x0 -> 0x) here together with the functional change of adding new entries. Please submit as a separate patch. / Leif > +Package () {0x2,0,0,640}, // INT_A > +Package () {0x2,1,0,641}, // INT_B > +Package () {0x2,2,0,642}, // INT_C > +Package () {0x2,3,0,643}, // INT_D > + > +Package () {0x4,0,0,640}, // INT_A > +Package () {0x4,1,0,641}, // INT_B > +Package () {0x4,2,0,642}, // INT_C > +Package () {0x4,3,0,643}, // INT_D > + > +Package () {0x6,0,0,640}, // INT_A > +Package () {0x6,1,0,641}, // INT_B > +Package () {0x6,2,0,642}, // INT_C > +Package () {0x6,3,0,643}, // INT_D > + > +Package () {0x8,0,0,640}, // INT_A > +Package () {0x8,1,0,641}, // INT_B > +Package () {0x8,2,0,642}, // INT_C > +Package () {0x8,3,0,643}, // INT_D > + > +Package () {0xC,0,0,640}, // INT_A > +Package () {0xC,1,0,641}, // INT_B > +Package () {0xC,2,0,642}, // INT_C > +Package () {0xC,3,0,643}, // INT_D > + > +Package () {0xE,0,0,640}, // INT_A > +Package () {0xE,1,0,641}, // INT_B > +Package () {0xE,2,0,642}, // INT_C > +Package () {0xE,3,0,643}, // INT_D > > Package () {0x10,0,0,640}, // INT_A > Package () {0x10,1,0,641}, // INT_B > Package () {0x10,2,0,642}, // INT_C > Package () {0x10,3,0,643}, // INT_D > - }) > + > +Package () {0x12,
[edk2] [PATCH edk2-platforms v1 05/16] Hisilicon/D06: Add more PCIe port INT-x support
From: Jason Zhang Since NVMe riser width is 6*X4, need add the related port's INT-x support to match OS driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 65 +++- 1 file changed, 50 insertions(+), 15 deletions(-) diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 27fde2e09bfe..4d9d9d95be68 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -41,11 +41,21 @@ Scope(_SB) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added + Package () {0x2,0,0,640}, // INT_A + Package () {0x2,1,0,641}, // INT_B + Package () {0x2,2,0,642}, // INT_C + Package () {0x2,3,0,643}, // INT_D + Package () {0x4,0,0,640}, // INT_A Package () {0x4,1,0,641}, // INT_B Package () {0x4,2,0,642}, // INT_C Package () {0x4,3,0,643}, // INT_D + Package () {0x6,0,0,640}, // INT_A + Package () {0x6,1,0,641}, // INT_B + Package () {0x6,2,0,642}, // INT_C + Package () {0x6,3,0,643}, // INT_D + Package () {0x8,0,0,640}, // INT_A Package () {0x8,1,0,641}, // INT_B Package () {0x8,2,0,642}, // INT_C @@ -56,6 +66,11 @@ Scope(_SB) Package () {0xC,2,0,642}, // INT_C Package () {0xC,3,0,643}, // INT_D + Package () {0xE,0,0,640}, // INT_A + Package () {0xE,1,0,641}, // INT_B + Package () {0xE,2,0,642}, // INT_C + Package () {0xE,3,0,643}, // INT_D + Package () {0x10,0,0,640}, // INT_A Package () {0x10,1,0,641}, // INT_B Package () {0x10,2,0,642}, // INT_C @@ -759,26 +774,46 @@ Device (PCI6) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added -Package () {0x04,0,0,640}, // INT_A -Package () {0x04,1,0,641}, // INT_B -Package () {0x04,2,0,642}, // INT_C -Package () {0x04,3,0,643}, // INT_D - -Package () {0x08,0,0,640}, // INT_A -Package () {0x08,1,0,641}, // INT_B -Package () {0x08,2,0,642}, // INT_C -Package () {0x08,3,0,643}, // INT_D - -Package () {0x0C,0,0,640}, // INT_A -Package () {0x0C,1,0,641}, // INT_B -Package () {0x0C,2,0,642}, // INT_C -Package () {0x0C,3,0,643}, // INT_D +Package () {0x2,0,0,640}, // INT_A +Package () {0x2,1,0,641}, // INT_B +Package () {0x2,2,0,642}, // INT_C +Package () {0x2,3,0,643}, // INT_D + +Package () {0x4,0,0,640}, // INT_A +Package () {0x4,1,0,641}, // INT_B +Package () {0x4,2,0,642}, // INT_C +Package () {0x4,3,0,643}, // INT_D + +Package () {0x6,0,0,640}, // INT_A +Package () {0x6,1,0,641}, // INT_B +Package () {0x6,2,0,642}, // INT_C +Package () {0x6,3,0,643}, // INT_D + +Package () {0x8,0,0,640}, // INT_A +Package () {0x8,1,0,641}, // INT_B +Package () {0x8,2,0,642}, // INT_C +Package () {0x8,3,0,643}, // INT_D + +Package () {0xC,0,0,640}, // INT_A +Package () {0xC,1,0,641}, // INT_B +Package () {0xC,2,0,642}, // INT_C +Package () {0xC,3,0,643}, // INT_D + +Package () {0xE,0,0,640}, // INT_A +Package () {0xE,1,0,641}, // INT_B +Package () {0xE,2,0,642}, // INT_C +Package () {0xE,3,0,643}, // INT_D Package () {0x10,0,0,640}, // INT_A Package () {0x10,1,0,641}, // INT_B Package () {0x10,2,0,642}, // INT_C Package () {0x10,3,0,643}, // INT_D - }) + +Package () {0x12,0,0,640}, // INT_A +Package () {0x12,1,0,641}, // INT_B +Package () {0x12,2,0,642}, // INT_C +Package () {0x12,3,0,643}, // INT_D +}) Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, -- 2.9.5 ___ edk2-devel mailing li