Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
> It would be nice to add to the documentation that INSN_BASE_REG_CLASS, > INSN_INDEX_REG_CLASS, and REGNO_OK_FOR_INSN_BASE_P if defined have > priority over older corresponding macros as it is already documented for > REGNO_MODE_CODE_OK_FOR_BASE_P relating to REGNO_OK_FOR_BASE_P. But this > small issue can be addressed later. > Thanks, I would add the description like below when committing. +@defmac INSN_BASE_REG_CLASS (@var{insn}) +A C expression whose value is the register class to which a valid +base register for a specified @var{insn} must belong. This macro is +used when some backend insns may have limited usage of base register +compared with other insns. If you define this macro, the compiler will +use it instead of all other defined macros that relate to +BASE_REG_CLASS. +@end defmac + +@defmac REGNO_OK_FOR_INSN_BASE_P (@var{num}, @var{insn}) +A C expression which is nonzero if register number @var{num} is +suitable for use as a base register in operand addresses for a specified +@var{insn}. This macro is used when some backend insn may have limited +usage of base register compared with other insns. If you define this +macro, the compiler will use it instead of all other defined macros +that relate to REGNO_OK_FOR_BASE_P. +@end defmac + +@defmac INSN_INDEX_REG_CLASS (@var{insn}) +A C expression whose value is the register class to which a valid +index register for a specified @var{insn} must belong. This macro is +used when some backend insns may have limited usage of index register +compared with other insns. If you defined this macro, the compiler +will use it instead of @code{INDEX_REG_CLASS}. +@end defmac +
Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
On 9/22/23 06:56, Hongyu Wang wrote: From: Kong Lingling Current reload infrastructure does not support selective base_reg_class for backend insn. Add new macros with insn parameters to base_reg_class for lra/reload usage. gcc/ChangeLog: * addresses.h (base_reg_class): Add insn argument and new macro INSN_BASE_REG_CLASS. (regno_ok_for_base_p_1): Add insn argument and new macro REGNO_OK_FOR_INSN_BASE_P. (regno_ok_for_base_p): Add insn argument and parse to ok_for_base_p_1. * doc/tm.texi: Document INSN_BASE_REG_CLASS and REGNO_OK_FOR_INSN_BASE_P. * doc/tm.texi.in: Ditto. * lra-constraints.cc (process_address_1): Pass insn to base_reg_class. (curr_insn_transform): Ditto. * reload.cc (find_reloads): Ditto. (find_reloads_address): Ditto. (find_reloads_address_1): Ditto. (find_reloads_subreg_address): Ditto. * reload1.cc (maybe_fix_stack_asms): Ditto. The patch is ok for committing to the trunk. Thank you. It would be nice to add to the documentation that INSN_BASE_REG_CLASS, INSN_INDEX_REG_CLASS, and REGNO_OK_FOR_INSN_BASE_P if defined have priority over older corresponding macros as it is already documented for REGNO_MODE_CODE_OK_FOR_BASE_P relating to REGNO_OK_FOR_BASE_P. But this small issue can be addressed later.
[PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
From: Kong Lingling Current reload infrastructure does not support selective base_reg_class for backend insn. Add new macros with insn parameters to base_reg_class for lra/reload usage. gcc/ChangeLog: * addresses.h (base_reg_class): Add insn argument and new macro INSN_BASE_REG_CLASS. (regno_ok_for_base_p_1): Add insn argument and new macro REGNO_OK_FOR_INSN_BASE_P. (regno_ok_for_base_p): Add insn argument and parse to ok_for_base_p_1. * doc/tm.texi: Document INSN_BASE_REG_CLASS and REGNO_OK_FOR_INSN_BASE_P. * doc/tm.texi.in: Ditto. * lra-constraints.cc (process_address_1): Pass insn to base_reg_class. (curr_insn_transform): Ditto. * reload.cc (find_reloads): Ditto. (find_reloads_address): Ditto. (find_reloads_address_1): Ditto. (find_reloads_subreg_address): Ditto. * reload1.cc (maybe_fix_stack_asms): Ditto. Co-authored-by: Hongyu Wang Co-authored-by: Hongtao Liu --- gcc/addresses.h| 19 +++ gcc/doc/tm.texi| 14 ++ gcc/doc/tm.texi.in | 14 ++ gcc/lra-constraints.cc | 15 +-- gcc/reload.cc | 30 ++ gcc/reload1.cc | 2 +- 6 files changed, 71 insertions(+), 23 deletions(-) diff --git a/gcc/addresses.h b/gcc/addresses.h index 3519c241c6d..2c92927bd51 100644 --- a/gcc/addresses.h +++ b/gcc/addresses.h @@ -28,8 +28,12 @@ inline enum reg_class base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, addr_space_t as ATTRIBUTE_UNUSED, enum rtx_code outer_code ATTRIBUTE_UNUSED, - enum rtx_code index_code ATTRIBUTE_UNUSED) + enum rtx_code index_code ATTRIBUTE_UNUSED, + rtx_insn *insn ATTRIBUTE_UNUSED = NULL) { +#ifdef INSN_BASE_REG_CLASS + return INSN_BASE_REG_CLASS (insn); +#else #ifdef MODE_CODE_BASE_REG_CLASS return MODE_CODE_BASE_REG_CLASS (MACRO_MODE (mode), as, outer_code, index_code); @@ -44,6 +48,7 @@ base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, return BASE_REG_CLASS; #endif #endif +#endif } /* Wrapper function to unify target macros REGNO_MODE_CODE_OK_FOR_BASE_P, @@ -56,8 +61,12 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED, addr_space_t as ATTRIBUTE_UNUSED, enum rtx_code outer_code ATTRIBUTE_UNUSED, -enum rtx_code index_code ATTRIBUTE_UNUSED) +enum rtx_code index_code ATTRIBUTE_UNUSED, +rtx_insn* insn ATTRIBUTE_UNUSED = NULL) { +#ifdef REGNO_OK_FOR_INSN_BASE_P + return REGNO_OK_FOR_INSN_BASE_P (regno, insn); +#else #ifdef REGNO_MODE_CODE_OK_FOR_BASE_P return REGNO_MODE_CODE_OK_FOR_BASE_P (regno, MACRO_MODE (mode), as, outer_code, index_code); @@ -72,6 +81,7 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, return REGNO_OK_FOR_BASE_P (regno); #endif #endif +#endif } /* Wrapper around ok_for_base_p_1, for use after register allocation is @@ -79,12 +89,13 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, inline bool regno_ok_for_base_p (unsigned regno, machine_mode mode, addr_space_t as, -enum rtx_code outer_code, enum rtx_code index_code) +enum rtx_code outer_code, enum rtx_code index_code, +rtx_insn *insn = NULL) { if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0) regno = reg_renumber[regno]; - return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); + return ok_for_base_p_1 (regno, mode, as, outer_code, index_code, insn); } #endif /* GCC_ADDRESSES_H */ diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index b0779724d30..5b1e2a11f89 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -2568,6 +2568,13 @@ of an address, @code{ADDRESS} for something that occurs in an index expression if @var{outer_code} is @code{PLUS}; @code{SCRATCH} otherwise. @end defmac +@defmac INSN_BASE_REG_CLASS (@var{insn}) +A C expression whose value is the register class to which a valid +base register for a specified @var{insn} must belong. This macro is +used when some backend insns may have limited usage of base register +compared with other insns. +@end defmac + @defmac INDEX_REG_CLASS A macro whose definition is the name of the class to which a valid index register must belong. An index register is one used in an @@ -2618,6 +2625,13 @@ corresponding index expression if @var{outer_code} is @code{PLUS}; that appear outside a @code{MEM}, i.e., as an @code{address_operand}. @end defmac +@defmac REGNO_OK_FOR_INSN_BASE_P (@var{num}, @var{insn}) +A C expression which is nonzero if register number @var{num} is +suitable for use as a base register in operand addresses for a specified +@var{insn}. This macro is used when some backend insn may have limi
Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
On 9/10/23 00:49, Hongyu Wang wrote: Vladimir Makarov via Gcc-patches 于2023年9月9日周六 01:04写道: On 8/31/23 04:20, Hongyu Wang wrote: @@ -2542,6 +2542,8 @@ the code of the immediately enclosing expression (@code{MEM} for the top level of an address, @code{ADDRESS} for something that occurs in an @code{address_operand}). @var{index_code} is the code of the corresponding index expression if @var{outer_code} is @code{PLUS}; @code{SCRATCH} otherwise. +@code{insn} indicates insn specific base register class should be subset +of the original base register class. @end defmac I'd prefer more general description of 'insn' argument for the macros. Something like that: @code{insn} can be used to define an insn-specific base register class. Sure, will adjust in the V2 patch. Also, currently we reuse the old macro MODE_CODE_BASE_REG_CLASS, do you think we need a new macro like INSN_BASE_REG_CLASS as other parameters are actually unused? Then we don't need to change other targets like avr/gcn. I thought about this too. Using new macros would be definitely worth to add, especially when you are already adding INSN_INDEX_REG_CLASS. The names INSN_BASE_REG_CLASS instead of MODE_CODE_BASE_REG_CLASS and REGNO_OK_FOR_INSN_BASE_P instead of REGNO_MODE_CODE_OK_FOR_BASE_P are ok for me too. When you submit the v2 patch, I'll review the RA part as soon as possible (actually I already looked at this) and most probably give my approval for the RA part because I prefer you current approach for RA instead of introducing new memory constraints.
Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
Vladimir Makarov via Gcc-patches 于2023年9月9日周六 01:04写道: > > > On 8/31/23 04:20, Hongyu Wang wrote: > > @@ -2542,6 +2542,8 @@ the code of the immediately enclosing expression > > (@code{MEM} for the top level > > of an address, @code{ADDRESS} for something that occurs in an > > @code{address_operand}). @var{index_code} is the code of the > > corresponding > > index expression if @var{outer_code} is @code{PLUS}; @code{SCRATCH} > > otherwise. > > +@code{insn} indicates insn specific base register class should be subset > > +of the original base register class. > > @end defmac > > I'd prefer more general description of 'insn' argument for the macros. > Something like that: > > @code{insn} can be used to define an insn-specific base register class. > Sure, will adjust in the V2 patch. Also, currently we reuse the old macro MODE_CODE_BASE_REG_CLASS, do you think we need a new macro like INSN_BASE_REG_CLASS as other parameters are actually unused? Then we don't need to change other targets like avr/gcn.
Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
On 8/31/23 04:20, Hongyu Wang wrote: @@ -2542,6 +2542,8 @@ the code of the immediately enclosing expression (@code{MEM} for the top level of an address, @code{ADDRESS} for something that occurs in an @code{address_operand}). @var{index_code} is the code of the corresponding index expression if @var{outer_code} is @code{PLUS}; @code{SCRATCH} otherwise. +@code{insn} indicates insn specific base register class should be subset +of the original base register class. @end defmac I'd prefer more general description of 'insn' argument for the macros. Something like that: @code{insn} can be used to define an insn-specific base register class.
Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
On 9/7/23 02:23, Uros Bizjak wrote: On Wed, Sep 6, 2023 at 9:43 PM Vladimir Makarov wrote: On 9/1/23 05:07, Hongyu Wang wrote: I think the approach proposed by Intel developers is better. In some way we already use such approach when we pass memory mode to get the base reg class. Although we could use different memory constraints for different modes when the possible base reg differs for some memory modes. Using special memory constraints probably can be implemented too (I understand attractiveness of such approach for readability of the machine description). But in my opinion it will require much bigger work in IRA/LRA/reload. It also significantly slow down RA as we need to process insn constraints for processing each memory in many places (e.g. for calculation of reg classes and costs in IRA). Still I think there will be a few cases for this approach resulting in a bigger probability of assigning hard reg out of specific base reg class and this will result in additional reloads. So the approach proposed by Intel is ok for me. Although if x86 maintainers are strongly against this approach and the changes in x86 machine dependent code and Intel developers implement Uros approach, I am ready to review this. But still I prefer the current Intel developers approach for reasons I mentioned above. My above proposal is more or less a wish from a target maintainer PoV. Ideally, we would have a bunch of different memory constraints, and a target hook that returns corresponding BASE/INDEX reg classes. However, I have no idea about the complexity of the implementation in the infrastructure part of the compiler. Basically, it needs introducing new hooks which return base and index classes from special memory constraints. When we process memory in an insn (a lot of places in IRA, LRA,reload) we should consider all possible memory insn constraints, take intersection of basic and index reg classes for the constraints and use them instead of the default base and reg classes. The required functionality is absent in reload too. I would say that it is a moderate size project (1-2 months for me). It still requires to introduce new hooks and I guess there are few cases when we will still assign hard regs out of desirable base class for address pseudos and this will results in generation of additional reload insns. It also means much more additional changes in RA source code and x86 machine dependent files. Probably, with this approach there will be also edge cases when we need to solve new PRs because of LRA failures to generate the correct code but I believe they can be solved. Therefore I lean toward the current Intel approach when to get base reg class we pass the insn as a parameter additionally to memory mode.
Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
On Wed, Sep 6, 2023 at 9:43 PM Vladimir Makarov wrote: > > > On 9/1/23 05:07, Hongyu Wang wrote: > > Uros Bizjak via Gcc-patches 于2023年8月31日周四 18:16写道: > >> On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote: > >>> From: Kong Lingling > >>> > >>> Current reload infrastructure does not support selective base_reg_class > >>> for backend insn. Add insn argument to base_reg_class for > >>> lra/reload usage. > >> I don't think this is the correct approach. Ideally, a memory > >> constraint should somehow encode its BASE/INDEX register class. > >> Instead of passing "insn", simply a different constraint could be used > >> in the constraint string of the relevant insn. > > We tried constraint only at the beginning, but then we found the > > reload infrastructure > > does not work like that. > > > > The BASE/INDEX reg classes are determined before choosing alternatives, in > > process_address under curr_insn_transform. Process_address creates the mem > > operand according to the BASE/INDEX reg class. Then, the memory operand > > constraint check will evaluate the mem op with targetm.legitimate_address_p. > > > > If we want to make use of EGPR in base/index we need to either extend > > BASE/INDEX > > reg class in the backend, or, for specific insns, add a target hook to > > tell reload > > that the extended reg class with EGPR can be used to construct memory > > operand. > > > > CC'd Vladimir as git send-mail failed to add recipient. > > > > > I think the approach proposed by Intel developers is better. In some way > we already use such approach when we pass memory mode to get the base > reg class. Although we could use different memory constraints for > different modes when the possible base reg differs for some memory > modes. > > Using special memory constraints probably can be implemented too (I > understand attractiveness of such approach for readability of the > machine description). But in my opinion it will require much bigger > work in IRA/LRA/reload. It also significantly slow down RA as we need > to process insn constraints for processing each memory in many places > (e.g. for calculation of reg classes and costs in IRA). Still I think > there will be a few cases for this approach resulting in a bigger > probability of assigning hard reg out of specific base reg class and > this will result in additional reloads. > > So the approach proposed by Intel is ok for me. Although if x86 maintainers > are strongly against this approach and the changes in x86 machine > dependent code and Intel developers implement Uros approach, I am > ready to review this. But still I prefer the current Intel developers > approach for reasons I mentioned above. My above proposal is more or less a wish from a target maintainer PoV. Ideally, we would have a bunch of different memory constraints, and a target hook that returns corresponding BASE/INDEX reg classes. However, I have no idea about the complexity of the implementation in the infrastructure part of the compiler. Uros.
Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
On 9/1/23 05:07, Hongyu Wang wrote: Uros Bizjak via Gcc-patches 于2023年8月31日周四 18:16写道: On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote: From: Kong Lingling Current reload infrastructure does not support selective base_reg_class for backend insn. Add insn argument to base_reg_class for lra/reload usage. I don't think this is the correct approach. Ideally, a memory constraint should somehow encode its BASE/INDEX register class. Instead of passing "insn", simply a different constraint could be used in the constraint string of the relevant insn. We tried constraint only at the beginning, but then we found the reload infrastructure does not work like that. The BASE/INDEX reg classes are determined before choosing alternatives, in process_address under curr_insn_transform. Process_address creates the mem operand according to the BASE/INDEX reg class. Then, the memory operand constraint check will evaluate the mem op with targetm.legitimate_address_p. If we want to make use of EGPR in base/index we need to either extend BASE/INDEX reg class in the backend, or, for specific insns, add a target hook to tell reload that the extended reg class with EGPR can be used to construct memory operand. CC'd Vladimir as git send-mail failed to add recipient. I think the approach proposed by Intel developers is better. In some way we already use such approach when we pass memory mode to get the base reg class. Although we could use different memory constraints for different modes when the possible base reg differs for some memory modes. Using special memory constraints probably can be implemented too (I understand attractiveness of such approach for readability of the machine description). But in my opinion it will require much bigger work in IRA/LRA/reload. It also significantly slow down RA as we need to process insn constraints for processing each memory in many places (e.g. for calculation of reg classes and costs in IRA). Still I think there will be a few cases for this approach resulting in a bigger probability of assigning hard reg out of specific base reg class and this will result in additional reloads. So the approach proposed by Intel is ok for me. Although if x86 maintainers are strongly against this approach and the changes in x86 machine dependent code and Intel developers implement Uros approach, I am ready to review this. But still I prefer the current Intel developers approach for reasons I mentioned above.
Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
Uros Bizjak via Gcc-patches 于2023年8月31日周四 18:16写道: > > On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote: > > > > From: Kong Lingling > > > > Current reload infrastructure does not support selective base_reg_class > > for backend insn. Add insn argument to base_reg_class for > > lra/reload usage. > > I don't think this is the correct approach. Ideally, a memory > constraint should somehow encode its BASE/INDEX register class. > Instead of passing "insn", simply a different constraint could be used > in the constraint string of the relevant insn. We tried constraint only at the beginning, but then we found the reload infrastructure does not work like that. The BASE/INDEX reg classes are determined before choosing alternatives, in process_address under curr_insn_transform. Process_address creates the mem operand according to the BASE/INDEX reg class. Then, the memory operand constraint check will evaluate the mem op with targetm.legitimate_address_p. If we want to make use of EGPR in base/index we need to either extend BASE/INDEX reg class in the backend, or, for specific insns, add a target hook to tell reload that the extended reg class with EGPR can be used to construct memory operand. CC'd Vladimir as git send-mail failed to add recipient. > > Uros. > > > > gcc/ChangeLog: > > > > * addresses.h (base_reg_class): Add insn argument. > > Pass to MODE_CODE_BASE_REG_CLASS. > > (regno_ok_for_base_p_1): Add insn argument. > > Pass to REGNO_MODE_CODE_OK_FOR_BASE_P. > > (regno_ok_for_base_p): Add insn argument and parse to > > ok_for_base_p_1. > > * config/avr/avr.h (MODE_CODE_BASE_REG_CLASS): Add insn argument. > > (REGNO_MODE_CODE_OK_FOR_BASE_P): Ditto. > > * config/gcn/gcn.h (MODE_CODE_BASE_REG_CLASS): Ditto. > > (REGNO_MODE_CODE_OK_FOR_BASE_P): Ditto. > > * config/rl78/rl78.h (REGNO_MODE_CODE_OK_FOR_BASE_P): Ditto. > > (MODE_CODE_BASE_REG_CLASS): Ditto. > > * doc/tm.texi: Add insn argument for MODE_CODE_BASE_REG_CLASS > > and REGNO_MODE_CODE_OK_FOR_BASE_P. > > * doc/tm.texi.in: Ditto. > > * lra-constraints.cc (process_address_1): Pass insn to > > base_reg_class. > > (curr_insn_transform): Ditto. > > * reload.cc (find_reloads): Ditto. > > (find_reloads_address): Ditto. > > (find_reloads_address_1): Ditto. > > (find_reloads_subreg_address): Ditto. > > * reload1.cc (maybe_fix_stack_asms): Ditto. > > --- > > gcc/addresses.h| 15 +-- > > gcc/config/avr/avr.h | 5 +++-- > > gcc/config/gcn/gcn.h | 4 ++-- > > gcc/config/rl78/rl78.h | 6 -- > > gcc/doc/tm.texi| 8 ++-- > > gcc/doc/tm.texi.in | 8 ++-- > > gcc/lra-constraints.cc | 15 +-- > > gcc/reload.cc | 30 ++ > > gcc/reload1.cc | 2 +- > > 9 files changed, 58 insertions(+), 35 deletions(-) > > > > diff --git a/gcc/addresses.h b/gcc/addresses.h > > index 3519c241c6d..08b100cfe6d 100644 > > --- a/gcc/addresses.h > > +++ b/gcc/addresses.h > > @@ -28,11 +28,12 @@ inline enum reg_class > > base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, > > addr_space_t as ATTRIBUTE_UNUSED, > > enum rtx_code outer_code ATTRIBUTE_UNUSED, > > - enum rtx_code index_code ATTRIBUTE_UNUSED) > > + enum rtx_code index_code ATTRIBUTE_UNUSED, > > + rtx_insn *insn ATTRIBUTE_UNUSED = NULL) > > { > > #ifdef MODE_CODE_BASE_REG_CLASS > >return MODE_CODE_BASE_REG_CLASS (MACRO_MODE (mode), as, outer_code, > > - index_code); > > + index_code, insn); > > #else > > #ifdef MODE_BASE_REG_REG_CLASS > >if (index_code == REG) > > @@ -56,11 +57,12 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, > > machine_mode mode ATTRIBUTE_UNUSED, > > addr_space_t as ATTRIBUTE_UNUSED, > > enum rtx_code outer_code ATTRIBUTE_UNUSED, > > -enum rtx_code index_code ATTRIBUTE_UNUSED) > > +enum rtx_code index_code ATTRIBUTE_UNUSED, > > +rtx_insn* insn ATTRIBUTE_UNUSED = NULL) > > { > > #ifdef REGNO_MODE_CODE_OK_FOR_BASE_P > >return REGNO_MODE_CODE_OK_FOR_BASE_P (regno, MACRO_MODE (mode), as, > > - outer_code, index_code); > > + outer_code, index_code, insn); > > #else > > #ifdef REGNO_MODE_OK_FOR_REG_BASE_P > >if (index_code == REG) > > @@ -79,12 +81,13 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, > > > > inline bool > > regno_ok_for_base_p (unsigned regno, machine_mode mode, addr_space_t as, > > -enum rtx_code outer_code, enum rtx_code index_code) > > +enum rtx_code outer_code, enum rtx_code index_code, > > +rtx_insn* insn =
Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote: > > From: Kong Lingling > > Current reload infrastructure does not support selective base_reg_class > for backend insn. Add insn argument to base_reg_class for > lra/reload usage. I don't think this is the correct approach. Ideally, a memory constraint should somehow encode its BASE/INDEX register class. Instead of passing "insn", simply a different constraint could be used in the constraint string of the relevant insn. Uros. > > gcc/ChangeLog: > > * addresses.h (base_reg_class): Add insn argument. > Pass to MODE_CODE_BASE_REG_CLASS. > (regno_ok_for_base_p_1): Add insn argument. > Pass to REGNO_MODE_CODE_OK_FOR_BASE_P. > (regno_ok_for_base_p): Add insn argument and parse to ok_for_base_p_1. > * config/avr/avr.h (MODE_CODE_BASE_REG_CLASS): Add insn argument. > (REGNO_MODE_CODE_OK_FOR_BASE_P): Ditto. > * config/gcn/gcn.h (MODE_CODE_BASE_REG_CLASS): Ditto. > (REGNO_MODE_CODE_OK_FOR_BASE_P): Ditto. > * config/rl78/rl78.h (REGNO_MODE_CODE_OK_FOR_BASE_P): Ditto. > (MODE_CODE_BASE_REG_CLASS): Ditto. > * doc/tm.texi: Add insn argument for MODE_CODE_BASE_REG_CLASS > and REGNO_MODE_CODE_OK_FOR_BASE_P. > * doc/tm.texi.in: Ditto. > * lra-constraints.cc (process_address_1): Pass insn to > base_reg_class. > (curr_insn_transform): Ditto. > * reload.cc (find_reloads): Ditto. > (find_reloads_address): Ditto. > (find_reloads_address_1): Ditto. > (find_reloads_subreg_address): Ditto. > * reload1.cc (maybe_fix_stack_asms): Ditto. > --- > gcc/addresses.h| 15 +-- > gcc/config/avr/avr.h | 5 +++-- > gcc/config/gcn/gcn.h | 4 ++-- > gcc/config/rl78/rl78.h | 6 -- > gcc/doc/tm.texi| 8 ++-- > gcc/doc/tm.texi.in | 8 ++-- > gcc/lra-constraints.cc | 15 +-- > gcc/reload.cc | 30 ++ > gcc/reload1.cc | 2 +- > 9 files changed, 58 insertions(+), 35 deletions(-) > > diff --git a/gcc/addresses.h b/gcc/addresses.h > index 3519c241c6d..08b100cfe6d 100644 > --- a/gcc/addresses.h > +++ b/gcc/addresses.h > @@ -28,11 +28,12 @@ inline enum reg_class > base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, > addr_space_t as ATTRIBUTE_UNUSED, > enum rtx_code outer_code ATTRIBUTE_UNUSED, > - enum rtx_code index_code ATTRIBUTE_UNUSED) > + enum rtx_code index_code ATTRIBUTE_UNUSED, > + rtx_insn *insn ATTRIBUTE_UNUSED = NULL) > { > #ifdef MODE_CODE_BASE_REG_CLASS >return MODE_CODE_BASE_REG_CLASS (MACRO_MODE (mode), as, outer_code, > - index_code); > + index_code, insn); > #else > #ifdef MODE_BASE_REG_REG_CLASS >if (index_code == REG) > @@ -56,11 +57,12 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, > machine_mode mode ATTRIBUTE_UNUSED, > addr_space_t as ATTRIBUTE_UNUSED, > enum rtx_code outer_code ATTRIBUTE_UNUSED, > -enum rtx_code index_code ATTRIBUTE_UNUSED) > +enum rtx_code index_code ATTRIBUTE_UNUSED, > +rtx_insn* insn ATTRIBUTE_UNUSED = NULL) > { > #ifdef REGNO_MODE_CODE_OK_FOR_BASE_P >return REGNO_MODE_CODE_OK_FOR_BASE_P (regno, MACRO_MODE (mode), as, > - outer_code, index_code); > + outer_code, index_code, insn); > #else > #ifdef REGNO_MODE_OK_FOR_REG_BASE_P >if (index_code == REG) > @@ -79,12 +81,13 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, > > inline bool > regno_ok_for_base_p (unsigned regno, machine_mode mode, addr_space_t as, > -enum rtx_code outer_code, enum rtx_code index_code) > +enum rtx_code outer_code, enum rtx_code index_code, > +rtx_insn* insn = NULL) > { >if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0) > regno = reg_renumber[regno]; > > - return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); > + return ok_for_base_p_1 (regno, mode, as, outer_code, index_code, insn); > } > > #endif /* GCC_ADDRESSES_H */ > diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h > index 8e7e00db13b..1d090fe0838 100644 > --- a/gcc/config/avr/avr.h > +++ b/gcc/config/avr/avr.h > @@ -280,12 +280,13 @@ enum reg_class { > > #define REGNO_REG_CLASS(R) avr_regno_reg_class(R) > > -#define MODE_CODE_BASE_REG_CLASS(mode, as, outer_code, index_code) \ > +#define MODE_CODE_BASE_REG_CLASS(mode, as, outer_code, index_code, insn) \ >avr_mode_code_base_reg_class (mode, as, outer_code, index_code) > > #define INDEX_REG_CLASS NO_REGS > > -#define REGNO_MODE_CODE_OK_FOR_BASE_P(num, mode, as, outer_code, index_code) > \ > +#define REGNO_MODE_CODE_OK_FOR_BASE_P(num, mod
[PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class
From: Kong Lingling Current reload infrastructure does not support selective base_reg_class for backend insn. Add insn argument to base_reg_class for lra/reload usage. gcc/ChangeLog: * addresses.h (base_reg_class): Add insn argument. Pass to MODE_CODE_BASE_REG_CLASS. (regno_ok_for_base_p_1): Add insn argument. Pass to REGNO_MODE_CODE_OK_FOR_BASE_P. (regno_ok_for_base_p): Add insn argument and parse to ok_for_base_p_1. * config/avr/avr.h (MODE_CODE_BASE_REG_CLASS): Add insn argument. (REGNO_MODE_CODE_OK_FOR_BASE_P): Ditto. * config/gcn/gcn.h (MODE_CODE_BASE_REG_CLASS): Ditto. (REGNO_MODE_CODE_OK_FOR_BASE_P): Ditto. * config/rl78/rl78.h (REGNO_MODE_CODE_OK_FOR_BASE_P): Ditto. (MODE_CODE_BASE_REG_CLASS): Ditto. * doc/tm.texi: Add insn argument for MODE_CODE_BASE_REG_CLASS and REGNO_MODE_CODE_OK_FOR_BASE_P. * doc/tm.texi.in: Ditto. * lra-constraints.cc (process_address_1): Pass insn to base_reg_class. (curr_insn_transform): Ditto. * reload.cc (find_reloads): Ditto. (find_reloads_address): Ditto. (find_reloads_address_1): Ditto. (find_reloads_subreg_address): Ditto. * reload1.cc (maybe_fix_stack_asms): Ditto. --- gcc/addresses.h| 15 +-- gcc/config/avr/avr.h | 5 +++-- gcc/config/gcn/gcn.h | 4 ++-- gcc/config/rl78/rl78.h | 6 -- gcc/doc/tm.texi| 8 ++-- gcc/doc/tm.texi.in | 8 ++-- gcc/lra-constraints.cc | 15 +-- gcc/reload.cc | 30 ++ gcc/reload1.cc | 2 +- 9 files changed, 58 insertions(+), 35 deletions(-) diff --git a/gcc/addresses.h b/gcc/addresses.h index 3519c241c6d..08b100cfe6d 100644 --- a/gcc/addresses.h +++ b/gcc/addresses.h @@ -28,11 +28,12 @@ inline enum reg_class base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, addr_space_t as ATTRIBUTE_UNUSED, enum rtx_code outer_code ATTRIBUTE_UNUSED, - enum rtx_code index_code ATTRIBUTE_UNUSED) + enum rtx_code index_code ATTRIBUTE_UNUSED, + rtx_insn *insn ATTRIBUTE_UNUSED = NULL) { #ifdef MODE_CODE_BASE_REG_CLASS return MODE_CODE_BASE_REG_CLASS (MACRO_MODE (mode), as, outer_code, - index_code); + index_code, insn); #else #ifdef MODE_BASE_REG_REG_CLASS if (index_code == REG) @@ -56,11 +57,12 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED, addr_space_t as ATTRIBUTE_UNUSED, enum rtx_code outer_code ATTRIBUTE_UNUSED, -enum rtx_code index_code ATTRIBUTE_UNUSED) +enum rtx_code index_code ATTRIBUTE_UNUSED, +rtx_insn* insn ATTRIBUTE_UNUSED = NULL) { #ifdef REGNO_MODE_CODE_OK_FOR_BASE_P return REGNO_MODE_CODE_OK_FOR_BASE_P (regno, MACRO_MODE (mode), as, - outer_code, index_code); + outer_code, index_code, insn); #else #ifdef REGNO_MODE_OK_FOR_REG_BASE_P if (index_code == REG) @@ -79,12 +81,13 @@ ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, inline bool regno_ok_for_base_p (unsigned regno, machine_mode mode, addr_space_t as, -enum rtx_code outer_code, enum rtx_code index_code) +enum rtx_code outer_code, enum rtx_code index_code, +rtx_insn* insn = NULL) { if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0) regno = reg_renumber[regno]; - return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); + return ok_for_base_p_1 (regno, mode, as, outer_code, index_code, insn); } #endif /* GCC_ADDRESSES_H */ diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index 8e7e00db13b..1d090fe0838 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -280,12 +280,13 @@ enum reg_class { #define REGNO_REG_CLASS(R) avr_regno_reg_class(R) -#define MODE_CODE_BASE_REG_CLASS(mode, as, outer_code, index_code) \ +#define MODE_CODE_BASE_REG_CLASS(mode, as, outer_code, index_code, insn) \ avr_mode_code_base_reg_class (mode, as, outer_code, index_code) #define INDEX_REG_CLASS NO_REGS -#define REGNO_MODE_CODE_OK_FOR_BASE_P(num, mode, as, outer_code, index_code) \ +#define REGNO_MODE_CODE_OK_FOR_BASE_P(num, mode, as, outer_code, \ + index_code, insn) \ avr_regno_mode_code_ok_for_base_p (num, mode, as, outer_code, index_code) #define REGNO_OK_FOR_INDEX_P(NUM) 0 diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h index 4ff9a5d4d12..b56702a77fd 100644 --- a/gcc/config/gcn/gcn.h +++ b/gcc/config/gcn/gcn.h @@ -437,9 +437,9 @@ enum reg_class 0x, 0x, 0x, 0x, 0x, 0 }} #define REGNO_REG_CLASS(REGNO