Re: [gem5-dev] Namespace Inconvenience
Hi Daneil, thanks for the heads up. I've seen similar things like that
every once in a while in the past and had hoped to some day nail down where
the stale files were. It seems to be the param structure definitions for
you? I can see how that would happen since those are generated from python,
change infrequently, and scons may not realize the resulting file would now
be different. It would be great to actually fix that!
Gabe
On Fri, Apr 17, 2020 at 12:19 PM Daniel Carvalho
wrote:
> Hello all,
>
> I have just merged
> https://gem5-review.googlesource.com/c/public/gem5/+/24537, which may
> cause the following inconvenience:
> In file included from
> build/ISA/python/_m5/param_BaseCache.cc:4:0:build/ISA/params/BaseCache.hh:66:5:
> error: 'BasePrefetcher' does not name a type BasePrefetcher *
> prefetcher;
> ^
> build/ISA/python/_m5/param_BaseCache.cc: In function 'void
> module_init(pybind11::module&)':build/ISA/python/_m5/param_BaseCache.cc:49:39:
> error: 'prefetcher' is not a member of 'BaseCacheParams'
> .def_readwrite("prefetcher", ::prefetcher)
>^
> In file included from build/ISA/params/Cache.hh:6:0, from
> build/ISA/python/_m5/param_Cache.cc:4:build/ISA/params/BaseCache.hh:66:5:
> error: 'BasePrefetcher' does not name a type BasePrefetcher *
> prefetcher;
> If that is the case for you, please delete the respective
> build/ISA/params/BaseCache.hh to force updating that file without a
> complete rebuild. Since I plan to add namespaces to other SimObjects in the
> future, you may experience an equivalent issue, but the fix will be similar.
>
> Regards,Daniel
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[gem5-dev] Design doc - Merge gem5’s VPtr and BufferArg classes
One of these types is no longer used since Alpha was deleted, and they're pretty similar to one another but with some complementary capabilities. I put together a design doc which lays out how to merge them, and add some minor new features like teaching the GuestABI to construct them automatically from in-guest pointers. https://docs.google.com/document/d/1BYHBJcf7dB2Z25zAZ9snbeRKfstK9uERYH_3h66w_tc/edit?usp=sharing Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] How to get the size in bytes of a guest int or unsigned value to implement a system call?
Hi Ciro. There are some folks from AMD I think who have been doing quite a lot with syscall emulation and should probably chime in too, but here is my understanding. If you're accepting an address, you should use the Addr type. This is sometimes treated specially, and even though it's a 64 bit value should be filled from, for example, a 32 bit register where the native pointer is that size. I have an idea for something slightly more automatic than that which I've sent to my team internally and which I'll probably send externally shortly (I just realized I hadn't :-) ). Don't worry about that for now, just using an Addr and constructing a BufferArg manually is fine. If you're accepting a type of a fixed size, then use a uintXX_t or an intXX_t which will be the same size no matter who's frame of reference you're talking about. If you're using something that varies from system to system like I think a size_t or a structure with variable field placement and types, you can either wing it and hope it's consistent (less headache, more possibility for bugs, probably not great but it's in the codebase now I think), or you can implement your syscall as a template, define your types, structures, constants, etc., in the OS class, and then use that as the template parameter and get all your actual types from that. Gabe On Fri, Apr 17, 2020 at 1:39 PM Ciro Santilli wrote: > I want to implement the simple getcpu syscall. > > According to man getcpu and kernel source in kernel/sys.c, that function > as an argument an unsigned *cpu to which it writes the value. > > I was looking through the other syscall implementations in syscall_emul.hh > but all I've seen so far appear to assume host and guest sizes match and > simply do a sizeof() to determine the size of their BufferArg. > > Is this supported by your Guest ABI patches Gabe, and if so is there an > example usage somewhere in the code? > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: sim: Use off_t for mmap offset arguments
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27367 )
Change subject: sim: Use off_t for mmap offset arguments
..
sim: Use off_t for mmap offset arguments
The GuestABI used to call the system-calls infers the size of values
read from the registers based on the function signature of the system
call. For mmap this was causing offset to be truncated to a 32-bit
value. In the GPUComputeDriver mmap, the offset must be a 64-bit
value. This fixes a bug where the doorbell memory was not setup and
causing GPU applications to fail.
Change-Id: I75d9b32c0470d1907c68826ef81cf6cd46f60ea7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27367
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Tested-by: kokoro
Reviewed-by: Matthew Poremba
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/arch/x86/linux/linux.hh
M src/sim/syscall_emul.hh
2 files changed, 20 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Matthew Poremba: Looks good to me, approved
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh
index e373daf..4705123 100644
--- a/src/arch/x86/linux/linux.hh
+++ b/src/arch/x86/linux/linux.hh
@@ -190,6 +190,14 @@
static const int NUM_OPEN_FLAGS;
+//@{
+/// Basic X86_64 Linux types
+typedef uint64_t size_t;
+typedef uint64_t off_t;
+typedef int64_t time_t;
+typedef int64_t clock_t;
+//@}
+
static const unsigned TGT_MAP_SHARED= 0x1;
static const unsigned TGT_MAP_PRIVATE = 0x2;
static const unsigned TGT_MAP_32BIT = 0x00040;
@@ -318,6 +326,14 @@
static SyscallFlagTransTable mmapFlagTable[];
+//@{
+/// Basic X86 Linux types
+typedef uint32_t size_t;
+typedef uint32_t off_t;
+typedef int32_t time_t;
+typedef int32_t clock_t;
+//@}
+
static const unsigned TGT_MAP_SHARED= 0x1;
static const unsigned TGT_MAP_PRIVATE = 0x2;
static const unsigned TGT_MAP_32BIT = 0x00040;
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 11561a6..e5444b1 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1642,8 +1642,8 @@
template
SyscallReturn
mmapFunc(SyscallDesc *desc, ThreadContext *tc,
- Addr start, uint64_t length, int prot, int tgt_flags,
- int tgt_fd, int offset)
+ Addr start, typename OS::size_t length, int prot,
+ int tgt_flags, int tgt_fd, typename OS::off_t offset)
{
auto p = tc->getProcessPtr();
Addr page_bytes = tc->getSystemPtr()->getPageBytes();
@@ -1826,8 +1826,8 @@
template
SyscallReturn
mmap2Func(SyscallDesc *desc, ThreadContext *tc,
- Addr start, uint64_t length, int prot, int tgt_flags,
- int tgt_fd, int offset)
+ Addr start, typename OS::size_t length, int prot,
+ int tgt_flags, int tgt_fd, typename OS::off_t offset)
{
return mmapFunc(desc, tc, start, length, prot, tgt_flags,
tgt_fd, offset *
tc->getSystemPtr()->getPageBytes());
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27367
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I75d9b32c0470d1907c68826ef81cf6cd46f60ea7
Gerrit-Change-Number: 27367
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] How to get the size in bytes of a guest int or unsigned value to implement a system call?
I want to implement the simple getcpu syscall. According to man getcpu and kernel source in kernel/sys.c, that function as an argument an unsigned *cpu to which it writes the value. I was looking through the other syscall implementations in syscall_emul.hh but all I've seen so far appear to assume host and guest sizes match and simply do a sizeof() to determine the size of their BufferArg. Is this supported by your Guest ABI patches Gabe, and if so is there an example usage somewhere in the code? ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Create Prefetcher namespace
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24537 )
Change subject: mem-cache: Create Prefetcher namespace
..
mem-cache: Create Prefetcher namespace
Create a namespace for the Prefetcher classes.
As a side effect the Prefetcher suffix has been removed from the
C++'s classes names, and the memory leaking destructor overrides
have been fixed.
Change-Id: I9bae492d2fd4734bcdfb68c164345898e65102b2
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24537
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/base.hh
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/access_map_pattern_matching.cc
M src/mem/cache/prefetch/access_map_pattern_matching.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/bop.cc
M src/mem/cache/prefetch/bop.hh
M src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
M src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
M src/mem/cache/prefetch/indirect_memory.cc
M src/mem/cache/prefetch/indirect_memory.hh
M src/mem/cache/prefetch/irregular_stream_buffer.cc
M src/mem/cache/prefetch/irregular_stream_buffer.hh
M src/mem/cache/prefetch/multi.cc
M src/mem/cache/prefetch/multi.hh
M src/mem/cache/prefetch/pif.cc
M src/mem/cache/prefetch/pif.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/sbooe.cc
M src/mem/cache/prefetch/sbooe.hh
M src/mem/cache/prefetch/signature_path.cc
M src/mem/cache/prefetch/signature_path.hh
M src/mem/cache/prefetch/signature_path_v2.cc
M src/mem/cache/prefetch/signature_path_v2.hh
M src/mem/cache/prefetch/slim_ampm.cc
M src/mem/cache/prefetch/slim_ampm.hh
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
34 files changed, 434 insertions(+), 305 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index e77bfe0..3efc7c7 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -75,7 +75,9 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
-class BasePrefetcher;
+namespace Prefetcher {
+class Base;
+}
class MSHR;
class MasterPort;
class QueueEntry;
@@ -321,7 +323,7 @@
BaseCacheCompressor* compressor;
/** Prefetcher */
-BasePrefetcher *prefetcher;
+Prefetcher::Base *prefetcher;
/** To probe when a cache hit occurs */
ProbePointArg *ppHit;
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 33eb1ea..8cfefe1 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -59,6 +59,7 @@
class BasePrefetcher(ClockedObject):
type = 'BasePrefetcher'
abstract = True
+cxx_class = 'Prefetcher::Base'
cxx_header = "mem/cache/prefetch/base.hh"
cxx_exports = [
PyBindMethod("addEventProbe"),
@@ -106,7 +107,7 @@
class MultiPrefetcher(BasePrefetcher):
type = 'MultiPrefetcher'
-cxx_class = 'MultiPrefetcher'
+cxx_class = 'Prefetcher::Multi'
cxx_header = 'mem/cache/prefetch/multi.hh'
prefetchers = VectorParam.BasePrefetcher([], "Array of prefetchers")
@@ -114,7 +115,7 @@
class QueuedPrefetcher(BasePrefetcher):
type = "QueuedPrefetcher"
abstract = True
-cxx_class = "QueuedPrefetcher"
+cxx_class = "Prefetcher::Queued"
cxx_header = "mem/cache/prefetch/queued.hh"
latency = Param.Int(1, "Latency for generated prefetches")
queue_size = Param.Int(32, "Maximum number of queued prefetches")
@@ -140,7 +141,7 @@
class StridePrefetcher(QueuedPrefetcher):
type = 'StridePrefetcher'
-cxx_class = 'StridePrefetcher'
+cxx_class = 'Prefetcher::Stride'
cxx_header = "mem/cache/prefetch/stride.hh"
# Do not consult stride prefetcher on instruction accesses
@@ -163,14 +164,14 @@
class TaggedPrefetcher(QueuedPrefetcher):
type = 'TaggedPrefetcher'
-cxx_class = 'TaggedPrefetcher'
+cxx_class = 'Prefetcher::Tagged'
cxx_header = "mem/cache/prefetch/tagged.hh"
degree = Param.Int(2, "Number of prefetches to generate")
class IndirectMemoryPrefetcher(QueuedPrefetcher):
type = 'IndirectMemoryPrefetcher'
-cxx_class = 'IndirectMemoryPrefetcher'
+cxx_class = 'Prefetcher::IndirectMemory'
cxx_header = "mem/cache/prefetch/indirect_memory.hh"
pt_table_entries = Param.MemorySize("16",
"Number of entries of the Prefetch Table")
@@ -205,7 +206,7 @@
class SignaturePathPrefetcher(QueuedPrefetcher):
type = 'SignaturePathPrefetcher'
-cxx_class
[gem5-dev] Namespace Inconvenience
Hello all,
I have just merged https://gem5-review.googlesource.com/c/public/gem5/+/24537,
which may cause the following inconvenience:
In file included from
build/ISA/python/_m5/param_BaseCache.cc:4:0:build/ISA/params/BaseCache.hh:66:5:
error: 'BasePrefetcher' does not name a type BasePrefetcher * prefetcher;
^
build/ISA/python/_m5/param_BaseCache.cc: In function 'void
module_init(pybind11::module&)':build/ISA/python/_m5/param_BaseCache.cc:49:39:
error: 'prefetcher' is not a member of 'BaseCacheParams'
.def_readwrite("prefetcher", ::prefetcher)
^
In file included from build/ISA/params/Cache.hh:6:0, from
build/ISA/python/_m5/param_Cache.cc:4:build/ISA/params/BaseCache.hh:66:5:
error: 'BasePrefetcher' does not name a type BasePrefetcher * prefetcher;
If that is the case for you, please delete the respective
build/ISA/params/BaseCache.hh to force updating that file without a complete
rebuild. Since I plan to add namespaces to other SimObjects in the future, you
may experience an equivalent issue, but the fix will be similar.
Regards,Daniel
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Re: [gem5-dev] gem5-resources: Feedback appreciated!
Yes, my main point is that hopefully when you run "make ISA=arm64" / or scons
it will build at least all single input source files that we have in one go
e.g.:
main.c -> out/arm64/main.out
test2.c -> out/arm64/test2.out
for the given ISA, as I did in the mentioned patchset, without me having to cd
into various directories and run make in them.
From: gem5-dev on behalf of Bobby Bruce
Sent: Friday, April 17, 2020 12:45 AM
To: gem5 Developer List
Subject: Re: [gem5-dev] gem5-resources: Feedback appreciated!
Ciro,
Could you flesh out for me what you're asking here, and how it relates to
this gem5-resources repository?
If you want to add code compilable to all ISAs, etc, you'll be free to do
so.
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616
web: https://www.bobbybruce.net
On Thu, Apr 16, 2020 at 2:40 AM Ciro Santilli wrote:
> Thanks for this Bobby,
>
> I think this is in your plans, but just to confirm, what I would really
> like to see is a way to build all ISA agnostic C/C++ userland (and
> hopefully baremetal) sources that generate for a give ISA with a single
> build command along the lines of:
> https://gem5-review.googlesource.com/c/public/gem5/+/27308/1/tests/test-progs/Makefile
> (except possibly for huge userland executables that take a long time to
> compile or have non-trivial dependencies)
>
>
> From: gem5-dev on behalf of Gabe Black <
> gabebl...@google.com>
> Sent: Tuesday, April 14, 2020 2:43 AM
> To: gem5 Developer List
> Subject: Re: [gem5-dev] gem5-resources: Feedback appreciated!
>
> I think this is a good idea. I would advocate to not use Make for these
> since it sort of falls over, or gets very complicated, when trying to build
> the same source for multiple target architectures simultaneously. I have
> CLs which convert the m5 utility's build over to scons which I think worked
> out well, and with some thought could be regularized and hopefully made
> easy to stamp out for different test, etc, sources. Of course, as long as
> we don't say though shalt use make, it doesn't really matter in the short
> term since that's relatively easy to change in the future.
>
> Gabe
>
> On Mon, Apr 13, 2020 at 11:58 AM Bobby Bruce wrote:
>
> > Dear all,
> >
> > As part of the gem5 20 release, we want to improve the way we handle the
> > gem5 resources. What I mean by resources are things such as test
> programs,
> > images, kernels, etc; stuff that we don't strictly need to compile or run
> > gem5, but we frequently use (and/or may be difficult to distribute as
> part
> > of gem5 due to licencing conflicts). At present, some of these are
> > currently committed within the gem5 repository, and some are pulled from
> > our Google Cloud bucket as needed (there may be others outside of this of
> > which I am not aware of).
> >
> > The problem at present is:
> > A) The resources are not available in some common way across the project.
> > B) The resources change over time and this change is not well recorded,
> > particularly in the case of compiled binaries. The source of these
> binaries
> > needs to be provided and changes to them properly logged.
> > C) Similar to B), resources do not map to versions. A resource can change
> > in our cloud bucket over time, which may break certain activities if
> needed
> > by a previous version of gem5.
> >
> > The proposal is to add another repository alongside gem5 and gem5-website
> > on googlesource. This repository will contain the resources' sources,
> which
> > can be compiled to produce the resources used by the project. I've
> started
> > producing this here: https://github.com/gem5/gem5-resources. Please
> have a
> > look and consult the README.md for an explanation on how this repository
> > would work.
> >
> > The compiled products of this repo would be uploaded to our
> dist.gem5.org
> > bucket. If someone wanted to alter or add a resource to gem5, they'd do
> so
> > in this repo (via Gerrit). The gem5-resource directory would adopt the
> same
> > versioning and master/develop branch split system as gem5 currently does.
> > So, as gem5 v20.0.0.0 is released, so would gem5-resources v20.0.0.0.
> > Version X of gem5 would always be assumed to work with version X of
> > gem5-resources. The dist.gem5.org bucket would be kept up to date.
> > dist.gem5.org/dist/current would track changes made to the
> gem5-resources
> > develop branch with dist.gem5.org/dist/${VERSION}
>
> > containing the resources
> > for the ${VERSION} release.
> >
> > A few notes:
> > - gem5 19 contains tests that pull from dist.gem5.org/dist/current. I
> > believe I'll need to apply a hotfix to this release to pull from
> > dist.gem5.org/dist/v19-0-0-1 instead.
> > - Right now there is a lot of stuff on dist.gem5.org/dist/current which
> I
> > do not have sources for. I may need to ask
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby, mem-garnet: Multiple networks per RubySystem
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27927 )
Change subject: mem-ruby,mem-garnet: Multiple networks per RubySystem
..
mem-ruby,mem-garnet: Multiple networks per RubySystem
Add support for multiple networks per RubySystem. This is done by
introducing local IDs to each network and translating from a global ID
passed around through Ruby and SLICC code. The local IDs represents the
NodeID of a MachineType in the network and are ordered the same way
that NodeIDs are ordered using MachineType_base_number. If there are
not multiple networks in a RubySystem the local and global IDs are the
same value.
This is useful in cases where multiple isolated networks are needed to
support devices with Ruby caches which do not interact with other
networks. For example, a dGPU device will have a cache hierarchy that
will not interact with the CPU cache hierachy.
Change-Id: I33a917b3a394eec84b16fbf001c3c2c44c047f66
JIRA: https://gem5.atlassian.net/browse/GEM5-445
---
M src/mem/ruby/network/Network.cc
M src/mem/ruby/network/Network.hh
M src/mem/ruby/network/Network.py
M src/mem/ruby/network/garnet2.0/GarnetNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
7 files changed, 95 insertions(+), 34 deletions(-)
diff --git a/src/mem/ruby/network/Network.cc
b/src/mem/ruby/network/Network.cc
index 57834f2..4f7c51e 100644
--- a/src/mem/ruby/network/Network.cc
+++ b/src/mem/ruby/network/Network.cc
@@ -57,13 +57,44 @@
// Total nodes/controllers in network
// Must make sure this is called after the State Machine constructors
-m_nodes = MachineType_base_number(MachineType_NUM);
+if (p->local_nodes) {
+m_nodes = p->local_nodes;
+} else {
+m_nodes = MachineType_base_number(MachineType_NUM);
+}
+
assert(m_nodes != 0);
assert(m_virtual_networks != 0);
m_topology_ptr = new Topology(p->routers.size(), p->ext_links,
p->int_links);
+// Populate localNodeVersions with the version of each MachineType in
+// this network. This will be used to compute a global to local ID.
+// Do this by looking at the ext_node for each ext_link. There is one
+// ext_node per ext_link and it points to an AbstractController.
+// For RubySystems with one network global and local ID are the same.
+std::unordered_map> localNodeVersions;
+for (auto : params()->ext_links) {
+AbstractController *cntrl = it->params()->ext_node;
+localNodeVersions[cntrl->getType()].push_back(cntrl->getVersion());
+}
+
+// Compute a local ID for each MachineType using the same order as
SLICC
+NodeID local_node_id = 0;
+for (int i = 0; i < MachineType_base_level(MachineType_NUM); ++i) {
+MachineType mach = static_cast(i);
+if (localNodeVersions.count(mach)) {
+for (auto : localNodeVersions.at(mach)) {
+// Get the global ID Ruby will pass around
+NodeID global_node_id = MachineType_base_number(mach) +
ver;
+globalToLocalMap.insert(
+std::make_pair(global_node_id, local_node_id));
+++local_node_id;
+}
+}
+}
+
// Allocate to and from queues
// Queues that are getting messages from protocol
m_toNetQueues.resize(m_nodes);
@@ -158,11 +189,11 @@
}
void
-Network::checkNetworkAllocation(NodeID id, bool ordered,
+Network::checkNetworkAllocation(NodeID local_id, bool ordered,
int network_num,
std::string vnet_type)
{
-fatal_if(id >= m_nodes, "Node ID is out of range");
+fatal_if(local_id >= m_nodes, "Node ID is out of range");
fatal_if(network_num >= m_virtual_networks, "Network id is out of
range");
if (ordered) {
@@ -174,25 +205,31 @@
void
-Network::setToNetQueue(NodeID id, bool ordered, int network_num,
+Network::setToNetQueue(NodeID global_id, bool ordered, int network_num,
std::string vnet_type, MessageBuffer *b)
{
-checkNetworkAllocation(id, ordered, network_num, vnet_type);
-while (m_toNetQueues[id].size() <= network_num) {
-m_toNetQueues[id].push_back(nullptr);
+assert(globalToLocalMap.count(global_id));
+NodeID local_id = globalToLocalMap[global_id];
+checkNetworkAllocation(local_id, ordered, network_num, vnet_type);
+
+while (m_toNetQueues[local_id].size() <= network_num) {
+m_toNetQueues[local_id].push_back(nullptr);
}
-m_toNetQueues[id][network_num] = b;
+m_toNetQueues[local_id][network_num] = b;
}
void
-Network::setFromNetQueue(NodeID id, bool ordered, int network_num,
+Network::setFromNetQueue(NodeID global_id, bool ordered, int network_num,
[gem5-dev] Change in gem5/gem5[develop]: sim-se: add missing path redirection to mmap createObjectFile
Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27887 )
Change subject: sim-se: add missing path redirection to mmap
createObjectFile
..
sim-se: add missing path redirection to mmap createObjectFile
The redirection call was mistakenly removed at:
Ide158e69cdff19bc81157e3e9826bcabc2a51140 and that breaks running
cross compiled dynamically linked executables in SE.
JIRA: https://gem5.atlassian.net/browse/GEM5-430
Change-Id: I33419c78fbf183cda0bba98f7035a2b25ebc6fa3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27887
Reviewed-by: Matthew Poremba
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Tested-by: kokoro
Maintainer: Gabe Black
---
M src/sim/syscall_emul.hh
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
Matthew Poremba: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index e1a23a0..11561a6 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1713,7 +1713,8 @@
if (p->interpImage.contains(tc->pcState().instAddr())) {
std::shared_ptr fdep = (*p->fds)[tgt_fd];
auto ffdp = std::dynamic_pointer_cast(fdep);
-ObjectFile *lib = createObjectFile(ffdp->getFileName());
+ObjectFile *lib = createObjectFile(p->checkPathRedirect(
+ffdp->getFileName()));
DPRINTF_SYSCALL(Verbose, "Loading symbols from %s\n",
ffdp->getFileName());
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27887
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I33419c78fbf183cda0bba98f7035a2b25ebc6fa3
Gerrit-Change-Number: 27887
Gerrit-PatchSet: 3
Gerrit-Owner: Ciro Santilli
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: make --disk-images optional in fs.py
Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27867 )
Change subject: configs: make --disk-images optional in fs.py
..
configs: make --disk-images optional in fs.py
The main applications are to run baremetal programs and initramfs Linux
kernel.
Before this patch, disks() calls in makeArmSystem would throw:
IOError: Can't find file 'linux-aarch32-ael.img' on M5_PATH.
In order to achieve this, this commit also removes the default hardcoded
disk image basenames.
For example, before this commit, running without a --disk-image in X86
would automatically search for an image with basename x86root.img in
M5_PATH, which means we would either have to ignore any disk image error,
or else running without disk images would fail.
After this commit, you would have to pass --disk-image x86root.img to
achieve the old behaviour.
Change-Id: I0ae8c4b3b93d0074fd4fca0d5ed52181c50b6c04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27867
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
---
M configs/common/Benchmarks.py
M configs/common/FSConfig.py
2 files changed, 2 insertions(+), 17 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Gabe Black: Looks good to me, approved
Giacomo Travaglini: Looks good to me, but someone else must approve
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index 4c905e3..8477d77 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -55,16 +55,8 @@
def disks(self):
if self.disknames:
return [disk(diskname) for diskname in self.disknames]
-elif buildEnv['TARGET_ISA'] == 'x86':
-return [env.get('LINUX_IMAGE', disk('x86root.img'))]
-elif buildEnv['TARGET_ISA'] == 'arm':
-return [env.get('LINUX_IMAGE', disk('linux-aarch32-ael.img'))]
-elif buildEnv['TARGET_ISA'] == 'sparc':
-return [env.get('LINUX_IMAGE', disk('disk.s10hw2'))]
else:
-print("Don't know what default disk image to use for %s ISA" %
-buildEnv['TARGET_ISA'])
-exit(1)
+return []
def rootdev(self):
if self.root:
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 376ae1a..a424a30 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -205,13 +205,6 @@
self.realview = platform_class()
self._bootmem = self.realview.bootmem
-if isinstance(self.realview, VExpress_EMM64):
-if os.path.split(mdesc.disks()[0])[-1] == 'linux-aarch32-ael.img':
-print("Selected 64-bit ARM architecture, updating default "
- "disk image...")
-mdesc.diskname = 'linaro-minimal-aarch64.img'
-
-
# Attach any PCI devices this platform supports
self.realview.attachPciDevices()
@@ -278,7 +271,7 @@
# the error message below. The disk can have any name now and
# doesn't need to include 'android' substring.
if (mdesc.disks() and
-
os.path.split(mdesc.disks()[0])[-1]).lower().count('android'):
+
os.path.split(mdesc.disks()[0])[-1].lower().count('android')):
if 'android' not in mdesc.os_type():
fatal("It looks like you are trying to boot an Android " \
"platform. To boot Android, you must specify " \
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0ae8c4b3b93d0074fd4fca0d5ed52181c50b6c04
Gerrit-Change-Number: 27867
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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