[Intel-gfx] ✓ Fi.CI.IGT: success for drm/print: Add drm_dbg_ratelimited

[Patchwork]

== Series Details ==

Series: drm/print: Add drm_dbg_ratelimited
URL   : https://patchwork.freedesktop.org/series/124722/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722_full -> Patchwork_124722v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 9)
--

  Missing(1): shard-tglu0 

Known issues


  Here are the changes found in Patchwork_124722v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@device_reset@unbind-reset-rebind:
- shard-dg1:  NOTRUN -> [INCOMPLETE][1] ([i915#9408])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg1-17/igt@device_re...@unbind-reset-rebind.html

  * igt@drm_fdinfo@busy@ccs0:
- shard-dg2:  NOTRUN -> [SKIP][2] ([i915#8414]) +21 other tests skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-2/igt@drm_fdinfo@b...@ccs0.html

  * igt@gem_basic@multigpu-create-close:
- shard-tglu: NOTRUN -> [SKIP][3] ([i915#7697])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-tglu-2/igt@gem_ba...@multigpu-create-close.html

  * igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-lmem0-lmem0:
- shard-dg2:  NOTRUN -> [INCOMPLETE][4] ([i915#7297])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-10/igt@gem_ccs@suspend-res...@xmajor-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_ctx_param@set-priority-not-supported:
- shard-dg2:  NOTRUN -> [SKIP][5] ([fdo#109314])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-6/igt@gem_ctx_pa...@set-priority-not-supported.html

  * igt@gem_ctx_persistence@heartbeat-close:
- shard-dg2:  NOTRUN -> [SKIP][6] ([i915#8555])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-7/igt@gem_ctx_persiste...@heartbeat-close.html

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2:  NOTRUN -> [SKIP][7] ([i915#5882]) +9 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-2/igt@gem_ctx_persistence@saturated-hostile-nopree...@ccs0.html

  * igt@gem_ctx_sseu@mmap-args:
- shard-dg2:  NOTRUN -> [SKIP][8] ([i915#280])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-2/igt@gem_ctx_s...@mmap-args.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglu: NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-tglu-3/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-throttle:
- shard-dg2:  NOTRUN -> [SKIP][10] ([i915#3539]) +1 other test skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-6/igt@gem_exec_f...@basic-throttle.html

  * igt@gem_exec_flush@basic-wb-prw-default:
- shard-dg2:  NOTRUN -> [SKIP][11] ([i915#3539] / [i915#4852]) +2 
other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-7/igt@gem_exec_fl...@basic-wb-prw-default.html

  * igt@gem_exec_params@rsvd2-dirt:
- shard-dg2:  NOTRUN -> [SKIP][12] ([fdo#109283] / [i915#5107])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-6/igt@gem_exec_par...@rsvd2-dirt.html

  * igt@gem_exec_params@secure-non-master:
- shard-dg2:  NOTRUN -> [SKIP][13] ([fdo#112283])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-7/igt@gem_exec_par...@secure-non-master.html

  * igt@gem_exec_reloc@basic-softpin:
- shard-rkl:  NOTRUN -> [SKIP][14] ([i915#3281])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-rkl-3/igt@gem_exec_re...@basic-softpin.html

  * igt@gem_exec_reloc@basic-write-read-active:
- shard-dg2:  NOTRUN -> [SKIP][15] ([i915#3281]) +11 other tests 
skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-1/igt@gem_exec_re...@basic-write-read-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
- shard-dg2:  NOTRUN -> [SKIP][16] ([i915#4537] / [i915#4812])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-6/igt@gem_exec_sched...@preempt-queue-contexts.html

  * igt@gem_fence_thrash@bo-copy:
- shard-dg2:  NOTRUN -> [SKIP][17] ([i915#4860]) +5 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg2-2/igt@gem_fence_thr...@bo-copy.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-dg1:  NOTRUN -> [SKIP][18] ([i915#4860])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/shard-dg1-17/igt@gem_fenced_exec_thr...@no-spare-fences-busy.html

  * igt@gem_lmem_swapping@heavy-verify-random:
 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/lnl: Remove watchdog timers for PSR

[Patchwork]

== Series Details ==

Series: drm/i915/lnl: Remove watchdog timers for PSR
URL   : https://patchwork.freedesktop.org/series/124715/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13722_full -> Patchwork_124715v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_124715v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_124715v1_full, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 9)
--

  Missing(1): shard-tglu0 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_124715v1_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_suspend@basic-s0@lmem0:
- shard-dg2:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/shard-dg2-10/igt@gem_exec_suspend@basic...@lmem0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg2-5/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@i915_selftest@perf@request:
- shard-dg2:  [PASS][3] -> [ABORT][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/shard-dg2-2/igt@i915_selftest@p...@request.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg2-11/igt@i915_selftest@p...@request.html

  
New tests
-

  New tests have been introduced between CI_DRM_13722_full and 
Patchwork_124715v1_full:

### New IGT tests (2) ###

  * igt@kms_plane_alpha_blend@constant-alpha-mid@pipe-a-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_plane_alpha_blend@constant-alpha-mid@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_124715v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@device_reset@unbind-reset-rebind:
- shard-dg1:  NOTRUN -> [INCOMPLETE][5] ([i915#9408])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg1-15/igt@device_re...@unbind-reset-rebind.html

  * igt@drm_fdinfo@busy@ccs0:
- shard-dg2:  NOTRUN -> [SKIP][6] ([i915#8414]) +10 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg2-2/igt@drm_fdinfo@b...@ccs0.html

  * igt@gem_basic@multigpu-create-close:
- shard-dg1:  NOTRUN -> [SKIP][7] ([i915#7697])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg1-17/igt@gem_ba...@multigpu-create-close.html
- shard-tglu: NOTRUN -> [SKIP][8] ([i915#7697])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-tglu-8/igt@gem_ba...@multigpu-create-close.html

  * igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0:
- shard-dg2:  NOTRUN -> [INCOMPLETE][9] ([i915#7297])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg2-5/igt@gem_ccs@suspend-res...@tile4-compressed-compfmt0-smem-lmem0.html

  * igt@gem_ctx_param@set-priority-not-supported:
- shard-dg2:  NOTRUN -> [SKIP][10] ([fdo#109314])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg2-1/igt@gem_ctx_pa...@set-priority-not-supported.html

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2:  NOTRUN -> [SKIP][11] ([i915#5882]) +9 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg2-2/igt@gem_ctx_persistence@saturated-hostile-nopree...@ccs0.html

  * igt@gem_ctx_sseu@mmap-args:
- shard-dg2:  NOTRUN -> [SKIP][12] ([i915#280])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg2-2/igt@gem_ctx_s...@mmap-args.html

  * igt@gem_eio@kms:
- shard-dg2:  [PASS][13] -> [INCOMPLETE][14] ([i915#7892])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/shard-dg2-11/igt@gem_...@kms.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg2-10/igt@gem_...@kms.html

  * igt@gem_exec_balancer@bonded-pair:
- shard-dg1:  NOTRUN -> [SKIP][15] ([i915#4771])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-dg1-17/igt@gem_exec_balan...@bonded-pair.html

  * igt@gem_exec_capture@capture@vcs1-smem:
- shard-mtlp: [PASS][16] -> [DMESG-WARN][17] ([i915#5591])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/shard-mtlp-1/igt@gem_exec_capture@capt...@vcs1-smem.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/shard-mtlp-7/igt@gem_exec_capture@capt...@vcs1-smem.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- 

Re: [Intel-gfx] [PATCH 3/4] drm/i915/guc: Add support for w/a KLVs

[Belgaumkar, Vinay]

On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote:

From: John Harrison 

To prevent running out of bits, new w/a enable flags are being added
via a KLV system instead of a 32 bit flags word.

Signed-off-by: John Harrison 
---
  .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h   |  1 +
  drivers/gpu/drm/i915/gt/uc/intel_guc.h|  3 +
  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 64 ++-
  drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  6 ++
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  5 +-
  5 files changed, 77 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
index dabeaf4f245f3..00d6402333f8e 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
@@ -36,6 +36,7 @@ enum intel_guc_load_status {
INTEL_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_START,
INTEL_GUC_LOAD_STATUS_MPU_DATA_INVALID = 0x73,
INTEL_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID   = 0x74,
+   INTEL_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR= 0x75,
INTEL_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_END,
  
  	INTEL_GUC_LOAD_STATUS_READY= 0xF0,

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 6c392bad29c19..3b1fc5f96306b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -186,6 +186,8 @@ struct intel_guc {
struct guc_mmio_reg *ads_regset;
/** @ads_golden_ctxt_size: size of the golden contexts in the ADS */
u32 ads_golden_ctxt_size;
+   /** @ads_waklv_size: size of workaround KLVs */
+   u32 ads_waklv_size;
/** @ads_capture_size: size of register lists in the ADS used for error 
capture */
u32 ads_capture_size;
/** @ads_engine_usage_size: size of engine usage in the ADS */
@@ -295,6 +297,7 @@ struct intel_guc {
  #define MAKE_GUC_VER(maj, min, pat)   (((maj) << 16) | ((min) << 8) | (pat))
  #define MAKE_GUC_VER_STRUCT(ver)  MAKE_GUC_VER((ver).major, (ver).minor, 
(ver).patch)
  #define GUC_SUBMIT_VER(guc)   
MAKE_GUC_VER_STRUCT((guc)->submission_version)
+#define GUC_FIRMWARE_VER(guc)  
MAKE_GUC_VER_STRUCT((guc)->fw.file_selected.ver)
  
  static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)

  {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 63724e17829a7..792910af3a481 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -46,6 +46,10 @@
   *  +---+
   *  | padding   |
   *  +---+ <== 4K aligned
+ *  | w/a KLVs  |
+ *  +---+
+ *  | padding   |
+ *  +---+ <== 4K aligned
   *  | capture lists |
   *  +---+
   *  | padding   |
@@ -88,6 +92,11 @@ static u32 guc_ads_golden_ctxt_size(struct intel_guc *guc)
return PAGE_ALIGN(guc->ads_golden_ctxt_size);
  }
  
+static u32 guc_ads_waklv_size(struct intel_guc *guc)

+{
+   return PAGE_ALIGN(guc->ads_waklv_size);
+}
+
  static u32 guc_ads_capture_size(struct intel_guc *guc)
  {
return PAGE_ALIGN(guc->ads_capture_size);
@@ -113,7 +122,7 @@ static u32 guc_ads_golden_ctxt_offset(struct intel_guc *guc)
return PAGE_ALIGN(offset);
  }
  
-static u32 guc_ads_capture_offset(struct intel_guc *guc)

+static u32 guc_ads_waklv_offset(struct intel_guc *guc)
  {
u32 offset;
  
@@ -123,6 +132,16 @@ static u32 guc_ads_capture_offset(struct intel_guc *guc)

return PAGE_ALIGN(offset);
  }
  
+static u32 guc_ads_capture_offset(struct intel_guc *guc)

+{
+   u32 offset;
+
+   offset = guc_ads_waklv_offset(guc) +
+guc_ads_waklv_size(guc);
+
+   return PAGE_ALIGN(offset);
+}
+
  static u32 guc_ads_private_data_offset(struct intel_guc *guc)
  {
u32 offset;
@@ -791,6 +810,40 @@ guc_capture_prep_lists(struct intel_guc *guc)
return PAGE_ALIGN(total_size);
  }
  
+static void guc_waklv_init(struct intel_guc *guc)

+{
+   struct intel_gt *gt = guc_to_gt(guc);
+   u32 offset, addr_ggtt, remain, size;
+
+   if (!intel_uc_uses_guc_submission(>uc))
+   return;
+
+   if (GUC_FIRMWARE_VER(guc) < MAKE_GUC_VER(70, 10, 0))
+   return;

should this be <= ?

+
+   GEM_BUG_ON(iosys_map_is_null(>ads_map));
+   offset = guc_ads_waklv_offset(guc);
+   remain = guc_ads_waklv_size(guc);
+
+   /* Add workarounds here */
+

extra blank line?

+   size = guc_ads_waklv_size(guc) - remain;

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Enable Wa_16019325821

[Belgaumkar, Vinay]

On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote:

From: John Harrison 

Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.

Signed-off-by: John Harrison 
---
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c  | 19 +++
  drivers/gpu/drm/i915/gt/intel_engine_types.h  |  7 ---
  drivers/gpu/drm/i915/gt/uc/intel_guc.c|  4 
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  3 ++-
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  8 +++-
  5 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 0143445dba830..8b494825c55f2 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -733,21 +733,23 @@ static u32 *gen12_emit_preempt_busywait(struct 
i915_request *rq, u32 *cs)
  }
  
  /* Wa_14014475959:dg2 */

-#define CCS_SEMAPHORE_PPHWSP_OFFSET0x540
-static u32 ccs_semaphore_offset(struct i915_request *rq)
+/* Wa_16019325821 */
+#define HOLD_SWITCHOUT_SEMAPHORE_PPHWSP_OFFSET 0x540
+static u32 hold_switchout_semaphore_offset(struct i915_request *rq)
  {
return i915_ggtt_offset(rq->context->state) +
-   (LRC_PPHWSP_PN * PAGE_SIZE) + CCS_SEMAPHORE_PPHWSP_OFFSET;
+   (LRC_PPHWSP_PN * PAGE_SIZE) + 
HOLD_SWITCHOUT_SEMAPHORE_PPHWSP_OFFSET;
  }
  
  /* Wa_14014475959:dg2 */

-static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs)
+/* Wa_16019325821 */
+static u32 *hold_switchout_emit_wa_busywait(struct i915_request *rq, u32 *cs)
  {
int i;
  
  	*cs++ = MI_ATOMIC_INLINE | MI_ATOMIC_GLOBAL_GTT | MI_ATOMIC_CS_STALL |

MI_ATOMIC_MOVE;
-   *cs++ = ccs_semaphore_offset(rq);
+   *cs++ = hold_switchout_semaphore_offset(rq);
*cs++ = 0;
*cs++ = 1;
  
@@ -763,7 +765,7 @@ static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs)

MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_EQ_SDD;
*cs++ = 0;
-   *cs++ = ccs_semaphore_offset(rq);
+   *cs++ = hold_switchout_semaphore_offset(rq);
*cs++ = 0;
  
  	return cs;

@@ -780,8 +782,9 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, 
u32 *cs)
cs = gen12_emit_preempt_busywait(rq, cs);
  
  	/* Wa_14014475959:dg2 */

-   if (intel_engine_uses_wa_hold_ccs_switchout(rq->engine))
-   cs = ccs_emit_wa_busywait(rq, cs);
+   /* Wa_16019325821 */
+   if (intel_engine_uses_wa_hold_switchout(rq->engine))
+   cs = hold_switchout_emit_wa_busywait(rq, cs);
  
  	rq->tail = intel_ring_offset(rq, cs);

assert_ring_tail_valid(rq->ring, rq->tail);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index a7e6775980043..68fe1cef9cd94 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -573,7 +573,7 @@ struct intel_engine_cs {
  #define I915_ENGINE_HAS_RCS_REG_STATE  BIT(9)
  #define I915_ENGINE_HAS_EU_PRIORITYBIT(10)
  #define I915_ENGINE_FIRST_RENDER_COMPUTE BIT(11)
-#define I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT BIT(12)
+#define I915_ENGINE_USES_WA_HOLD_SWITCHOUT BIT(12)
unsigned int flags;
  
  	/*

@@ -683,10 +683,11 @@ intel_engine_has_relative_mmio(const struct 
intel_engine_cs * const engine)
  }
  
  /* Wa_14014475959:dg2 */

+/* Wa_16019325821 */
  static inline bool
-intel_engine_uses_wa_hold_ccs_switchout(struct intel_engine_cs *engine)
+intel_engine_uses_wa_hold_switchout(struct intel_engine_cs *engine)
  {
-   return engine->flags & I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
+   return engine->flags & I915_ENGINE_USES_WA_HOLD_SWITCHOUT;
  }
  
  #endif /* __INTEL_ENGINE_TYPES_H__ */

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 27df41c53b890..4001679ba0793 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -294,6 +294,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
IS_DG2(gt->i915))
flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
  
+	/* Wa_16019325821 */

+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+   flags |= GUC_WA_RCS_CCS_SWITCHOUT;
+
/*
 * Wa_14012197797
 * Wa_22011391025
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index b4d56eccfb1f0..f97af0168a66b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -95,8 +95,9 @@
  #define   GUC_WA_GAM_CREDITS  BIT(10)
  #define   GUC_WA_DUAL_QUEUE   BIT(11)
  #define   GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
-#define   GUC_WA_CONTEXT_ISOLATION BIT(15)
  #define   GUC_WA_PRE_PARSER   BIT(14)
+#define   

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Annotate struct ct_incoming_msg with __counted_by

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Annotate struct ct_incoming_msg with __counted_by
URL   : https://patchwork.freedesktop.org/series/124747/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13723 -> Patchwork_124747v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124747v1/index.html

Participating hosts (40 -> 38)
--

  Missing(2): fi-kbl-soraka fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_124747v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@requests:
- bat-mtlp-8: [PASS][1] -> [ABORT][2] ([i915#9414])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13723/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124747v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#1845])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124747v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][4] -> [ABORT][5] ([i915#8668])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13723/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124747v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@lmem0:
- bat-dg2-9:  [INCOMPLETE][6] ([i915#9275]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13723/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124747v1/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
  [i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414


Build changes
-

  * Linux: CI_DRM_13723 -> Patchwork_124747v1

  CI-20190529: 20190529
  CI_DRM_13723: 2f2f3a5735816736995263c4de4f221480183a99 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7519: d1db7333d9c5fbbb05e50b0804123950d9dc1c46 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_124747v1: 2f2f3a5735816736995263c4de4f221480183a99 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

7b728caadfa5 drm/i915/guc: Annotate struct ct_incoming_msg with __counted_by

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124747v1/index.html

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Create the guc_to_i915() wrapper (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Create the guc_to_i915() wrapper (rev2)
URL   : https://patchwork.freedesktop.org/series/124686/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13722_full -> Patchwork_124686v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_124686v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_124686v2_full, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/index.html

Participating hosts (10 -> 9)
--

  Missing(1): shard-tglu0 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_124686v2_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_eio@in-flight-contexts-1us:
- shard-mtlp: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/shard-mtlp-3/igt@gem_...@in-flight-contexts-1us.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-mtlp-1/igt@gem_...@in-flight-contexts-1us.html

  
New tests
-

  New tests have been introduced between CI_DRM_13722_full and 
Patchwork_124686v2_full:

### New IGT tests (8) ###

  * igt@kms_flip@basic-flip-vs-dpms@a-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_flip@basic-flip-vs-dpms@b-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_flip@basic-flip-vs-dpms@c-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_flip@basic-flip-vs-dpms@d-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@d-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_124686v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@device_reset@unbind-reset-rebind:
- shard-dg1:  NOTRUN -> [INCOMPLETE][3] ([i915#9408])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-dg1-16/igt@device_re...@unbind-reset-rebind.html

  * igt@drm_fdinfo@busy@ccs0:
- shard-dg2:  NOTRUN -> [SKIP][4] ([i915#8414]) +11 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-dg2-10/igt@drm_fdinfo@b...@ccs0.html

  * igt@gem_basic@multigpu-create-close:
- shard-dg1:  NOTRUN -> [SKIP][5] ([i915#7697])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-dg1-17/igt@gem_ba...@multigpu-create-close.html
- shard-tglu: NOTRUN -> [SKIP][6] ([i915#7697])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-tglu-7/igt@gem_ba...@multigpu-create-close.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
- shard-dg2:  [PASS][7] -> [INCOMPLETE][8] ([i915#7297])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/shard-dg2-2/igt@gem_ccs@suspend-res...@linear-compressed-compfmt0-smem-lmem0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-dg2-10/igt@gem_ccs@suspend-res...@linear-compressed-compfmt0-smem-lmem0.html

  * igt@gem_ctx_param@set-priority-not-supported:
- shard-dg2:  NOTRUN -> [SKIP][9] ([fdo#109314])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-dg2-7/igt@gem_ctx_pa...@set-priority-not-supported.html

  * igt@gem_ctx_persistence@heartbeat-close:
- shard-dg2:  NOTRUN -> [SKIP][10] ([i915#8555])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-dg2-5/igt@gem_ctx_persiste...@heartbeat-close.html

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2:  NOTRUN -> [SKIP][11] ([i915#5882]) +9 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-dg2-10/igt@gem_ctx_persistence@saturated-hostile-nopree...@ccs0.html

  * igt@gem_ctx_sseu@mmap-args:
- shard-dg2:  NOTRUN -> [SKIP][12] ([i915#280])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-dg2-10/igt@gem_ctx_s...@mmap-args.html

  * igt@gem_exec_balancer@bonded-pair:
- shard-dg1:  NOTRUN -> [SKIP][13] ([i915#4771])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/shard-dg1-17/igt@gem_exec_balan...@bonded-pair.html

  * 

Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Support new and improved engine busyness

[John Harrison]

On 10/3/2023 13:58, Umesh Nerlige Ramappa wrote:
On Fri, Sep 22, 2023 at 03:25:08PM -0700, john.c.harri...@intel.com 
wrote:

From: John Harrison 

The GuC has been extended to support a much more friendly engine
busyness interface. So partition the old interface into a 'busy_v1'
space and add 'busy_v2' support alongside. And if v2 is available, use
that in preference to v1. Note that v2 provides extra features over
and above v1 which will be exposed via PMU in subsequent patches.


Since we are thinking of using the existing busyness counter to expose 
the v2 values, we can drop the last sentence from above.




Signed-off-by: John Harrison 
---
drivers/gpu/drm/i915/gt/intel_engine_types.h  |   4 +-
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |   4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.h    |  82 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c    |  55 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h    |   9 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  23 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 381 ++
7 files changed, 427 insertions(+), 131 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h

index a7e6775980043..40fd8f984d64b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -323,7 +323,7 @@ struct intel_engine_execlists_stats {
ktime_t start;
};

-struct intel_engine_guc_stats {
+struct intel_engine_guc_stats_v1 {
/**
 * @running: Active state of the engine when busyness was last 
sampled.

 */
@@ -603,7 +603,7 @@ struct intel_engine_cs {
struct {
    union {
    struct intel_engine_execlists_stats execlists;
-    struct intel_engine_guc_stats guc;
+    struct intel_engine_guc_stats_v1 guc_v1;
    };


Overall, I would suggest having the renames as a separate patch. Would 
make the review easier.




    /**
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h

index f359bef046e0b..c190a99a36c38 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -137,7 +137,9 @@ enum intel_guc_action {
INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
-    INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
+    INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF_V1 = 0x550A,
+    INTEL_GUC_ACTION_SET_DEVICE_ENGINE_UTILIZATION_V2 = 0x550C,
+    INTEL_GUC_ACTION_SET_FUNCTION_ENGINE_UTILIZATION_V2 = 0x550D,
INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,
INTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h

index 6c392bad29c19..e6502ab5f049f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -226,45 +226,61 @@ struct intel_guc {
struct mutex send_mutex;

/**
- * @timestamp: GT timestamp object that stores a copy of the 
timestamp

- * and adjusts it for overflow using a worker.
+ * @busy: Data used by the different versions of engine busyness 
implementations.

 */
-    struct {
-    /**
- * @lock: Lock protecting the below fields and the engine 
stats.

- */
-    spinlock_t lock;
-
-    /**
- * @gt_stamp: 64 bit extended value of the GT timestamp.
- */
-    u64 gt_stamp;
-
-    /**
- * @ping_delay: Period for polling the GT timestamp for
- * overflow.
- */
-    unsigned long ping_delay;
-
-    /**
- * @work: Periodic work to adjust GT timestamp, engine and
- * context usage for overflows.
- */
-    struct delayed_work work;
-
+    union {
    /**
- * @shift: Right shift value for the gpm timestamp
+ * @v1: Data used by v1 engine busyness implementation. 
Mostly a copy
+ * of the GT timestamp extended to 64 bits and the worker 
for maintaining it.

 */
-    u32 shift;
+    struct {
+    /**
+ * @lock: Lock protecting the below fields and the 
engine stats.

+ */
+    spinlock_t lock;
+
+    /**
+ * @gt_stamp: 64 bit extended value of the GT timestamp.
+ */
+    u64 gt_stamp;
+
+    /**
+ * @ping_delay: Period for polling the GT timestamp for
+ * overflow.
+ */
+    unsigned long ping_delay;
+
+    /**
+ * @work: Periodic work to adjust GT timestamp, engine and
+ * context usage for overflows.
+ */
+    struct delayed_work work;
+
+    /**
+ * @shift: Right shift value for the gpm timestamp
+  

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Define and use GuC and CTB TLB invalidation routines

[Patchwork]

== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines
URL   : https://patchwork.freedesktop.org/series/124744/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124744v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_124744v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_124744v1, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/index.html

Participating hosts (39 -> 37)
--

  Additional (1): bat-dg2-9 
  Missing(3): bat-adlp-11 fi-snb-2520m fi-pnv-d510 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_124744v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@guc_multi_lrc:
- bat-dg2-11: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-dg2-11/igt@i915_selftest@live@guc_multi_lrc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-11/igt@i915_selftest@live@guc_multi_lrc.html

  
Known issues


  Here are the changes found in Patchwork_124744v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][4] ([i915#4077]) +2 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][6] ([i915#6621])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#5190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#4215] / [i915#5190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#4212]) +6 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([i915#4212] / [i915#5608])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9:  NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9:  NOTRUN -> [SKIP][15] ([i915#5274])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_psr@sprite_plane_onoff:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([i915#1072]) +3 other tests skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124744v1/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#3555])
   [17]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines

[Patchwork]

== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines
URL   : https://patchwork.freedesktop.org/series/124744/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines

[Patchwork]

== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines
URL   : https://patchwork.freedesktop.org/series/124744/
State : warning

== Summary ==

Error: dim checkpatch failed
a989e19c9fa8 drm/i915: Add GuC TLB Invalidation device info flags
b8ea885e3069 drm/i915/guc: Add CT size delay helper
ec7ad50f3bc3 drm/i915: Define and use GuC and CTB TLB invalidation routines
-:411: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to 
using 'fini_tlb_lookup', this function's name, in a string
#411: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2002:
+   guc_dbg(guc, "fini_tlb_lookup: Unexpected item in 
tlb_lookup\n");

total: 0 errors, 1 warnings, 0 checks, 442 lines checked
a71d6627453a drm/i915: No TLB invalidation on suspended GT
9a28bcd71d02 drm/i915: No TLB invalidation on wedged GT
6810984ab8f8 drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
-:23: ERROR:TRAILING_WHITESPACE: trailing whitespace
#23: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:140:
+^I * Short sleep to sanitycheck the batch is spinning before we begin $

-:29: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see 
Documentation/timers/timers-howto.rst
#29: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:146:
+   msleep(10);

total: 1 errors, 1 warnings, 0 checks, 17 lines checked
7ffe5af8a6bd drm/i915: Enable GuC TLB invalidations for MTL

Re: [Intel-gfx] [PATCH 1/2] drm/i915: drop -Wall and related disables from cflags as redundant

[Nick Desaulniers]

On Fri, Oct 6, 2023 at 5:35 AM Jani Nikula  wrote:
>
> The kernel top level Makefile, and recently scripts/Makefile.extrawarn,
> have included -Wall, and the disables -Wno-format-security and
> $(call cc-disable-warning,frame-address,) for a very long time. They're
> redundant in our local subdir-ccflags-y and can be dropped.
>
> Cc: Arnd Bergmann 
> Cc: Nick Desaulniers 
> Cc: Nathan Chancellor 
> Cc: Masahiro Yamada 
> Signed-off-by: Jani Nikula 

I didn't carefully cross reference these specific flags so I provide
and ack rather than RB, but the logic in the description checks out
IMO.

Acked-by: Nick Desaulniers 

> ---
>  drivers/gpu/drm/i915/Makefile | 8 +++-
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index dec78efa452a..623f81217442 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -5,22 +5,20 @@
>
>  # Add a set of useful warning flags and enable -Werror for CI to prevent
>  # trivial mistakes from creeping in. We have to do this piecemeal as we 
> reject
> -# any patch that isn't warning clean, so turning on -Wall -Wextra (or W=1) we
> +# any patch that isn't warning clean, so turning on -Wextra (or W=1) we
>  # need to filter out dubious warnings.  Still it is our interest
>  # to keep running locally with W=1 C=1 until we are completely clean.
>  #
> -# Note the danger in using -Wall -Wextra is that when CI updates gcc we
> +# Note the danger in using -Wextra is that when CI updates gcc we
>  # will most likely get a sudden build breakage... Hopefully we will fix
>  # new warnings before CI updates!
> -subdir-ccflags-y := -Wall -Wextra
> -subdir-ccflags-y += -Wno-format-security
> +subdir-ccflags-y := -Wextra
>  subdir-ccflags-y += -Wno-unused-parameter
>  subdir-ccflags-y += -Wno-type-limits
>  subdir-ccflags-y += -Wno-missing-field-initializers
>  subdir-ccflags-y += -Wno-sign-compare
>  subdir-ccflags-y += -Wno-shift-negative-value
>  subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
> -subdir-ccflags-y += $(call cc-disable-warning, frame-address)
>  subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
>
>  # Fine grained warnings disable
> --
> 2.39.2
>


-- 
Thanks,
~Nick Desaulniers

Re: [Intel-gfx] [PATCH] drm/i915/guc: Annotate struct ct_incoming_msg with __counted_by

[Andi Shyti]

Hi Kees,

On Fri, Oct 06, 2023 at 01:17:45PM -0700, Kees Cook wrote:
> Prepare for the coming implementation by GCC and Clang of the __counted_by
> attribute. Flexible array members annotated with __counted_by can have
> their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
> array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
> functions).
> 
> As found with Coccinelle[1], add __counted_by for struct ct_incoming_msg.
> 
> Cc: Jani Nikula 
> Cc: Joonas Lahtinen 
> Cc: Rodrigo Vivi 
> Cc: Tvrtko Ursulin 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: "Gustavo A. R. Silva" 
> Cc: John Harrison 
> Cc: Matthew Brost 
> Cc: Michal Wajdeczko 
> Cc: Matt Roper 
> Cc: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Cc: linux-harden...@vger.kernel.org
> Link: 
> https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci
>  [1]
> Signed-off-by: Kees Cook 

Reviewed-by: Andi Shyti  

Andi

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Enable WA 14018913170 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Enable WA 14018913170 (rev2)
URL   : https://patchwork.freedesktop.org/series/124694/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124694v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/index.html

Participating hosts (39 -> 39)
--

  Additional (2): fi-kbl-soraka bat-dg2-9 
  Missing(2): bat-adlp-11 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_124694v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0@lmem0:
- bat-dg2-9:  NOTRUN -> [INCOMPLETE][1] ([i915#9275])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3:  [PASS][2] -> [INCOMPLETE][3] ([i915#9275])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][6] ([i915#4083])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_module_load@load:
- bat-adlp-6: [PASS][9] -> [DMESG-WARN][10] ([i915#1982] / 
[i915#8449])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-6/igt@i915_module_l...@load.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-adlp-6/igt@i915_module_l...@load.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#6621])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][12] ([i915#1886])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@requests:
- bat-mtlp-8: [PASS][13] -> [ABORT][14] ([i915#9414])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3:  [PASS][15] -> [FAIL][16] ([fdo#103375])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#5190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#4215] / [i915#5190])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][19] ([i915#4212]) +6 other tests skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][20] ([i915#4212] / [i915#5608])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124694v2/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][21] ([i915#4103] / [i915#4213] / 

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: align with W=1 warnings (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: align with W=1 warnings (rev2)
URL   : https://patchwork.freedesktop.org/series/124718/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/124718/revisions/2/mbox/ not 
applied
Applying: drm/i915: drop -Wall and related disables from cflags as redundant
Applying: drm/i915: enable W=1 warnings by default
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/Makefile
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/Makefile
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/Makefile
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm/i915: enable W=1 warnings by default
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Enable WA 14018913170 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Enable WA 14018913170 (rev2)
URL   : https://patchwork.freedesktop.org/series/124694/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH] drm/i915/guc: Annotate struct ct_incoming_msg with __counted_by

[Gustavo A. R. Silva]

On 10/6/23 22:17, Kees Cook wrote:

Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).

As found with Coccinelle[1], add __counted_by for struct ct_incoming_msg.

Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: "Gustavo A. R. Silva" 
Cc: John Harrison 
Cc: Matthew Brost 
Cc: Michal Wajdeczko 
Cc: Matt Roper 
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Cc: linux-harden...@vger.kernel.org
Link: 
https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci
 [1]
Signed-off-by: Kees Cook 


Reviewed-by: Gustavo A. R. Silva 

Thanks!
--
Gustavo


---
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 6e22af31513a..c33210ead1ef 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -96,7 +96,7 @@ struct ct_request {
  struct ct_incoming_msg {
struct list_head link;
u32 size;
-   u32 msg[];
+   u32 msg[] __counted_by(size);
  };
  
  enum { CTB_SEND = 0, CTB_RECV = 1 };

Re: [Intel-gfx] Regression in linux-next

[Wysocki, Rafael J]

Hi,

On 10/5/2023 5:58 PM, Borah, Chaitanya Kumar wrote:


Hello Rafael,

Hope you are doing well. I am Chaitanya from the linux graphics team 
in Intel.


This mail is regarding a regression we are seeing in our CI runs[1] on 
linux-next repository.



Thanks for the report, I think that this is a lockdep assertion failing.

If that is correct, it should be straightforward to fix.

I'll take care of this early next week.

Thanks!



On next-20231003 [2], we are seeing the following error

```

<4>[ 14.093075] [ cut here ]

<4>[ 14.097664] WARNING: CPU: 0 PID: 1 at 
drivers/thermal/thermal_trip.c:18 for_each_thermal_trip+0x83/0x90


<4>[ 14.106977] Modules linked in:

<4>[ 14.110017] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 
  6.6.0-rc4-next-20231003-next-20231003-gc9f2baaa18b5+ #1


<4>[ 14.121305] Hardware name: Intel Corporation Meteor Lake Client 
Platform/MTL-P DDR5 SODIMM SBS RVP, BIOS 
MTLPFWI1.R00.3323.D89.2309110529 09/11/2023


<4>[ 14.134478] RIP: 0010:for_each_thermal_trip+0x83/0x90

<4>[ 14.139496] Code: 5c 41 5d c3 cc cc cc cc 5b 31 c0 5d 41 5c 41 5d 
c3 cc cc cc cc 48 8d bf f0 05 00 00 be ff ff ff ff e8 21 a2 2d 00 85 
c0 75 9a <0f> 0b eb 96 66 0f 1f 84 00 00 00 00 00 90 90 90 90 90 90 90 
90 90


Details log can be found in [3].

After bisecting the tree, the following patch [4] seems to be causing 
the regression.


commit d5ea889246b112e228433a5f27f57af90ca0c1fb

Author: Rafael J. Wysocki rafael.j.wyso...@intel.com

Date:   Thu Sep 21 20:02:59 2023 +0200

    ACPI: thermal: Do not use trip indices for cooling device binding

    Rearrange the ACPI thermal driver's callback functions used for 
cooling


    device binding and unbinding, acpi_thermal_bind_cooling_device() and

    acpi_thermal_unbind_cooling_device(), respectively, so that they 
use trip


    pointers instead of trip indices which is more straightforward and 
allows


    the driver to become independent of the ordering of trips in the 
thermal


    zone structure.

    The general functionality is not expected to be changed.

    Signed-off-by: Rafael J. Wysocki rafael.j.wyso...@intel.com

    Reviewed-by: Daniel Lezcano daniel.lezc...@linaro.org

We also verified by moving the head of the tree to the previous commit.

Could you please check why this patch causes the regression and if we 
can find a solution for it soon?


[1] https://intel-gfx-ci.01.org/tree/linux-next/combined-alt.html?

[2] 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20231003


[3] 
https://intel-gfx-ci.01.org/tree/linux-next/next-20231003/bat-mtlp-6/boot0.txt


[4] 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20231003=d5ea889246b112e228433a5f27f57af90ca0c1fb 

Re: [Intel-gfx] [PATCH] drm/i915/guc: Update 'recommended' version to 70.12.1 for DG2/ADL-S/ADL-P/MTL

[Andi Shyti]

Hi John,

> The latest GuC has new features and new workarounds that we wish to
> enable. So let the universe know that it is useful to update their
> firmware.
> 
> Signed-off-by: John Harrison 

Reviewed-by: Andi Shyti  

Andi

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Update 'recommended' version to 70.12.1 for DG2/ADL-S/ADL-P/MTL

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Update 'recommended' version to 70.12.1 for 
DG2/ADL-S/ADL-P/MTL
URL   : https://patchwork.freedesktop.org/series/124733/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124733v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/index.html

Participating hosts (39 -> 37)
--

  Additional (1): bat-dg2-9 
  Missing(3): bat-adlp-11 fi-snb-2520m fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_124733v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][1] ([i915#4083])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][2] ([i915#4077]) +2 other tests skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][3] ([i915#4079]) +1 other test skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][4] ([i915#6621])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@requests:
- bat-mtlp-8: [PASS][5] -> [ABORT][6] ([i915#9414])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#5190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#4215] / [i915#5190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#4212]) +6 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#4212] / [i915#5608])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([fdo#109285])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#5274])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#1845])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][15] -> [ABORT][16] ([i915#8668])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html

  * igt@kms_psr@sprite_plane_onoff:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#1072]) +3 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#3555])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124733v1/bat-dg2-9/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
- bat-dg2-9:  NOTRUN -> [SKIP][19] ([i915#3708])
   [19]: 

[Intel-gfx] [PATCH] drm/i915/guc: Annotate struct ct_incoming_msg with __counted_by

[Kees Cook]

Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).

As found with Coccinelle[1], add __counted_by for struct ct_incoming_msg.

Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: "Gustavo A. R. Silva" 
Cc: John Harrison 
Cc: Matthew Brost 
Cc: Michal Wajdeczko 
Cc: Matt Roper 
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Cc: linux-harden...@vger.kernel.org
Link: 
https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci
 [1]
Signed-off-by: Kees Cook 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 6e22af31513a..c33210ead1ef 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -96,7 +96,7 @@ struct ct_request {
 struct ct_incoming_msg {
struct list_head link;
u32 size;
-   u32 msg[];
+   u32 msg[] __counted_by(size);
 };
 
 enum { CTB_SEND = 0, CTB_RECV = 1 };
-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.BAT: success for Trim some pre-production code (rev2)

[Patchwork]

== Series Details ==

Series: Trim some pre-production code (rev2)
URL   : https://patchwork.freedesktop.org/series/124705/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124705v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/index.html

Participating hosts (39 -> 38)
--

  Additional (1): bat-dg2-9 
  Missing(2): bat-adlp-11 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_124705v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-hsw-4770:[PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-hsw-4770/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@smem:
- bat-mtlp-8: [PASS][3] -> [ABORT][4] ([i915#8213] / [i915#9262])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#5190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#4215] / [i915#5190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#4212]) +6 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([i915#4212] / [i915#5608])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9:  NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9:  NOTRUN -> [SKIP][15] ([i915#5274])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_psr@sprite_plane_onoff:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([i915#1072]) +3 other tests skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#3555])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#3708])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@prime_v...@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
- bat-dg2-9:  NOTRUN -> [SKIP][19] ([i915#3708] / [i915#4077]) +1 
other test skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v2/bat-dg2-9/igt@prime_v...@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
- bat-dg2-9:   

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Remove xehpsdv support

[Andrzej Hajda]

On 06.10.2023 10:31, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

XeHP SDV was a pre-production hardware used to bring up ATS and was not
generally available. Since latter was since explicitly added, there is no
need to keep the code for the former around.

Signed-off-by: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/gt/intel_gsc.c | 15 
  drivers/gpu/drm/i915/gt/intel_gt_mcr.c  | 16 
  drivers/gpu/drm/i915/gt/intel_gt_regs.h |  1 -
  drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 20 ++---
  drivers/gpu/drm/i915/gt/intel_mocs.c| 31 ---
  drivers/gpu/drm/i915/gt/intel_rps.c |  4 +-
  drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 -
  drivers/gpu/drm/i915/gt/uc/intel_uc.c   |  4 -
  drivers/gpu/drm/i915/i915_drv.h |  4 -
  drivers/gpu/drm/i915/i915_hwmon.c   |  6 --
  drivers/gpu/drm/i915/i915_pci.c | 17 
  drivers/gpu/drm/i915/i915_perf.c|  4 +-
  drivers/gpu/drm/i915/i915_reg.h |  1 -
  drivers/gpu/drm/i915/intel_clock_gating.c   | 10 ---
  drivers/gpu/drm/i915/intel_device_info.c|  1 -
  drivers/gpu/drm/i915/intel_device_info.h|  1 -
  drivers/gpu/drm/i915/intel_step.c   | 10 ---
  17 files changed, 8 insertions(+), 232 deletions(-)


Reviewed-by: Andrzej Hajda 

Regards
Andrzej

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Remove incomplete PVC plumbing

[Andrzej Hajda]

On 06.10.2023 10:31, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

PVC support will not be coming to i915 so get rid of its partial
enablement and reduce the driver maintenance burden.

Signed-off-by: Tvrtko Ursulin 
---
  .../gpu/drm/i915/gem/i915_gem_object_types.h  |   2 +-
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |   3 -
  drivers/gpu/drm/i915/gt/intel_gt_mcr.c|  31 +---
  drivers/gpu/drm/i915/gt/intel_mocs.c  |  19 ---
  drivers/gpu/drm/i915/gt/intel_rps.c   |   4 +-
  drivers/gpu/drm/i915/gt/intel_sseu.c  |   9 +-
  drivers/gpu/drm/i915/gt/intel_workarounds.c   |  81 +-
  drivers/gpu/drm/i915/gt/uc/intel_uc.c |   4 +-
  drivers/gpu/drm/i915/i915_debugfs.c   |  12 --
  drivers/gpu/drm/i915/i915_drv.h   |   9 --
  drivers/gpu/drm/i915/i915_pci.c   |  35 -
  drivers/gpu/drm/i915/i915_reg.h   |   1 -
  drivers/gpu/drm/i915/intel_clock_gating.c |  16 +-
  drivers/gpu/drm/i915/intel_device_info.c  |   1 -
  drivers/gpu/drm/i915/intel_device_info.h  |   1 -
  drivers/gpu/drm/i915/intel_step.c |  70 +
  drivers/gpu/drm/i915/intel_uncore.c   | 142 --
  drivers/gpu/drm/i915/selftests/intel_uncore.c |   2 -
  18 files changed, 10 insertions(+), 432 deletions(-)


Nice diffstat.
Reviewed-by: Andrzej Hajda 

Regards
Andrzej

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Remove early/pre-production Haswell code

[Andrzej Hajda]

On 06.10.2023 10:31, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

It is not our policy to keep pre-production hardware support for this long
so I guess this one was just forgotten.

Signed-off-by: Tvrtko Ursulin 


Reviewed-by: Andrzej Hajda 

Regards
Andrzej


---
  drivers/gpu/drm/i915/i915_driver.c | 1 -
  drivers/gpu/drm/i915/i915_drv.h| 2 --
  2 files changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index ccbb2834cde0..78a42c8a8509 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -175,7 +175,6 @@ static void intel_detect_preproduction_hw(struct 
drm_i915_private *dev_priv)
  {
bool pre = false;
  
-	pre |= IS_HASWELL_EARLY_SDV(dev_priv);

pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb60fc9cf873..9d493ff1685a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -590,8 +590,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
  #define IS_RAPTORLAKE_U(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
-#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
-   (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
  #define IS_BROADWELL_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
  #define IS_BROADWELL_ULX(i915) \

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Trim some pre-production code (rev2)

[Patchwork]

== Series Details ==

Series: Trim some pre-production code (rev2)
URL   : https://patchwork.freedesktop.org/series/124705/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add wrapper for getiing display step (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Add wrapper for getiing display step (rev3)
URL   : https://patchwork.freedesktop.org/series/124340/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124340v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124340v3/index.html

Participating hosts (39 -> 37)
--

  Additional (1): fi-kbl-soraka 
  Missing(3): bat-adlp-11 fi-snb-2520m fi-bsw-n3050 

Known issues


  Here are the changes found in Patchwork_124340v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124340v3/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124340v3/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][3] ([i915#5334] / [i915#7872])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124340v3/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][4] ([i915#1886])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124340v3/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_dsc@dsc-basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271]) +9 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124340v3/fi-kbl-soraka/igt@kms_...@dsc-basic.html

  
 Possible fixes 

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][6] ([IGT#3]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124340v3/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
  [i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952


Build changes
-

  * Linux: CI_DRM_13722 -> Patchwork_124340v3

  CI-20190529: 20190529
  CI_DRM_13722: ead693ec2d2fddb30bff4718845d42f9adabcce6 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7518: 2d4a57e28db0c2ccbf8b2e763074c9aa74a1ae52 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_124340v3: ead693ec2d2fddb30bff4718845d42f9adabcce6 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

fcfe6887c067 drm/i915: Add wrapper for getting display step

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124340v3/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Add wrapper for getiing display step (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Add wrapper for getiing display step (rev3)
URL   : https://patchwork.freedesktop.org/series/124340/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [bug report] drm/i915: Move submission tasklet to i915_sched_engine

[John Harrison]

Tvrtko, would you have any thoughts on this one?

John.


On 10/4/2023 02:57, Dan Carpenter wrote:

Hello Matthew Brost,

This is a semi-automatic email about new static checker warnings.

The patch 22916bad07a5: "drm/i915: Move submission tasklet to
i915_sched_engine" from Jun 17, 2021, leads to the following Smatch
complaint:

 drivers/gpu/drm/i915/gt/intel_execlists_submission.c:3659 
rcu_virtual_context_destroy()
 warn: variable dereferenced before check 've->base.sched_engine' (see line 
3633)

drivers/gpu/drm/i915/gt/intel_execlists_submission.c
   3632  */
   3633 tasklet_kill(>base.sched_engine->tasklet);
  ^^^
The patch introduced a new dereference here

   3634 
   3635 /* Decouple ourselves from the siblings, no more access 
allowed. */
   3636 for (n = 0; n < ve->num_siblings; n++) {
   3637 struct intel_engine_cs *sibling = ve->siblings[n];
   3638 struct rb_node *node = >nodes[sibling->id].rb;
   3639 
   3640 if (RB_EMPTY_NODE(node))
   3641 continue;
   3642 
   3643 spin_lock_irq(>sched_engine->lock);
   3644 
   3645 /* Detachment is lazily performed in the 
sched_engine->tasklet */
   3646 if (!RB_EMPTY_NODE(node))
   3647 rb_erase_cached(node, 
>execlists.virtual);
   3648 
   3649 spin_unlock_irq(>sched_engine->lock);
   3650 }
   3651 
GEM_BUG_ON(__tasklet_is_scheduled(>base.sched_engine->tasklet));
   3652 GEM_BUG_ON(!list_empty(virtual_queue(ve)));
   3653 
   3654 lrc_fini(>context);
   3655 intel_context_fini(>context);
   3656 
   3657 if (ve->base.breadcrumbs)
   3658 intel_breadcrumbs_put(ve->base.breadcrumbs);
   3659 if (ve->base.sched_engine)
 ^
But previous code had assumed the sched_engine could be NULL.

   3660 i915_sched_engine_put(ve->base.sched_engine);
   3661 intel_engine_free_request_pool(>base);

regards,
dan carpenter

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Add bigjoiner force enable option to debugfs

[Patchwork]

== Series Details ==

Series: drm/i915: Add bigjoiner force enable option to debugfs
URL   : https://patchwork.freedesktop.org/series/124730/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124730v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_124730v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_124730v1, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/index.html

Participating hosts (39 -> 38)
--

  Additional (1): fi-kbl-soraka 
  Missing(2): bat-adlp-6 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_124730v1:

### IGT changes ###

 Possible regressions 

  * igt@debugfs_test@read_all_entries:
- bat-adlp-11:[PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-11/igt@debugfs_test@read_all_entries.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/bat-adlp-11/igt@debugfs_test@read_all_entries.html

  * igt@i915_module_load@load:
- fi-ilk-650: [PASS][3] -> [ABORT][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-ilk-650/igt@i915_module_l...@load.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/fi-ilk-650/igt@i915_module_l...@load.html
- fi-blb-e6850:   [PASS][5] -> [ABORT][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-blb-e6850/igt@i915_module_l...@load.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/fi-blb-e6850/igt@i915_module_l...@load.html
- fi-pnv-d510:[PASS][7] -> [ABORT][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-pnv-d510/igt@i915_module_l...@load.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/fi-pnv-d510/igt@i915_module_l...@load.html
- fi-elk-e7500:   [PASS][9] -> [ABORT][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-elk-e7500/igt@i915_module_l...@load.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/fi-elk-e7500/igt@i915_module_l...@load.html
- fi-hsw-4770:[PASS][11] -> [ABORT][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-hsw-4770/igt@i915_module_l...@load.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/fi-hsw-4770/igt@i915_module_l...@load.html
- fi-ivb-3770:[PASS][13] -> [ABORT][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-ivb-3770/igt@i915_module_l...@load.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/fi-ivb-3770/igt@i915_module_l...@load.html

  
Known issues


  Here are the changes found in Patchwork_124730v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][17] ([i915#1886])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_dsc@dsc-basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][18] ([fdo#109271]) +9 other tests 
skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/fi-kbl-soraka/igt@kms_...@dsc-basic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#1845]) +1 other test skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124730v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613


Build changes

Re: [Intel-gfx] [PATCH v7 2/5] drm/i915: Define and use GuC and CTB TLB invalidation routines

[Cavitt, Jonathan]

As far as I can tell, most if not all of the below comments
have now been addressed in version 8.  Please check to
verify this is correct.
-Jonathan Cavitt

-Original Message-
From: Tvrtko Ursulin  
Sent: Friday, October 6, 2023 6:05 AM
To: Cavitt, Jonathan ; 
intel-gfx@lists.freedesktop.org
Cc: Dutt, Sudeep ; Chang, Yu bruce 
; chris.p.wil...@linux.intel.com; Iddamsetty, Aravind 
; Yang, Fei ; Shyti, Andi 
; Harrison, John C ; Das, 
Nirmoy ; Krzysztofik, Janusz 
; Roper, Matthew D ; 
jani.nik...@linux.intel.com
Subject: Re: [PATCH v7 2/5] drm/i915: Define and use GuC and CTB TLB 
invalidation routines
> 
> 
> On 06/10/2023 11:11, Tvrtko Ursulin wrote:
> > 
> > Hi,
> > 
> > 
> > Andi asked me to summarize what I think is unaddressed review feedback 
> > so far in order to consolidate and enable hopefully things to move 
> > forward. So I will try to re-iterate the comments and questions below.
> > 
> > But also note that there is a bunch of new valid comments from John 
> > against v7 which I will not repeat.
> > 
> > On 05/10/2023 20:35, Jonathan Cavitt wrote:
> >> From: Prathap Kumar Valsan 
> >>
> >> The GuC firmware had defined the interface for Translation Look-Aside
> >> Buffer (TLB) invalidation.  We should use this interface when
> >> invalidating the engine and GuC TLBs.
> >> Add additional functionality to intel_gt_invalidate_tlb, invalidating
> >> the GuC TLBs and falling back to GT invalidation when the GuC is
> >> disabled.
> >> The invalidation is done by sending a request directly to the GuC
> >> tlb_lookup that invalidates the table.  The invalidation is submitted as
> >> a wait request and is performed in the CT event handler.  This means we
> >> cannot perform this TLB invalidation path if the CT is not enabled.
> >> If the request isn't fulfilled in two seconds, this would constitute
> >> an error in the invalidation as that would constitute either a lost
> >> request or a severe GuC overload.
> >> The tlb_lookup table is allocated as an xarray because the set of
> >> pending TLB invalidations may have no upper bound.  The consequence of
> >> this is that all actions interfacing with this table need to use the
> >> xarray functions, such as xa_alloc_cyclic_irq for array insertion.
> >>
> >> With this new invalidation routine, we can perform GuC-based GGTT
> >> invalidations.  GuC-based GGTT invalidation is incompatible with
> >> MMIO invalidation so we should not perform MMIO invalidation when
> >> GuC-based GGTT invalidation is expected.
> > 
> > On the commit message, I was asking that it describes the justification 
> > for the complexity patch adds with the wait queue management. It is 
> > non-trivial code, open-coded-almost-copy-of wait_token(), etc, so it 
> > needs explanation.
> > 
> > Today we have all threads serialize their invalidation under 
> > gt->tlb.invalidate_lock. With this patch that remains, but it allows a 
> > little bit of de-serialization in waiting. I suspect this is because 
> > with mmio i915 has direct access to invalidation, where with GuC the 
> > requests are competing for latency with other CT requests too (not 
> > invalidations).
> > 
> > Simpler patch could be doing the same as the GFP_ATOMIC fallback path in 
> > guc_send_invalidate_tlb - ie. serialize it all against one CT 
> > invalidation "slot". Are the gains of allowing multiple wait slots 
> > significant enough to warrant the complexity etc needs to be documented 
> > and the above problem space explained in the commit message.
> 
> Also, any gains from the invidual waiters are limited to 
> ggtt->invalidate() callers right? Because the put_pages invalidations 
> are serialized at the top-level in intel_gt_invalidate_tlb_full() anyway.
> 
> And how frequent or relevant are ggtt invalidations at runtime? It is 
> just context creation and such, no (rings, contexts state)? Are page 
> flips / framebuffers relevant too?
> 
> Question is whether a simpler scheme, with a single wait queue (no open 
> coded wait_token(), xarray etc) and just waking up all waiters on 
> processing CT done, where each waiters check the seqno and goes back to 
> sleep if it's invalidation hasn't been completed yet, would be sufficient.
> 
> Regards,
> 
> Tvrtko
> 
> > 
> >> Signed-off-by: Prathap Kumar Valsan 
> >> Signed-off-by: Bruce Chang 
> >> Signed-off-by: Chris Wilson 
> >> Signed-off-by: Umesh Nerlige Ramappa 
> >> Signed-off-by: Jonathan Cavitt 
> >> Signed-off-by: Aravind Iddamsetty 
> >> Signed-off-by: Fei Yang 
> >> CC: Andi Shyti 
> >> ---
> >>   drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 ++-
> >>   drivers/gpu/drm/i915/gt/intel_tlb.c   |  14 +-
> >>   .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 +++
> >>   drivers/gpu/drm/i915/gt/uc/intel_guc.h    |  22 ++
> >>   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
> >>   drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
> >>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 211 +-
> >>   7 files 

[Intel-gfx] [PATCH v8 6/7] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck

[Jonathan Cavitt]

For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.

Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c 
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 7e41f69fc818f..8c3bb9893dae8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -136,8 +136,15 @@ pte_tlbinv(struct intel_context *ce,
i915_request_get(rq);
i915_request_add(rq);
 
-   /* Short sleep to sanitycheck the batch is spinning before we begin */
-   msleep(10);
+   /*
+* Short sleep to sanitycheck the batch is spinning before we begin 
+* FIXME: Why is GSC so slow?
+*/
+   if (ce->engine->class == OTHER_CLASS)
+   msleep(200);
+   else
+   msleep(10);
+
if (va == vb) {
if (!i915_request_completed(rq)) {
pr_err("%s(%s): Semaphore sanitycheck failed %llx, with 
alignment %llx, using PTE size %x (phys %x, sg %x)\n",
-- 
2.25.1

[Intel-gfx] [PATCH v8 3/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

[Jonathan Cavitt]

From: Prathap Kumar Valsan 

The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation.  We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back to GT invalidation when the GuC is
disabled.
The invalidation is done by sending a request directly to the GuC
tlb_lookup that invalidates the table.  The invalidation is submitted as
a wait request and is performed in the CT event handler.  This means we
cannot perform this TLB invalidation path if the CT is not enabled.
If the request isn't fulfilled in two seconds, this would constitute
an error in the invalidation as that would constitute either a lost
request or a severe GuC overload.

With this new invalidation routine, we can perform GuC-based GGTT
invalidations.  GuC-based GGTT invalidation is incompatible with
MMIO invalidation so we should not perform MMIO invalidation when
GuC-based GGTT invalidation is expected.

Purpose of xarray:
The tlb_lookup table is allocated as an xarray because the set of
pending TLB invalidations may have no upper bound.  The consequence of
this is that all actions interfacing with this table need to use the
xarray functions, such as xa_alloc_cyclic_irq for array insertion.

Purpose of must_wait_woken:
Our wait for the G2H ack for the completion of a TLB invalidation is
mandatory; we must wait for the HW to confirm that the physical
addresses are no longer accessible before we return those to the system.

On switching to using the wait_woken() convenience routine, we
introduced ourselves to an issue where wait_woken() may complete early
under a kthread that is stopped. Since we send a TLB invalidation when
we try to release pages from the shrinker, we can be called from any
process; including kthreads.

Using wait_woken() from any process context causes another issue. The
use of is_kthread_should_stop() assumes that any task with PF_KTHREAD
set was made by kthread_create() and has called set_kthread_struct().
This is not true for the raw kernel_thread():

BUG: kernel NULL pointer dereference, address: 
[ 3089.759660] Call Trace:
[ 3089.762110]  wait_woken+0x4f/0x80
[ 3089.765496]  guc_send_invalidate_tlb+0x1fe/0x310 [i915]
[ 3089.770725]  ? syscall_return_via_sysret+0xf/0x7f
[ 3089.775426]  ? do_wait_intr_irq+0xb0/0xb0
[ 3089.779430]  ? __switch_to_asm+0x40/0x70
[ 3089.783349]  ? __switch_to_asm+0x34/0x70
[ 3089.787273]  ? __switch_to+0x7a/0x3e0
[ 3089.790930]  ? __switch_to_asm+0x34/0x70
[ 3089.794883]  intel_guc_invalidate_tlb_full+0x92/0xa0 [i915]
[ 3089.800487]  intel_invalidate_tlb_full+0x94/0x190 [i915]
[ 3089.805824]  intel_invalidate_tlb_full_sync+0x1b/0x30 [i915]
[ 3089.811508]  __i915_gem_object_unset_pages+0x138/0x150 [i915]
[ 3089.817279]  __i915_gem_object_put_pages+0x25/0x90 [i915]
[ 3089.822706]  i915_gem_shrink+0x532/0x7e0 [i915]
[ 3089.827264]  i915_gem_shrinker_scan+0x3d/0xd0 [i915]
[ 3089.832230]  do_shrink_slab+0x12c/0x2a0
[ 3089.836065]  shrink_slab+0xad/0x2b0
[ 3089.839550]  shrink_node+0xcc/0x410
[ 3089.843035]  do_try_to_free_pages+0xc6/0x380
[ 3089.847306]  try_to_free_pages+0xec/0x1c0
[ 3089.851312]  __alloc_pages_slowpath+0x3ad/0xd10
[ 3089.855845]  ? update_sd_lb_stats+0x636/0x710
[ 3089.860204]  __alloc_pages_nodemask+0x2d5/0x310
[ 3089.864737]  new_slab+0x265/0xa80
[ 3089.868053]  ___slab_alloc+0y_to_free_pages+0xec/0x1c0
[ 3089.871798]  ? copy_process+0x1e5/0x1a00
[ 3089.875717]  ? load_balance+0x165/0xb20
[ 3089.879555]  __slab_alloc+0x1c/0x30
[ 3089.883047]  kmem_cache_alloc_node+0x9f/0x240
[ 3089.887397]  ? copy_process+0x1e5/0x1a00
[ 3089.891314]  copy_process+0x1e5/0x1a00
[ 3089.895058]  ? __switch_to_asm+0x40/0x70
[ 3089.879555]  __slab_alloc+0x1c/0x30
[ 3089.883047]  kmem_cache_alloc_node+0x9f/0x240
[ 3089.887397]  ? copy_process+0x1e5/0x1a00
[ 3089.891314]  copy_process+0x1e5/0x1a00
[ 3089.895058]  ? __switch_to_asm+0x40/0x70
[ 3089.898977]  ? __switch_to_asm+0x34/0x70
[ 3089.902903]  ? __switch_to_asm+0x40/0x70
[ 3089.906828]  ? __switch_to_asm+0x34/0x70
[ 3089.910745]  _do_fork+0x83/0x350
[ 3089.913969]  ? __switch_to+0x7a/0x3e0
[ 3089.917626]  ? __switch_to_asm+0x34/0x70
[ 3089.921545]  kernel_thread+0x58/0x80
[ 3089.925124]  ? kthread_park+0x80/0x80
[ 3089.928788]  kthreadd+0x162/0x1b0
[ 3089.932098]  ? kthread_create_on_cpu+0xa0/0xa0
[ 3089.936538]  ret_from_fork+0x1f/0x40

Signed-off-by: Prathap Kumar Valsan 
Signed-off-by: Bruce Chang 
Signed-off-by: Chris Wilson 
Signed-off-by: Umesh Nerlige Ramappa 
Signed-off-by: Jonathan Cavitt 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Fei Yang 
CC: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 ++-
 drivers/gpu/drm/i915/gt/intel_tlb.c   |  15 +-
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  22 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
 

[Intel-gfx] [PATCH v8 7/7] drm/i915: Enable GuC TLB invalidations for MTL

[Jonathan Cavitt]

Enable GuC TLB invalidations for MTL.  Though more platforms than just
MTL support GuC TLB invalidations, MTL is presently the only platform
that requires it for any purpose, so only enable it there for now to
minimize cross-platform impact.

Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index df7c261410f79..d4b51ececbb12 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -829,6 +829,7 @@ static const struct intel_device_info mtl_info = {
.has_flat_ccs = 0,
.has_gmd_id = 1,
.has_guc_deprivilege = 1,
+   .has_guc_tlb_invalidation = 1,
.has_llc = 0,
.has_mslice_steering = 0,
.has_snoop = 1,
-- 
2.25.1

[Intel-gfx] [PATCH v8 2/7] drm/i915/guc: Add CT size delay helper

[Jonathan Cavitt]

Add a helper function to the GuC CT buffer that reports the expected
time to process all outstanding requests.  As of now, there is no
functionality to check number of requests in the buffer, so the helper
function just reports 2 seconds, or 1ms per request up to the maximum
number of requests the CT buffer can store.

Suggested-by: John Harrison 
Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 58e42901ff498..36afc1ce9fabd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -120,6 +120,19 @@ static inline bool intel_guc_ct_enabled(struct 
intel_guc_ct *ct)
return ct->enabled;
 }
 
+/*
+ * GuC has a timeout of 1ms for a TLB invalidation response from GAM.  On a
+ * timeout GuC drops the request and has no mechanism to notify the host about
+ * the timeout.  There is also no mechanism for determining the number of
+ * outstanding requests in the CT buffer.  Ergo, keep a larger timeout that 
accounts
+ * for this individual timeout and the max number of outstanding requests that
+ * can be queued in CT buffer.
+ */
+static inline long intel_guc_ct_expected_delay(struct intel_guc_ct *ct)
+{
+   return HZ * 2;
+}
+
 #define INTEL_GUC_CT_SEND_NB   BIT(31)
 #define INTEL_GUC_CT_SEND_G2H_DW_SHIFT 0
 #define INTEL_GUC_CT_SEND_G2H_DW_MASK  (0xff << INTEL_GUC_CT_SEND_G2H_DW_SHIFT)
-- 
2.25.1

[Intel-gfx] [PATCH v8 5/7] drm/i915: No TLB invalidation on wedged GT

[Jonathan Cavitt]

It is not an error for GuC TLB invalidations to fail when the GT is
wedged or disabled, so do not process a wait failure as one in
guc_send_invalidate_tlb.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 4ed6e9e759007..ddb3115715e41 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -32,6 +32,7 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "i915_irq.h"
 #include "i915_trace.h"
 
 /**
@@ -4759,6 +4760,14 @@ static long must_wait_woken(struct wait_queue_entry 
*wq_entry, long timeout)
return timeout;
 }
 
+static bool intel_gt_is_enabled(const struct intel_gt *gt)
+{
+   /* Check if GT is wedged or suspended */
+   if (intel_gt_is_wedged(gt) || !intel_irqs_enabled(gt->i915))
+   return false;
+   return true;
+}
+
 static int guc_send_invalidate_tlb(struct intel_guc *guc, enum 
intel_guc_tlb_inval_mode type)
 {
struct intel_guc_tlb_wait _wq, *wq = &_wq;
@@ -4810,7 +4819,8 @@ static int guc_send_invalidate_tlb(struct intel_guc *guc, 
enum intel_guc_tlb_inv
if (err)
goto out;
 
-   if (!must_wait_woken(, intel_guc_ct_expected_delay(>ct))) {
+   if (intel_gt_is_enabled(guc_to_gt(guc)) &&
+   !must_wait_woken(, intel_guc_ct_expected_delay(>ct))) {
guc_err(guc,
"TLB invalidation response timed out for seqno %u\n", 
seqno);
err = -ETIME;
-- 
2.25.1

[Intel-gfx] [PATCH v8 4/7] drm/i915: No TLB invalidation on suspended GT

[Jonathan Cavitt]

In case of GT is suspended, don't allow submission of new TLB invalidation
request and cancel all pending requests. The TLB entries will be
invalidated either during GuC reload or on system resume.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
---
 drivers/gpu/drm/i915/gt/intel_gt.h|  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 23 +++
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  8 +++
 drivers/gpu/drm/i915/i915_driver.c|  2 ++
 5 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 970bedf6b78a7..4e3bb221d2f4d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -179,4 +179,5 @@ enum i915_map_type intel_gt_coherent_map_type(struct 
intel_gt *gt,
 void intel_gt_bind_context_set_ready(struct intel_gt *gt);
 void intel_gt_bind_context_set_unready(struct intel_gt *gt);
 bool intel_gt_is_bind_context_ready(struct intel_gt *gt);
+
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 88deb43bbdc48..add74000e621e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -536,4 +536,5 @@ void intel_guc_dump_time_info(struct intel_guc *guc, struct 
drm_printer *p);
 
 int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc);
 
+void wake_up_all_tlb_invalidate(struct intel_guc *guc);
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0c5ccda1b3e87..4ed6e9e759007 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1796,13 +1796,23 @@ static void __guc_reset_context(struct intel_context 
*ce, intel_engine_mask_t st
intel_context_put(parent);
 }
 
-void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
stalled)
+void wake_up_all_tlb_invalidate(struct intel_guc *guc)
 {
struct intel_guc_tlb_wait *wait;
+   unsigned long i;
+
+   if (!HAS_GUC_TLB_INVALIDATION(guc_to_gt(guc)->i915))
+   return;
+   xa_for_each(>tlb_lookup, i, wait) {
+   wake_up(>wq);
+   }
+}
+
+void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
stalled)
+{
struct intel_context *ce;
unsigned long index;
unsigned long flags;
-   unsigned long i;
 
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
@@ -1838,8 +1848,7 @@ void intel_guc_submission_reset(struct intel_guc *guc, 
intel_engine_mask_t stall
 * invalidations on GT reset, and there's a large window of time
 * between the GT reset and GuC becoming available.
 */
-   xa_for_each(>tlb_lookup, i, wait)
-   wake_up(>wq);
+   wake_up_all_tlb_invalidate(guc);
 }
 
 static void guc_cancel_context_requests(struct intel_context *ce)
@@ -1935,6 +1944,12 @@ void intel_guc_submission_cancel_requests(struct 
intel_guc *guc)
 
/* GuC is blown away, drop all references to contexts */
xa_destroy(>context_lookup);
+
+   /*
+* Wedged GT won't respond to any TLB invalidation request. Simply
+* release all the blocked waiters.
+*/
+   wake_up_all_tlb_invalidate(guc);
 }
 
 void intel_guc_submission_reset_finish(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 98b103375b7ab..8d6a4d8ce61bb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -688,6 +688,9 @@ void intel_uc_suspend(struct intel_uc *uc)
/* flush the GSC worker */
intel_gsc_uc_flush_work(>gsc);
 
+   if (HAS_GUC_TLB_INVALIDATION(guc_to_gt(guc)->i915))
+   wake_up_all_tlb_invalidate(guc);
+
if (!intel_guc_is_ready(guc)) {
guc->interrupts.enabled = false;
return;
@@ -736,6 +739,11 @@ static int __uc_resume(struct intel_uc *uc, bool 
enable_communication)
 
intel_gsc_uc_resume(>gsc);
 
+   if (HAS_GUC_TLB_INVALIDATION(gt->i915)) {
+   intel_guc_invalidate_tlb_engines(guc);
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index ccbb2834cde07..85ac9400c2dc7 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -72,6 +72,7 @@
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_rc6.h"
+#include "gt/intel_tlb.h"
 
 #include "pxp/intel_pxp.h"
 #include "pxp/intel_pxp_debugfs.h"
@@ -1093,6 +1094,7 @@ static int i915_drm_suspend(struct 

[Intel-gfx] [PATCH v8 1/7] drm/i915: Add GuC TLB Invalidation device info flags

[Jonathan Cavitt]

Add device info flags for if GuC TLB Invalidation is enabled.

Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/i915_drv.h  | 3 ++-
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb60fc9cf8737..b7933e1120aa7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -794,11 +794,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_GUC_DEPRIVILEGE(i915) \
(INTEL_INFO(i915)->has_guc_deprivilege)
 
+#define HAS_GUC_TLB_INVALIDATION(i915) 
(INTEL_INFO(i915)->has_guc_tlb_invalidation)
+
 #define HAS_3D_PIPELINE(i915)  (INTEL_INFO(i915)->has_3d_pipeline)
 
 #define HAS_ONE_EU_PER_FUSE_BIT(i915)  
(INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
 
 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
   GRAPHICS_VER_FULL(i915) >= IP_VER(12, 
70))
-
 #endif
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 39817490b13fd..eba2f0b919c87 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
func(has_heci_pxp); \
func(has_heci_gscfi); \
func(has_guc_deprivilege); \
+   func(has_guc_tlb_invalidation); \
func(has_l3_ccs_read); \
func(has_l3_dpf); \
func(has_llc); \
-- 
2.25.1

[Intel-gfx] [PATCH v8 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

[Jonathan Cavitt]

Implement GuC-based TLB invalidations and use them on MTL.

v2:
- Add missing supporting patches.

v3:
- Split suspend/resume changes and multi-gt support into separate
  patches.
- Only perform GuC TLB invalidation functions when supported.
- Move intel_guc_is_enabled check function to usage location.
- Address comments.

v4:
- Change conditions for GuC-based tlb invalidation support
  to a pci tag that's only active for MTL.
- Address some FIXMEs and formatting issues.
- Move suspend/resume changes to helper functions in intel_gt.h
- Improve comment for ct_handle_event change.
- Use cleaner if-else conditions.
- Address comments.

v5:
- Reintroduce missing change to selftest msleep duration
- Move suspend/resume loops from intel_gt.h to intel_tlb.c,
  making them no longer static inlines.
- Remove superfluous blocking and error checks.
- Move ct_handle_event exception to general case in
  ct_process_request.
- Explain usage of xa_alloc_cyclic_irq.
- Modify explanation of purpose of
  OUTSTANDING_GUC_TIMEOUT_PERIOD macro.
- Explain purpose of performing tlb invalidation twice in
  intel_gt_tlb_resume_all.

v6:
- Add this cover letter.
- Fix explanation of purpose of
  OUTSTANDING_GUC_TIMEOUT_PERIOD macro again.
- s/pci tags/pci flags
- Enable GuC TLB Invalidations separately from adding the
  flags to do so.

v7:
- Eliminate pci terminology from patches.
- Order new device info flag correctly.
- Run gen8_ggtt_invalidate in more cases, specifically when
  GuC-based TLB invalidation is not supported.
- Use intel_uncore_write_fw instead of intel_uncore_write
  during guc_ggtt_invalidate.
- Remove duplicate request message clear in ct_process_request.
- Remove faulty tag from series.

v8:
- Simplify cover letter contents.
- Fix miscellaneous formatting and typos.
- Reorder device info flags and defines.
- Reword commit message.
- Rename TLB invalidation enums and functions.
- Add comments explaining confusing points.
- Add helper function getting expected delay of CT buffer.
- Simplify intel_guc_tlb_invalidation_done by passing computed
  values.
- Remove helper functions for tlb suspend and resume.
- Move tlb suspend and resume paths to uc.
- Split suspend/resume and wedged into two patches.
- Clarify purpose of sleep change in tlb selftest.

Jonathan Cavitt (6):
  drm/i915: Add GuC TLB Invalidation device info flags
  drm/i915/guc: Add CT size delay helper
  drm/i915: No TLB invalidation on suspended GT
  drm/i915: No TLB invalidation on wedged GT
  drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
  drm/i915: Enable GuC TLB invalidations for MTL

Prathap Kumar Valsan (1):
  drm/i915: Define and use GuC and CTB TLB invalidation routines

 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 ++-
 drivers/gpu/drm/i915/gt/intel_gt.h|   1 +
 drivers/gpu/drm/i915/gt/intel_tlb.c   |  15 +-
 drivers/gpu/drm/i915/gt/selftest_tlb.c|  11 +-
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  23 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  13 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 225 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |   8 +
 drivers/gpu/drm/i915/i915_driver.c|   2 +
 drivers/gpu/drm/i915/i915_drv.h   |   3 +-
 drivers/gpu/drm/i915/i915_pci.c   |   1 +
 drivers/gpu/drm/i915/intel_device_info.h  |   1 +
 15 files changed, 360 insertions(+), 15 deletions(-)

-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Store DSC DPCD capabilities in the connector

[Patchwork]

== Series Details ==

Series: drm/i915: Store DSC DPCD capabilities in the connector
URL   : https://patchwork.freedesktop.org/series/124723/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124723v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/index.html

Participating hosts (39 -> 38)
--

  Additional (1): bat-dg2-9 
  Missing(2): fi-snb-2520m fi-bsw-n3050 

Known issues


  Here are the changes found in Patchwork_124723v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-hsw-4770:[PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-hsw-4770/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3:  [PASS][3] -> [INCOMPLETE][4] ([i915#9275])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
- bat-mtlp-8: [PASS][5] -> [ABORT][6] ([i915#8213] / [i915#9262])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#4083])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005:   [PASS][11] -> [DMESG-FAIL][12] ([i915#5334])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3:  [PASS][13] -> [FAIL][14] ([fdo#103375])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][15] ([i915#5190])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([i915#4215] / [i915#5190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#4212]) +6 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#4212] / [i915#5608])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp5:
- bat-adlp-11:[PASS][20] -> [DMESG-WARN][21] ([i915#1982] / 
[i915#6868])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vbl...@a-dp5.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vbl...@a-dp5.html

  * 

Re: [Intel-gfx] [PATCH v7 4/5] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck

[John Harrison]

On 10/5/2023 12:35, Jonathan Cavitt wrote:

For the gt_tlb live selftest, increase the timeout from 10 ms to 200 ms.
200 ms should be more than enough time, and 10 ms was too aggressive.
This is simply waiting for a request to begin executing on an idle 
system? How can 10ms possibly be too aggressive?


John.



Signed-off-by: Jonathan Cavitt 
---
  drivers/gpu/drm/i915/gt/selftest_tlb.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c 
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 7e41f69fc818f..46e0a1dbecc8d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -137,7 +137,7 @@ pte_tlbinv(struct intel_context *ce,
i915_request_add(rq);
  
  	/* Short sleep to sanitycheck the batch is spinning before we begin */

-   msleep(10);
+   msleep(200);
if (va == vb) {
if (!i915_request_completed(rq)) {
pr_err("%s(%s): Semaphore sanitycheck failed %llx, with 
alignment %llx, using PTE size %x (phys %x, sg %x)\n",

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Store DSC DPCD capabilities in the connector

[Patchwork]

== Series Details ==

Series: drm/i915: Store DSC DPCD capabilities in the connector
URL   : https://patchwork.freedesktop.org/series/124723/
State : warning

== Summary ==

Error: dim checkpatch failed
a34e461c1c43 drm/i915/dp: Sanitize DPCD revision check in 
intel_dp_get_dsc_sink_cap()
d53d0c044733 drm/i915/dp: Store DSC DPCD capabilities in the connector
2601054468a1 drm/i915/dp_mst: Set connector DSC capabilities and decompression 
AUX
14a104b8c113 drm/i915/dp: Use i915/intel connector local variables in 
i915_dsc_fec_support_show()
5e1338b3c2df drm/i915/dp: Use connector DSC DPCD in i915_dsc_fec_support_show()
-:39: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:1249:
+  
str_yes_no(drm_dp_sink_supports_fec(connector->dp.fec_capability)));

total: 0 errors, 1 warnings, 0 checks, 24 lines checked
e12f0222d790 drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_compute_max_bpp()
71a2b1178514 drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_fec()
437deb7a0cb1 drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_dsc()
7d24e3ba6c19 drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_max_sink_compressed_bppx16()
3876d9b5bdd6 drm/i915/dp: Pass connector DSC DPCD to 
drm_dp_dsc_sink_supported_input_bpcs()
e14f16280128 drm/i915/dp: Pass only the required i915 to 
intel_dp_source_dsc_version_minor()
c30e9d652751 drm/i915/dp: Pass only the required DSC DPCD to 
intel_dp_sink_dsc_version_minor()
dc5dda112095 drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_compute_params()
75d44fff8afe drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_supports_format()
821c5b466faf drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_get_slice_count()
bb21f88dfddf drm/i915/dp: Use connector DSC DPCD in intel_dp_mode_valid()
5e30b8ceb610 drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_compute_config()
d649e3acf8dd drm/i915/dp_mst: Use connector DSC DPCD in 
intel_dp_mst_mode_valid_ctx()
9674f9b43d9b drm/i915/dp: Remove unused DSC caps from intel_dp

Re: [Intel-gfx] [PATCH 2/2] drm/i915: enable W=1 warnings by default

[Nathan Chancellor]

On Fri, Oct 06, 2023 at 03:34:47PM +0300, Jani Nikula wrote:
> We enable a bunch more compiler warnings than the kernel
> defaults. However, they've drifted to become a unique set of warnings,
> and have increasingly fallen behind from the W=1 set.
> 
> Align with the W=1 warnings from scripts/Makefile.extrawarn for clarity,
> by copy-pasting them with s/KBUILD_CFLAGS/subdir-ccflags-y/ to make it
> easier to compare in the future.
> 
> Cc: Arnd Bergmann 
> Cc: Nick Desaulniers 
> Cc: Nathan Chancellor 
> Cc: Masahiro Yamada 
> Signed-off-by: Jani Nikula 

One meta comment and review comment below. Feel free to carry forward

Reviewed-by: Nathan Chancellor 

on future revisions.

> ---
> 
> An alternative or future option would be to have Makefile.extrawarn
> assign W=1 etc. flags to intermediate variables, say KBUILD_CFLAGS_W1,
> like this:
> 
> KBUILD_CFLAGS_W1 += -Wextra -Wunused -Wno-unused-parameter
> etc...
> 
> export KBUILD_CFLAGS_W1
> 
> ifneq ($(findstring 1, $(KBUILD_EXTRA_WARN)),)
> 
> KBUILD_CFLAGS += $(KBUILD_CFLAGS_W1)
> 
> else
> etc...
> 
> and then drivers and subsystems could simply use:
> 
> subdir-ccflags-y += $(KBUILD_CFLAGS_W1)
> 
> to enable and remain up-to-date with W=1 warnings.

This has definitely come up a few times and while I am generally in
favor of something like this, it makes adding warnings to W=1 a little
bit harder because when we add warnings to W=1, we typically are not
concerned with breaking the build, as W=1 is not the default build. If a
subsystem has opted into "whatever the current W=1 is" by default,
changes to W=1 will have to be reviewed/tested within a normal build.

Doing something like this patch with a more regular cadence (maybe every
update after the merge window) seems like a reasonable compromise to me,
although I know that means more work for individual subsystem
maintainers.

> ---
>  drivers/gpu/drm/i915/Makefile | 33 ++---
>  1 file changed, 18 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 623f81217442..0485157054fc 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -3,22 +3,25 @@
>  # Makefile for the drm device driver.  This driver provides support for the
>  # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
>  
> -# Add a set of useful warning flags and enable -Werror for CI to prevent
> -# trivial mistakes from creeping in. We have to do this piecemeal as we 
> reject
> -# any patch that isn't warning clean, so turning on -Wextra (or W=1) we
> -# need to filter out dubious warnings.  Still it is our interest
> -# to keep running locally with W=1 C=1 until we are completely clean.
> -#
> -# Note the danger in using -Wextra is that when CI updates gcc we
> -# will most likely get a sudden build breakage... Hopefully we will fix
> -# new warnings before CI updates!
> -subdir-ccflags-y := -Wextra
> -subdir-ccflags-y += -Wno-unused-parameter
> -subdir-ccflags-y += -Wno-type-limits
> -subdir-ccflags-y += -Wno-missing-field-initializers
> -subdir-ccflags-y += -Wno-sign-compare
> -subdir-ccflags-y += -Wno-shift-negative-value

As the test robot points out, you'll want to keep these four, as they
are only enabled for W=2 or W=3. With this diff on top of these two
patches:

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0485157054fc..9c4e09c8aa4e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -21,6 +21,12 @@ subdir-ccflags-y += $(call cc-option, -Wstringop-overflow)
 subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
 # --- end copy-paste
 
+# The following turn off the warnings enabled by -Wextra
+subdir-ccflags-y += -Wno-type-limits
+subdir-ccflags-y += -Wno-missing-field-initializers
+subdir-ccflags-y += -Wno-sign-compare
+subdir-ccflags-y += -Wno-shift-negative-value
+
 # Enable -Werror in CI and development
 subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
 
I can continue to build i915 warning free with ARCH=x86_64 allmodconfig
using all supported versions of LLVM for building the kernel.

> +# Unconditionally enable W=1 warnings locally
> +# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
> +subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
> +subdir-ccflags-y += -Wmissing-declarations
> +subdir-ccflags-y += $(call cc-option, -Wrestrict)
> +subdir-ccflags-y += -Wmissing-format-attribute
> +subdir-ccflags-y += -Wmissing-prototypes
> +subdir-ccflags-y += -Wold-style-definition
> +subdir-ccflags-y += -Wmissing-include-dirs
>  subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
> +subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
> +subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
> +subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
> +subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
> +subdir-ccflags-y += $(call cc-option, 

Re: [Intel-gfx] [PATCH v7 3/5] drm/i915: No TLB invalidation on wedged or suspended GT

[John Harrison]

On 10/6/2023 03:23, Tvrtko Ursulin wrote:



On 05/10/2023 20:35, Jonathan Cavitt wrote:

...
+static bool intel_gt_is_enabled(const struct intel_gt *gt)
+{
+    /* Check if GT is wedged or suspended */
+    if (intel_gt_is_wedged(gt) || !intel_irqs_enabled(gt->i915))
+    return false;
+    return true;
+}
+
  static int guc_send_invalidate_tlb(struct intel_guc *guc, u32 type)
  {
  struct intel_guc_tlb_wait _wq, *wq = &_wq;
@@ -4763,7 +4786,8 @@ static int guc_send_invalidate_tlb(struct 
intel_guc *guc, u32 type)

  };
  u32 size = ARRAY_SIZE(action);
  -    if (!intel_guc_ct_enabled(>ct))
+    if (!intel_gt_is_enabled(gt) ||
+    !intel_guc_ct_enabled(>ct))


IMO this reads confused but I leave it to the GuC experts to decide 
what makes sense. Not only that it reads confused but it does inspire 
confidence that it closes any race, since this state can still change 
just after this check, and then the invalidation request gets 
submitted (contrary to what the commit says?). Only thing it does 
below is skip the wait and the time out error message. Again, I leave 
it for people who know the GuC state transition flows to bless this part.


Regards,

Tvrtko
Regarding confused naming, I personally still think that 
intel_gt_is_enabled() is a bad name. Even the comment inside the 
function does not mention 'enable', it says 'wedged or suspended'. One 
could certainly argue that the GT is also not currently enabled if GuC 
is in use but the CT channel is down.


Regarding race conditions, the only things that can take the CT channel 
down are driver shutdown, suspend and GT reset. On the submission side, 
the assumption is that the scheduling levels of the driver are not going 
to call in to the submission backend without suitable locking held to 
ensure those operations cannot occur concurrently. Is the same not true 
here? We have to guard against the situation where the call starts from 
a 'bad' state, e.g. wedged. But the lowest level of code can't be 
expected to take higher level locks. From all the way down here, we have 
no idea what the upper levels may or may not be doing and what locks may 
or may not have been acquired, and therefore what locks may or may not 
be safe to acquire.


John.




  return -EINVAL;
    init_waitqueue_head(&_wq.wq);
@@ -4806,7 +4830,8 @@ static int guc_send_invalidate_tlb(struct 
intel_guc *guc, u32 type)

   * can be queued in CT buffer.
   */
  #define OUTSTANDING_GUC_TIMEOUT_PERIOD  (HZ * 2)
-    if (!must_wait_woken(, OUTSTANDING_GUC_TIMEOUT_PERIOD)) {
+    if (intel_gt_is_enabled(gt) &&
+    !must_wait_woken(, OUTSTANDING_GUC_TIMEOUT_PERIOD)) {
  gt_err(gt,
 "TLB invalidation response timed out for seqno 
%u\n", seqno);

  err = -ETIME;
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c

index ccbb2834cde07..0c9d9826d2f41 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -72,6 +72,7 @@
  #include "gt/intel_gt.h"
  #include "gt/intel_gt_pm.h"
  #include "gt/intel_rc6.h"
+#include "gt/intel_tlb.h"
    #include "pxp/intel_pxp.h"
  #include "pxp/intel_pxp_debugfs.h"
@@ -1093,6 +1094,9 @@ static int i915_drm_suspend(struct drm_device 
*dev)

  intel_dp_mst_suspend(dev_priv);
    intel_runtime_pm_disable_interrupts(dev_priv);
+
+    intel_gt_tlb_suspend_all(dev_priv);
+
  intel_hpd_cancel_work(dev_priv);
    intel_suspend_encoders(dev_priv);
@@ -1264,6 +1268,8 @@ static int i915_drm_resume(struct drm_device *dev)
    intel_gvt_resume(dev_priv);
  +    intel_gt_tlb_resume_all(dev_priv);
+
  enable_rpm_wakeref_asserts(_priv->runtime_pm);
    return 0;

Re: [Intel-gfx] [PATCH 1/2] drm/i915: drop -Wall and related disables from cflags as redundant

[Nathan Chancellor]

On Fri, Oct 06, 2023 at 03:34:46PM +0300, Jani Nikula wrote:
> The kernel top level Makefile, and recently scripts/Makefile.extrawarn,
> have included -Wall, and the disables -Wno-format-security and
> $(call cc-disable-warning,frame-address,) for a very long time. They're
> redundant in our local subdir-ccflags-y and can be dropped.
> 
> Cc: Arnd Bergmann 
> Cc: Nick Desaulniers 
> Cc: Nathan Chancellor 
> Cc: Masahiro Yamada 
> Signed-off-by: Jani Nikula 

Yeah, this seems totally reasonable. I always assumed the intention of
-Wall was to re-enable some warnings that the rest of the kernel had
turned off but I think we are getting better about auditing what
warnings are explicitly turned off and getting some of those turned back
on for the whole kernel, so I expect this to basically be a no-op.

Reviewed-by: Nathan Chancellor 

> ---
>  drivers/gpu/drm/i915/Makefile | 8 +++-
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index dec78efa452a..623f81217442 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -5,22 +5,20 @@
>  
>  # Add a set of useful warning flags and enable -Werror for CI to prevent
>  # trivial mistakes from creeping in. We have to do this piecemeal as we 
> reject
> -# any patch that isn't warning clean, so turning on -Wall -Wextra (or W=1) we
> +# any patch that isn't warning clean, so turning on -Wextra (or W=1) we
>  # need to filter out dubious warnings.  Still it is our interest
>  # to keep running locally with W=1 C=1 until we are completely clean.
>  #
> -# Note the danger in using -Wall -Wextra is that when CI updates gcc we
> +# Note the danger in using -Wextra is that when CI updates gcc we
>  # will most likely get a sudden build breakage... Hopefully we will fix
>  # new warnings before CI updates!
> -subdir-ccflags-y := -Wall -Wextra
> -subdir-ccflags-y += -Wno-format-security
> +subdir-ccflags-y := -Wextra
>  subdir-ccflags-y += -Wno-unused-parameter
>  subdir-ccflags-y += -Wno-type-limits
>  subdir-ccflags-y += -Wno-missing-field-initializers
>  subdir-ccflags-y += -Wno-sign-compare
>  subdir-ccflags-y += -Wno-shift-negative-value
>  subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
> -subdir-ccflags-y += $(call cc-disable-warning, frame-address)
>  subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
>  
>  # Fine grained warnings disable
> -- 
> 2.39.2
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/print: Add drm_dbg_ratelimited

[Patchwork]

== Series Details ==

Series: drm/print: Add drm_dbg_ratelimited
URL   : https://patchwork.freedesktop.org/series/124722/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124722v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/index.html

Participating hosts (39 -> 39)
--

  Additional (1): bat-dg2-9 
  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_124722v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-hsw-4770:[PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-hsw-4770/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-9:  NOTRUN -> [INCOMPLETE][3] ([i915#9275])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][5] ([i915#4077]) +2 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#6621])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#5190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#4215] / [i915#5190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#4212]) +6 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#4212] / [i915#5608])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([fdo#109285])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9:  NOTRUN -> [SKIP][14] ([i915#5274])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5:
- bat-adlp-11:[PASS][15] -> [ABORT][16] ([i915#8668])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-dp-5.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-dp-5.html

  * igt@kms_psr@sprite_plane_onoff:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#1072]) +3 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#3555])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
- bat-dg2-9:  NOTRUN -> [SKIP][19] ([i915#3708])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124722v1/bat-dg2-9/igt@prime_v...@basic-fence-flip.html

  * 

Re: [Intel-gfx] [PATCH 2/2] drm/i915: enable W=1 warnings by default

[kernel test robot]

Hi Jani,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-tip/drm-tip]

url:
https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-i915-drop-Wall-and-related-disables-from-cflags-as-redundant/20231006-203658
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:
https://lore.kernel.org/r/f50c8ea0e63615aea28fe7f6049703e1d28ba7eb.1696595500.git.jani.nikula%40intel.com
patch subject: [Intel-gfx] [PATCH 2/2] drm/i915: enable W=1 warnings by default
config: x86_64-rhel-8.3-rust 
(https://download.01.org/0day-ci/archive/20231007/202310070011.fji48ibk-...@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git 
ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): 
(https://download.01.org/0day-ci/archive/20231007/202310070011.fji48ibk-...@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot 
| Closes: 
https://lore.kernel.org/oe-kbuild-all/202310070011.fji48ibk-...@intel.com/

All warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/i915/i915_driver.c:30:
   In file included from include/linux/acpi.h:13:
   In file included from include/linux/resource_ext.h:11:
   In file included from include/linux/slab.h:16:
   In file included from include/linux/gfp.h:7:
   In file included from include/linux/mmzone.h:8:
   In file included from include/linux/spinlock.h:56:
   In file included from include/linux/preempt.h:79:
   In file included from arch/x86/include/asm/preempt.h:9:
>> include/linux/thread_info.h:240:29: warning: comparison of integers of 
>> different signs: 'int' and 'size_t' (aka 'unsigned long') [-Wsign-compare]
   if (unlikely(sz >= 0 && sz < bytes)) {
   ~~ ^ ~
   include/linux/compiler.h:77:42: note: expanded from macro 'unlikely'
   # define unlikely(x)__builtin_expect(!!(x), 0)
   ^
   In file included from drivers/gpu/drm/i915/i915_driver.c:30:
   In file included from include/linux/acpi.h:13:
   In file included from include/linux/resource_ext.h:11:
   In file included from include/linux/slab.h:16:
   In file included from include/linux/gfp.h:7:
   In file included from include/linux/mmzone.h:22:
>> include/linux/mm_types.h:1036:13: warning: comparison of integers of 
>> different signs: 'int' and 'unsigned int' [-Wsign-compare]
   return cid == MM_CID_UNSET;
  ~~~ ^  
   include/linux/mm_types.h:1074:2: warning: comparison of integers of 
different signs: 'int' and 'unsigned int' [-Wsign-compare]
   for_each_possible_cpu(i) {
   ^~~~
   include/linux/cpumask.h:974:36: note: expanded from macro 
'for_each_possible_cpu'
   #define for_each_possible_cpu(cpu) for_each_cpu((cpu), cpu_possible_mask)
  ^~
   include/linux/cpumask.h:282:2: note: expanded from macro 'for_each_cpu'
   for_each_set_bit(cpu, cpumask_bits(mask), small_cpumask_bits)
   ^~~~  ~~
   include/linux/find.h:559:70: note: expanded from macro 'for_each_set_bit'
   for ((bit) = 0; (bit) = find_next_bit((addr), (size), (bit)), (bit) 
< (size); (bit)++)
  ~~~  
^  
   In file included from drivers/gpu/drm/i915/i915_driver.c:30:
   In file included from include/linux/acpi.h:13:
   In file included from include/linux/resource_ext.h:11:
   In file included from include/linux/slab.h:16:
   In file included from include/linux/gfp.h:7:
>> include/linux/mmzone.h:1627:44: warning: comparison of integers of different 
>> signs: 'int' and 'enum zone_type' [-Wsign-compare]
   if (likely(!nodes && zonelist_zone_idx(z) <= highest_zoneidx))
 ^  ~~~
   include/linux/compiler.h:76:40: note: expanded from macro 'likely'
   # define likely(x)  __builtin_expect(!!(x), 1)
   ^
   In file included from drivers/gpu/drm/i915/i915_driver.c:30:
   In file included from include/linux/acpi.h:13:
   In file included from include/linux/resource_ext.h:11:
   In file included from include/linux/slab.h:20:
>> include/linux/percpu-refcount.h:205:3: warning: comparison of integers of 
>> different signs: 'unsigned long' and 'int' [-Wsign-compare]
   this_cpu_add(*percpu_count, nr);
   ^~~
   include/linux/percpu-defs.h:491:33: note: expanded from macro 'this_cpu_add'
  

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/print: Add drm_dbg_ratelimited

[Patchwork]

== Series Details ==

Series: drm/print: Add drm_dbg_ratelimited
URL   : https://patchwork.freedesktop.org/series/124722/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v7 2/5] drm/i915: Define and use GuC and CTB TLB invalidation routines

[John Harrison]

On 10/6/2023 09:18, John Harrison wrote:

On 10/6/2023 03:20, Nirmoy Das wrote:


On 10/6/2023 12:11 PM, Tvrtko Ursulin wrote:


Hi,


Andi asked me to summarize what I think is unaddressed review 
feedback so far in order to consolidate and enable hopefully things 
to move forward. So I will try to re-iterate the comments and 
questions below.


But also note that there is a bunch of new valid comments from John 
against v7 which I will not repeat.


On 05/10/2023 20:35, Jonathan Cavitt wrote:

...
+enum intel_guc_tlb_invalidation_type {
+    INTEL_GUC_TLB_INVAL_FULL = 0x0,
+    INTEL_GUC_TLB_INVAL_GUC = 0x3,


New question - are these names coming from the GuC iface? I find it 
confusing that full does not include GuC but maybe it is just me. So 
maybe full should be called GT or something? Although then again it 
wouldn't be clear GT does not include the GuC..  bummer. GPU? Dunno. 
Minor confusion I guess so can keep as is.


I agree this is bit confusing name. We are using 
INTEL_GUC_TLB_INVAL_GUC to invalidate ggtt, how about 
INTEL_GUC_TLB_INVAL_GGTT ?



The GuC interface spec says:

GUC_TLB_INV_TYPE_TLB_INV_FULL_INTRA_VF = 0x00
Full TLB invalidation within a VF. Invalidates VF’s TLBs only if
that VF is active, will invalidate across all engines.

GUC_TLB_INV_TYPE_TLB_INV_GUC = 0x03
Guc TLB Invalidation.


So the 'GUC' type is not GGTT, it is the TLBs internal to GuC itself 
is how I would read the above. Whereas 'FULL' is everything that is 
per-VF, aka everything in the GT that is beyond the GuC level - i.e. 
the engines, EUs and everything from there on.


So I think the INVAL_GUC name is correct. But maybe INVAL_FULL should 
be called INVAL_VF? Or INVAL_ENGINES if you don't like using the VF 
term in a non-SRIOV capable driver?


John.



PS: The function names should also match the type name.

Currently the functions are:
    int intel_guc_invalidate_tlb_full(struct intel_guc *guc);
    int intel_guc_invalidate_tlb(struct intel_guc *guc);

The second should have a suffix to say what is being invalidated - e.g. 
intel_guc_invalidate_tlb_guc(). The 'guc' in the prefix is just 
describing the mechanism not the target. So I would read the above as 
'full' being a subset of 'blank'.


John.

Re: [Intel-gfx] [PATCH v7 2/5] drm/i915: Define and use GuC and CTB TLB invalidation routines

[John Harrison]

On 10/6/2023 03:20, Nirmoy Das wrote:


On 10/6/2023 12:11 PM, Tvrtko Ursulin wrote:


Hi,


Andi asked me to summarize what I think is unaddressed review 
feedback so far in order to consolidate and enable hopefully things 
to move forward. So I will try to re-iterate the comments and 
questions below.


But also note that there is a bunch of new valid comments from John 
against v7 which I will not repeat.


On 05/10/2023 20:35, Jonathan Cavitt wrote:

...
+enum intel_guc_tlb_invalidation_type {
+    INTEL_GUC_TLB_INVAL_FULL = 0x0,
+    INTEL_GUC_TLB_INVAL_GUC = 0x3,


New question - are these names coming from the GuC iface? I find it 
confusing that full does not include GuC but maybe it is just me. So 
maybe full should be called GT or something? Although then again it 
wouldn't be clear GT does not include the GuC.. bummer. GPU? Dunno. 
Minor confusion I guess so can keep as is.


I agree this is bit confusing name. We are using 
INTEL_GUC_TLB_INVAL_GUC to invalidate ggtt, how about 
INTEL_GUC_TLB_INVAL_GGTT ?



The GuC interface spec says:

   GUC_TLB_INV_TYPE_TLB_INV_FULL_INTRA_VF = 0x00
   Full TLB invalidation within a VF. Invalidates VF’s TLBs only if
   that VF is active, will invalidate across all engines.

   GUC_TLB_INV_TYPE_TLB_INV_GUC = 0x03
   Guc TLB Invalidation.


So the 'GUC' type is not GGTT, it is the TLBs internal to GuC itself is 
how I would read the above. Whereas 'FULL' is everything that is per-VF, 
aka everything in the GT that is beyond the GuC level - i.e. the 
engines, EUs and everything from there on.


So I think the INVAL_GUC name is correct. But maybe INVAL_FULL should be 
called INVAL_VF? Or INVAL_ENGINES if you don't like using the VF term in 
a non-SRIOV capable driver?


John.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: align with W=1 warnings

[Patchwork]

== Series Details ==

Series: drm/i915: align with W=1 warnings
URL   : https://patchwork.freedesktop.org/series/124718/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124718v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124718v1/index.html

Participating hosts (39 -> 38)
--

  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_124718v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-dp6:
- bat-adlp-11:[PASS][1] -> [DMESG-WARN][2] ([i915#6868])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vbl...@c-dp6.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124718v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vbl...@c-dp6.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@d-dp6:
- bat-adlp-11:[PASS][3] -> [FAIL][4] ([i915#6121])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vbl...@d-dp6.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124718v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vbl...@d-dp6.html

  * igt@kms_flip@basic-plain-flip:
- bat-adlp-11:NOTRUN -> [SKIP][5] ([i915#3637])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124718v1/bat-adlp-11/igt@kms_f...@basic-plain-flip.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5:
- bat-adlp-11:[PASS][6] -> [ABORT][7] ([i915#8668])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-dp-5.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124718v1/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-dp-5.html

  
 Possible fixes 

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][8] ([IGT#3]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124718v1/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-5:
- bat-adlp-11:[ABORT][10] ([i915#8668] / [i915#9451]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-c-dp-5.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124718v1/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-c-dp-5.html

  
 Warnings 

  * igt@kms_force_connector_basic@force-connector-state:
- bat-adlp-11:[SKIP][12] ([i915#4093]) -> [FAIL][13] ([i915#8803])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-11/igt@kms_force_connector_ba...@force-connector-state.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124718v1/bat-adlp-11/igt@kms_force_connector_ba...@force-connector-state.html

  
  [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093
  [i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
  [i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8803]: https://gitlab.freedesktop.org/drm/intel/issues/8803
  [i915#9451]: https://gitlab.freedesktop.org/drm/intel/issues/9451


Build changes
-

  * Linux: CI_DRM_13722 -> Patchwork_124718v1

  CI-20190529: 20190529
  CI_DRM_13722: ead693ec2d2fddb30bff4718845d42f9adabcce6 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7518: 2d4a57e28db0c2ccbf8b2e763074c9aa74a1ae52 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_124718v1: ead693ec2d2fddb30bff4718845d42f9adabcce6 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

596a52a71ef7 drm/i915: enable W=1 warnings by default
e28a46430f10 drm/i915: drop -Wall and related disables from cflags as redundant

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124718v1/index.html

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Remove early/pre-production Haswell code

[Zanoni, Paulo R]

On Fri, 2023-10-06 at 09:31 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> It is not our policy to keep pre-production hardware support for this long
> so I guess this one was just forgotten.

Wouldn't it make sense to also remove the PCI IDs if they never made it
to the real production world*? Couldn't these IDs end up getting reused
for something else (maybe not even graphics) at some point in the
future?

*: I can't confirm this is the case.

> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_driver.c | 1 -
>  drivers/gpu/drm/i915/i915_drv.h| 2 --
>  2 files changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> b/drivers/gpu/drm/i915/i915_driver.c
> index ccbb2834cde0..78a42c8a8509 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -175,7 +175,6 @@ static void intel_detect_preproduction_hw(struct 
> drm_i915_private *dev_priv)
>  {
>   bool pre = false;
>  
> - pre |= IS_HASWELL_EARLY_SDV(dev_priv);
>   pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
>   pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
>   pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cb60fc9cf873..9d493ff1685a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -590,8 +590,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
>  #define IS_RAPTORLAKE_U(i915) \
>   IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> -#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
> - (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
>  #define IS_BROADWELL_ULT(i915) \
>   IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
>  #define IS_BROADWELL_ULX(i915) \

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: align with W=1 warnings

[Patchwork]

== Series Details ==

Series: drm/i915: align with W=1 warnings
URL   : https://patchwork.freedesktop.org/series/124718/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/lnl: Remove watchdog timers for PSR

[Patchwork]

== Series Details ==

Series: drm/i915/lnl: Remove watchdog timers for PSR
URL   : https://patchwork.freedesktop.org/series/124715/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124715v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/index.html

Participating hosts (39 -> 38)
--

  Additional (1): bat-dg2-9 
  Missing(2): fi-snb-2520m fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_124715v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-hsw-4770:[PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-hsw-4770/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-9:  NOTRUN -> [INCOMPLETE][3] ([i915#9275])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][5] ([i915#4077]) +2 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#6621])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hugepages:
- bat-mtlp-8: [PASS][8] -> [ABORT][9] ([i915#9414])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html

  * igt@i915_selftest@live@requests:
- bat-mtlp-6: [PASS][10] -> [ABORT][11] ([i915#9414])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-mtlp-6/igt@i915_selftest@l...@requests.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([i915#5190])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#4215] / [i915#5190])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][14] ([i915#4212]) +6 other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][15] ([i915#4212] / [i915#5608])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-dpms@a-dp5:
- bat-adlp-11:[PASS][17] -> [DMESG-WARN][18] ([i915#6868])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-11/igt@kms_flip@basic-flip-vs-d...@a-dp5.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-d...@a-dp5.html

  * igt@kms_flip@basic-flip-vs-dpms@d-dp6:
- bat-adlp-11:[PASS][19] -> [FAIL][20] ([i915#6121]) +6 other tests 
fail
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adlp-11/igt@kms_flip@basic-flip-vs-d...@d-dp6.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-d...@d-dp6.html

  * igt@kms_flip@basic-flip-vs-modeset:
- bat-adlp-11:NOTRUN -> [SKIP][21] ([i915#3637])
   [21]: 

Re: [Intel-gfx] [PATCH 01/19] drm/i915/dp: Sanitize DPCD revision check in intel_dp_get_dsc_sink_cap()

[Lisovskiy, Stanislav]

On Fri, Oct 06, 2023 at 04:37:09PM +0300, Imre Deak wrote:
> Check only the eDP or the DP specific DPCD revision depending on the
> sink type. Pass the corresponding revision to the function, which allows
> getting the DSC caps of a branch device (in an MST topology, which has
> its own DPCD and so DPCD revision).
> 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 12 +++-
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0ef7cb8134b66..1bd11f9e308c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3467,7 +3467,7 @@ bool intel_dp_get_colorimetry_status(struct intel_dp 
> *intel_dp)
>   return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
>  }
>  
> -static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
> +static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp)
>  {
>   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  
> @@ -3481,8 +3481,8 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp 
> *intel_dp)
>   intel_dp->fec_capable = 0;
>  
>   /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
> - if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
> - intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> + if ((intel_dp_is_edp(intel_dp) && dpcd_rev >= DP_EDP_14) ||
> + (!intel_dp_is_edp(intel_dp) && dpcd_rev >= 0x14)) {

A bit curious whether could we use some macro for 0x14, just as for DP_EDP_14?
Because otherwise we are combining some values with macros, which seems like a 
bit
non-uniform approach.

However that is a minor thing anyway..

Reviewed-by: Stanislav Lisovskiy 


>   if (drm_dp_dpcd_read(_dp->aux, DP_DSC_SUPPORT,
>intel_dp->dsc_dpcd,
>sizeof(intel_dp->dsc_dpcd)) < 0)
> @@ -3674,7 +3674,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>  
>   /* Read the eDP DSC DPCD registers */
>   if (HAS_DSC(dev_priv))
> - intel_dp_get_dsc_sink_cap(intel_dp);
> + intel_dp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
> +   intel_dp);
>  
>   /*
>* If needed, program our source OUI so we can make various 
> Intel-specific AUX services
> @@ -5384,7 +5385,8 @@ intel_dp_detect(struct drm_connector *connector,
>  
>   /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
>   if (HAS_DSC(dev_priv))
> - intel_dp_get_dsc_sink_cap(intel_dp);
> + intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
> +   intel_dp);
>  
>   intel_dp_configure_mst(intel_dp);
>  
> -- 
> 2.39.2
> 

[Intel-gfx] [PATCH] drm/i915/guc: Update 'recommended' version to 70.12.1 for DG2/ADL-S/ADL-P/MTL

[John . C . Harrison]

From: John Harrison 

The latest GuC has new features and new workarounds that we wish to
enable. So let the universe know that it is useful to update their
firmware.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 32e27e9a2490f..362639162ed60 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -88,12 +88,12 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * security fixes, etc. to be enabled.
  */
 #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \
-   fw_def(METEORLAKE,   0, guc_maj(mtl,  70, 6, 6)) \
-   fw_def(DG2,  0, guc_maj(dg2,  70, 5, 1)) \
-   fw_def(ALDERLAKE_P,  0, guc_maj(adlp, 70, 5, 1)) \
+   fw_def(METEORLAKE,   0, guc_maj(mtl,  70, 12, 1)) \
+   fw_def(DG2,  0, guc_maj(dg2,  70, 12, 1)) \
+   fw_def(ALDERLAKE_P,  0, guc_maj(adlp, 70, 12, 1)) \
fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 70, 1, 1)) \
fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 69, 0, 3)) \
-   fw_def(ALDERLAKE_S,  0, guc_maj(tgl,  70, 5, 1)) \
+   fw_def(ALDERLAKE_S,  0, guc_maj(tgl,  70, 12, 1)) \
fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  70, 1, 1)) \
fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  69, 0, 3)) \
fw_def(DG1,  0, guc_maj(dg1,  70, 5, 1)) \
-- 
2.41.0

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/atomic-helper: relax unregistered connector check

[Patchwork]

== Series Details ==

Series: drm/atomic-helper: relax unregistered connector check
URL   : https://patchwork.freedesktop.org/series/124664/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13719_full -> Patchwork_124664v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 10)
--

  Additional (1): shard-tglu0 

Known issues


  Here are the changes found in Patchwork_124664v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[FAIL][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50]) ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk6/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk4/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk4/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk4/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk4/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk9/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk9/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk9/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk5/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk8/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk8/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk8/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk7/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk7/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk2/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk2/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk3/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk3/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-glk3/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk7/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk3/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk4/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk4/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk4/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk4/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk5/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk5/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk5/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk6/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk6/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk7/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk7/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk8/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk8/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk8/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124664v1/shard-glk8/boot.html
   [43]: 

[Intel-gfx] ✗ Fi.CI.BAT: failure for Trim some pre-production code

[Patchwork]

== Series Details ==

Series: Trim some pre-production code
URL   : https://patchwork.freedesktop.org/series/124705/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124705v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_124705v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_124705v1, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v1/index.html

Participating hosts (39 -> 38)
--

  Missing(1): fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_124705v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-skl-6600u:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-skl-6600u/igt@i915_susp...@basic-s3-without-i915.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v1/fi-skl-6600u/igt@i915_susp...@basic-s3-without-i915.html

  
Known issues


  Here are the changes found in Patchwork_124705v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@smem:
- bat-mtlp-8: [PASS][3] -> [ABORT][4] ([i915#8213] / [i915#9262])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v1/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][7] -> [ABORT][8] ([i915#8668])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html

  
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#9262]: https://gitlab.freedesktop.org/drm/intel/issues/9262


Build changes
-

  * Linux: CI_DRM_13722 -> Patchwork_124705v1

  CI-20190529: 20190529
  CI_DRM_13722: ead693ec2d2fddb30bff4718845d42f9adabcce6 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7518: 2d4a57e28db0c2ccbf8b2e763074c9aa74a1ae52 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_124705v1: ead693ec2d2fddb30bff4718845d42f9adabcce6 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

6843d74d0170 drm/i915: Remove xehpsdv support
bafa8152bd7a drm/i915: Remove incomplete PVC plumbing
33908308e6d8 drm/i915: Remove early/pre-production Haswell code

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124705v1/index.html

[Intel-gfx] [CI] PR for new GuC v70.12.1

[John . C . Harrison]

The following changes since commit 5105ff4b9f43ba08d0a22260d670120e53c4b667:

  Merge branch 'mlimonci/upstream-packaging' into 'main' (2023-10-04 12:35:17 
+)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware guc_70.12.1

for you to fetch changes up to 22fb3576f39769162c5da556159b72745b8570a8:

  i915: Add GuC v70.12.1 for DG2, TGL, ADL-P and MTL (2023-10-06 01:52:14 -0700)


John Harrison (1):
  i915: Add GuC v70.12.1 for DG2, TGL, ADL-P and MTL

 WHENCE   |   8 
 i915/adlp_guc_70.bin | Bin 297984 -> 342528 bytes
 i915/dg2_guc_70.bin  | Bin 385856 -> 443200 bytes
 i915/mtl_guc_70.bin  | Bin 308032 -> 365376 bytes
 i915/tgl_guc_70.bin  | Bin 285888 -> 329984 bytes
 5 files changed, 4 insertions(+), 4 deletions(-)

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Trim some pre-production code

[Patchwork]

== Series Details ==

Series: Trim some pre-production code
URL   : https://patchwork.freedesktop.org/series/124705/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH] drm/i915: Add bigjoiner force enable option to debugfs

[Stanislav Lisovskiy]

For validation purposes, it might be useful to be able to
force Bigjoiner mode, even if current dotclock/resolution
do not require that.
Lets add such to option to debugfs.

Signed-off-by: Stanislav Lisovskiy 
---
 .../drm/i915/display/intel_display_debugfs.c  | 71 +++
 .../drm/i915/display/intel_display_types.h|  2 +
 drivers/gpu/drm/i915/display/intel_dp.c   |  3 +-
 3 files changed, 75 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f6d7c4d45fae..5855c6de91a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1399,6 +1399,35 @@ out: 
drm_modeset_unlock(>mode_config.connection_mutex);
return ret;
 }
 
+static int i915_bigjoiner_enable_show(struct seq_file *m, void *data)
+{
+   struct drm_connector *connector = m->private;
+   struct drm_device *dev = connector->dev;
+   struct drm_crtc *crtc;
+   struct intel_encoder *encoder = 
intel_attached_encoder(to_intel_connector(connector));
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+   int ret;
+
+   if (!encoder)
+   return -ENODEV;
+
+   ret = 
drm_modeset_lock_single_interruptible(>mode_config.connection_mutex);
+   if (ret)
+   return ret;
+
+   crtc = connector->state->crtc;
+   if (connector->status != connector_status_connected || !crtc) {
+   ret = -ENODEV;
+   goto out;
+   }
+
+   seq_printf(m, "Bigjoiner enable: %d\n", intel_dp->force_bigjoiner_en);
+
+out:   drm_modeset_unlock(>mode_config.connection_mutex);
+
+   return ret;
+}
+
 static ssize_t i915_dsc_output_format_write(struct file *file,
const char __user *ubuf,
size_t len, loff_t *offp)
@@ -1420,12 +1449,39 @@ static ssize_t i915_dsc_output_format_write(struct file 
*file,
return len;
 }
 
+static ssize_t i915_bigjoiner_enable_fops_write(struct file *file,
+   const char __user *ubuf,
+   size_t len, loff_t *offp)
+{
+   struct drm_connector *connector =
+   ((struct seq_file *)file->private_data)->private;
+   struct intel_encoder *encoder = 
intel_attached_encoder(to_intel_connector(connector));
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+   int bigjoiner_en = 0;
+   int ret;
+
+   ret = kstrtoint_from_user(ubuf, len, 0, _en);
+   if (ret < 0)
+   return ret;
+
+   intel_dp->force_bigjoiner_en = bigjoiner_en;
+   *offp += len;
+
+   return len;
+}
+
 static int i915_dsc_output_format_open(struct inode *inode,
   struct file *file)
 {
return single_open(file, i915_dsc_output_format_show, inode->i_private);
 }
 
+static int i915_bigjoiner_enable_open(struct inode *inode,
+ struct file *file)
+{
+   return single_open(file, i915_bigjoiner_enable_show, inode->i_private);
+}
+
 static const struct file_operations i915_dsc_output_format_fops = {
.owner = THIS_MODULE,
.open = i915_dsc_output_format_open,
@@ -1435,6 +1491,15 @@ static const struct file_operations 
i915_dsc_output_format_fops = {
.write = i915_dsc_output_format_write
 };
 
+static const struct file_operations i915_bigjoiner_enable_fops = {
+   .owner = THIS_MODULE,
+   .open = i915_bigjoiner_enable_open,
+   .read = seq_read,
+   .llseek = seq_lseek,
+   .release = single_release,
+   .write = i915_bigjoiner_enable_fops_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1514,6 +1579,12 @@ void intel_connector_debugfs_add(struct intel_connector 
*intel_connector)
connector, _dsc_output_format_fops);
}
 
+   if (intel_dp_can_bigjoiner(enc_to_intel_dp(intel_connector->encoder)) &&
+   connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+   debugfs_create_file("i915_bigjoiner_force_enable", 0644, root,
+   connector, _bigjoiner_enable_fops);
+   }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8d8b2f8d37a9..ecec8a25838e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1753,6 +1753,8 @@ struct intel_dp {
bool is_mst;
int active_mst_links;
 
+   

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ddi: Fix i2c_adapter assignment (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/ddi: Fix i2c_adapter assignment (rev3)
URL   : https://patchwork.freedesktop.org/series/124646/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124646v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/index.html

Participating hosts (39 -> 39)
--

  Additional (1): bat-dg2-9 
  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_124646v3 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-bsw-n3050:   [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-bsw-n3050/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/fi-bsw-n3050/boot.html
- fi-hsw-4770:[PASS][3] -> [FAIL][4] ([i915#8293])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-hsw-4770/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@requests:
- bat-mtlp-8: [PASS][9] -> [ABORT][10] ([i915#9414])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#5190])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([i915#4215] / [i915#5190])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#4212]) +6 other tests skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][14] ([i915#4212] / [i915#5608])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([fdo#109285])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#5274])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_psr@sprite_plane_onoff:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#1072]) +3 other tests skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-9:  NOTRUN -> [SKIP][19] ([i915#3555])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
- bat-dg2-9:  NOTRUN -> [SKIP][20] ([i915#3708])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124646v3/bat-dg2-9/igt@prime_v...@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
- bat-dg2-9:  NOTRUN -> 

[Intel-gfx] [PATCH 19/19] drm/i915/dp: Remove unused DSC caps from intel_dp

[Imre Deak]

The previous patches converted all users of the DSC DPCD caps to look
these up from the connector, so remove the version stored in intel_dp.

A follow-up patchset will read out the MST connector specific
capabilities in intel_dp_add_mst_connector() ->
intel_dp_mst_read_decompression_port_dsc_caps().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  2 --
 drivers/gpu/drm/i915/display/intel_dp.c| 14 --
 2 files changed, 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index d6600079bcf74..65ea37fe8cff3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1725,10 +1725,8 @@ struct intel_dp {
u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
-   u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
-   u8 fec_capable;
u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
/* source rates */
int num_source_rates;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index f58940c1baf9c..9d504ce2b54a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3514,15 +3514,6 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct 
intel_dp *intel_dp,
drm_dbg_kms(>drm, "FEC CAPABILITY: %x\n",
connector->dp.fec_capability);
}
-
-   /*
-* TODO: remove the following intel_dp copies once all users
-* are converted to look up DSC DPCD/FEC capability via the
-* connector.
-*/
-   memcpy(intel_dp->dsc_dpcd, connector->dp.dsc_dpcd,
-  sizeof(intel_dp->dsc_dpcd));
-   intel_dp->fec_capable = connector->dp.fec_capability;
 }
 
 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
@@ -5390,11 +5381,6 @@ intel_dp_detect(struct drm_connector *connector,
 
if (status == connector_status_disconnected) {
memset(_dp->compliance, 0, sizeof(intel_dp->compliance));
-   /*
-* TODO: Remove clearing the DPCD in intel_dp, once all
-* user are converted to using the DPCD in connector.
-*/
-   memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
memset(intel_connector->dp.dsc_dpcd, 0, 
sizeof(intel_connector->dp.dsc_dpcd));
 
if (intel_dp->is_mst) {
-- 
2.39.2

[Intel-gfx] [PATCH 16/19] drm/i915/dp: Use connector DSC DPCD in intel_dp_mode_valid()

[Imre Deak]

Use the connector's DSC DPCD capabilities in intel_dp_mode_valid().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7449ff145a842..baab353154e85 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1205,7 +1205,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
   
intel_dp_mode_min_output_bpp(connector, mode));
 
if (HAS_DSC(dev_priv) &&
-   drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+   drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
enum intel_output_format sink_format, output_format;
int pipe_bpp;
 
@@ -1223,11 +1223,11 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 */
if (intel_dp_is_edp(intel_dp)) {
dsc_max_compressed_bpp =
-   drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) 
>> 4;
+   
drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
dsc_slice_count =
-   
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
+   
drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
true);
-   } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
+   } else if 
(drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
dsc_max_compressed_bpp =
intel_dp_dsc_get_max_compressed_bpp(dev_priv,

max_link_clock,
-- 
2.39.2

[Intel-gfx] [PATCH 17/19] drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_config()

[Imre Deak]

Use the connector's DSC DPCD capabilities in
intel_dp_dsc_compute_config().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index baab353154e85..f58940c1baf9c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2150,7 +2150,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
/* Calculate Slice count */
if (intel_dp_is_edp(intel_dp)) {
pipe_config->dsc.slice_count =
-   drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
+   drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
true);
if (!pipe_config->dsc.slice_count) {
drm_dbg_kms(_priv->drm, "Unsupported Slice Count 
%d\n",
-- 
2.39.2

[Intel-gfx] [PATCH 18/19] drm/i915/dp_mst: Use connector DSC DPCD in intel_dp_mst_mode_valid_ctx()

[Imre Deak]

Use the connector's DSC DPCD capabilities in
intel_dp_mst_mode_valid_ctx().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 115d4d8870b03..a065388c2199f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -996,14 +996,14 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
*connector,
}
 
if (DISPLAY_VER(dev_priv) >= 10 &&
-   drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+   drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) {
/*
 * TBD pass the connector BPC,
 * for now U8_MAX so that max BPC on that platform would be 
picked
 */
int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, 
U8_MAX);
 
-   if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
+   if 
(drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {
dsc_max_compressed_bpp =
intel_dp_dsc_get_max_compressed_bpp(dev_priv,

max_link_clock,
-- 
2.39.2

[Intel-gfx] [PATCH 13/19] drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_params()

[Imre Deak]

Use the connector's DSC DPCD capabilities in
intel_dp_dsc_compute_params().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index d08a206cb1237..02c020068c9c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1636,11 +1636,10 @@ static int intel_dp_get_slice_height(int vactive)
return 2;
 }
 
-static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
+static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
   struct intel_crtc_state *crtc_state)
 {
-   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+   struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct drm_dsc_config *vdsc_cfg = _state->dsc.config;
u8 line_buf_depth;
int ret;
@@ -1661,17 +1660,17 @@ static int intel_dp_dsc_compute_params(struct 
intel_encoder *encoder,
return ret;
 
vdsc_cfg->dsc_version_major =
-   (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+   (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
vdsc_cfg->dsc_version_minor =
min(intel_dp_source_dsc_version_minor(i915),
-   intel_dp_sink_dsc_version_minor(intel_dp->dsc_dpcd));
+   intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
if (vdsc_cfg->convert_rgb)
vdsc_cfg->convert_rgb =
-   intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - 
DP_DSC_SUPPORT] &
+   connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - 
DP_DSC_SUPPORT] &
DP_DSC_RGB;
 
-   line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
+   line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd);
if (!line_buf_depth) {
drm_dbg_kms(>drm,
"DSC Sink Line Buffer Depth invalid\n");
@@ -1686,7 +1685,7 @@ static int intel_dp_dsc_compute_params(struct 
intel_encoder *encoder,
DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
 
vdsc_cfg->block_pred_enable =
-   intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - 
DP_DSC_SUPPORT] &
+   connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - 
DP_DSC_SUPPORT] &
DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
 
return drm_dsc_compute_rc_parameters(vdsc_cfg);
@@ -2182,7 +2181,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
pipe_config->dsc.dsc_split = true;
 
-   ret = intel_dp_dsc_compute_params(_port->base, pipe_config);
+   ret = intel_dp_dsc_compute_params(connector, pipe_config);
if (ret < 0) {
drm_dbg_kms(_priv->drm,
"Cannot compute valid DSC parameters for Input Bpp 
= %d "
-- 
2.39.2

[Intel-gfx] [PATCH 12/19] drm/i915/dp: Pass only the required DSC DPCD to intel_dp_sink_dsc_version_minor()

[Imre Deak]

intel_dp_sink_dsc_version_minor() only requires the DSC DPCD, so pass
only this to the function.

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index eee7eac5e8e9c..d08a206cb1237 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1608,9 +1608,9 @@ static int intel_dp_source_dsc_version_minor(struct 
drm_i915_private *i915)
return DISPLAY_VER(i915) >= 14 ? 2 : 1;
 }
 
-static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
+static int intel_dp_sink_dsc_version_minor(const u8 
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
 {
-   return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 
DP_DSC_MINOR_MASK) >>
+   return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
DP_DSC_MINOR_SHIFT;
 }
 
@@ -1665,7 +1665,7 @@ static int intel_dp_dsc_compute_params(struct 
intel_encoder *encoder,
 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
vdsc_cfg->dsc_version_minor =
min(intel_dp_source_dsc_version_minor(i915),
-   intel_dp_sink_dsc_version_minor(intel_dp));
+   intel_dp_sink_dsc_version_minor(intel_dp->dsc_dpcd));
if (vdsc_cfg->convert_rgb)
vdsc_cfg->convert_rgb =
intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - 
DP_DSC_SUPPORT] &
@@ -1707,7 +1707,7 @@ static bool intel_dp_dsc_supports_format(struct intel_dp 
*intel_dp,
break;
case INTEL_OUTPUT_FORMAT_YCBCR420:
if (min(intel_dp_source_dsc_version_minor(i915),
-   intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
+   intel_dp_sink_dsc_version_minor(intel_dp->dsc_dpcd)) < 
2)
return false;
sink_dsc_format = DP_DSC_YCbCr420_Native;
break;
-- 
2.39.2

[Intel-gfx] [PATCH 14/19] drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_supports_format()

[Imre Deak]

Use the connector's DSC DPCD capabilities in
intel_dp_dsc_supports_format().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 02c020068c9c0..846a25a85d6b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1691,10 +1691,10 @@ static int intel_dp_dsc_compute_params(const struct 
intel_connector *connector,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
 }
 
-static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
+static bool intel_dp_dsc_supports_format(const struct intel_connector 
*connector,
 enum intel_output_format output_format)
 {
-   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+   struct drm_i915_private *i915 = to_i915(connector->base.dev);
u8 sink_dsc_format;
 
switch (output_format) {
@@ -1706,7 +1706,7 @@ static bool intel_dp_dsc_supports_format(struct intel_dp 
*intel_dp,
break;
case INTEL_OUTPUT_FORMAT_YCBCR420:
if (min(intel_dp_source_dsc_version_minor(i915),
-   intel_dp_sink_dsc_version_minor(intel_dp->dsc_dpcd)) < 
2)
+   
intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
return false;
sink_dsc_format = DP_DSC_YCbCr420_Native;
break;
@@ -1714,7 +1714,7 @@ static bool intel_dp_dsc_supports_format(struct intel_dp 
*intel_dp,
return false;
}
 
-   return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, 
sink_dsc_format);
+   return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, 
sink_dsc_format);
 }
 
 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
@@ -2124,7 +2124,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(connector, pipe_config))
return -EINVAL;
 
-   if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
+   if (!intel_dp_dsc_supports_format(connector, 
pipe_config->output_format))
return -EINVAL;
 
/*
-- 
2.39.2

[Intel-gfx] [PATCH 11/19] drm/i915/dp: Pass only the required i915 to intel_dp_source_dsc_version_minor()

[Imre Deak]

intel_dp_source_dsc_version_minor() only requires the i915 pointer, so pass
only this to the function.

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1bb00ac655c78..eee7eac5e8e9c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1603,10 +1603,8 @@ int intel_dp_dsc_compute_max_bpp(const struct 
intel_connector *connector,
return 0;
 }
 
-static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
+static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
 {
-   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-
return DISPLAY_VER(i915) >= 14 ? 2 : 1;
 }
 
@@ -1666,7 +1664,7 @@ static int intel_dp_dsc_compute_params(struct 
intel_encoder *encoder,
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
vdsc_cfg->dsc_version_minor =
-   min(intel_dp_source_dsc_version_minor(intel_dp),
+   min(intel_dp_source_dsc_version_minor(i915),
intel_dp_sink_dsc_version_minor(intel_dp));
if (vdsc_cfg->convert_rgb)
vdsc_cfg->convert_rgb =
@@ -1697,6 +1695,7 @@ static int intel_dp_dsc_compute_params(struct 
intel_encoder *encoder,
 static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
 enum intel_output_format output_format)
 {
+   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 sink_dsc_format;
 
switch (output_format) {
@@ -1707,7 +1706,7 @@ static bool intel_dp_dsc_supports_format(struct intel_dp 
*intel_dp,
sink_dsc_format = DP_DSC_YCbCr444;
break;
case INTEL_OUTPUT_FORMAT_YCBCR420:
-   if (min(intel_dp_source_dsc_version_minor(intel_dp),
+   if (min(intel_dp_source_dsc_version_minor(i915),
intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
return false;
sink_dsc_format = DP_DSC_YCbCr420_Native;
-- 
2.39.2

[Intel-gfx] [PATCH 15/19] drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_get_slice_count()

[Imre Deak]

Use the connector's DSC DPCD capabilities in
intel_dp_dsc_get_slice_count().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
 drivers/gpu/drm/i915/display/intel_dp.h |  2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 846a25a85d6b6..7449ff145a842 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -823,11 +823,11 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct 
drm_i915_private *i915,
return bits_per_pixel;
 }
 
-u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
int mode_clock, int mode_hdisplay,
bool bigjoiner)
 {
-   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+   struct drm_i915_private *i915 = to_i915(connector->base.dev);
u8 min_slice_count, i;
int max_slice_width;
 
@@ -845,7 +845,7 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
min_slice_count = max_t(u8, min_slice_count, 2);
 
-   max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
+   max_slice_width = 
drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
drm_dbg_kms(>drm,
"Unsupported slice width %d by DP DSC Sink 
device\n",
@@ -862,7 +862,7 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 
if (test_slice_count >
-   drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
+   drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 
false))
break;
 
/* big joiner needs small joiner to be enabled */
@@ -1238,7 +1238,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,

output_format,
pipe_bpp, 
64);
dsc_slice_count =
-   intel_dp_dsc_get_slice_count(intel_dp,
+   intel_dp_dsc_get_slice_count(connector,
 target_clock,
 mode->hdisplay,
 bigjoiner);
@@ -2161,7 +2161,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
u8 dsc_dp_slice_count;
 
dsc_dp_slice_count =
-   intel_dp_dsc_get_slice_count(intel_dp,
+   intel_dp_dsc_get_slice_count(connector,
 adjusted_mode->crtc_clock,
 
adjusted_mode->crtc_hdisplay,
 
pipe_config->bigjoiner_pipes);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h 
b/drivers/gpu/drm/i915/display/intel_dp.h
index af87aa2a5ed67..51edb587e4d24 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -125,7 +125,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct 
drm_i915_private *i915,
enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
-u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 303734ab7ef4e..115d4d8870b03 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1014,7 +1014,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
*connector,

INTEL_OUTPUT_FORMAT_RGB,
pipe_bpp, 
64);
dsc_slice_count =
-   intel_dp_dsc_get_slice_count(intel_dp,
+   intel_dp_dsc_get_slice_count(intel_connector,
 target_clock,
  

[Intel-gfx] [PATCH 09/19] drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_max_sink_compressed_bppx16()

[Imre Deak]

Use the connector's DSC DPCD capabilities in
intel_dp_dsc_max_sink_compressed_bppx16().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 437bd972fb040..ff4090a602b4b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1767,11 +1767,11 @@ static int dsc_compute_link_config(struct intel_dp 
*intel_dp,
 }
 
 static
-u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
+u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector 
*connector,
struct intel_crtc_state 
*pipe_config,
int bpc)
 {
-   u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd);
+   u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
 
if (max_bppx16)
return max_bppx16;
@@ -1810,11 +1810,11 @@ static int dsc_sink_min_compressed_bpp(struct 
intel_crtc_state *pipe_config)
return 0;
 }
 
-static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+static int dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
   struct intel_crtc_state *pipe_config,
   int bpc)
 {
-   return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
+   return intel_dp_dsc_max_sink_compressed_bppx16(connector,
   pipe_config, bpc) >> 4;
 }
 
@@ -1913,6 +1913,7 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 }
 
 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+ const struct intel_connector *connector,
  struct intel_crtc_state *pipe_config,
  struct link_config_limits *limits,
  int pipe_bpp,
@@ -1930,7 +1931,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp 
*intel_dp,
dsc_min_bpp = max(dsc_min_bpp, 
to_bpp_int_roundup(limits->link.min_bpp_x16));
 
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
-   dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, 
pipe_bpp / 3);
+   dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, 
pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) 
: dsc_src_max_bpp;
 
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, 
adjusted_mode->clock,
@@ -2002,6 +2003,8 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp 
*intel_dp,
 int timeslots)
 {
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+   const struct intel_connector *connector =
+   to_intel_connector(conn_state->connector);
u8 max_req_bpc = conn_state->max_requested_bpc;
u8 dsc_max_bpc, dsc_max_bpp;
u8 dsc_min_bpc, dsc_min_bpp;
@@ -2012,7 +2015,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp 
*intel_dp,
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
 
if (forced_bpp) {
-   ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+   ret = dsc_compute_compressed_bpp(intel_dp, connector, 
pipe_config,
 limits, forced_bpp, timeslots);
if (ret == 0) {
pipe_config->pipe_bpp = forced_bpp;
@@ -2041,7 +2044,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp 
*intel_dp,
break;
if (pipe_bpp > dsc_max_bpp)
continue;
-   ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+   ret = dsc_compute_compressed_bpp(intel_dp, connector, 
pipe_config,
 limits, pipe_bpp, timeslots);
if (ret == 0) {
pipe_config->pipe_bpp = pipe_bpp;
@@ -2088,7 +2091,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp 
*intel_dp,
dsc_min_bpp = max(dsc_min_bpp, 
to_bpp_int_roundup(limits->link.min_bpp_x16));
 
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
-   dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, 
pipe_bpp / 3);
+   dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, 
pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) 
: dsc_src_max_bpp;
dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
 
-- 
2.39.2

[Intel-gfx] [PATCH 10/19] drm/i915/dp: Pass connector DSC DPCD to drm_dp_dsc_sink_supported_input_bpcs()

[Imre Deak]

Use the connector's DSC DPCD capabilities in
drm_dp_dsc_sink_supported_input_bpcs().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +---
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index ff4090a602b4b..1bb00ac655c78 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2037,7 +2037,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp 
*intel_dp,
 * Get the maximum DSC bpc that will be supported by any valid
 * link configuration and compressed bpp.
 */
-   num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, 
dsc_bpc);
+   num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 
dsc_bpc);
for (i = 0; i < num_bpc; i++) {
pipe_bpp = dsc_bpc[i] * 3;
if (pipe_bpp < dsc_min_bpp)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3ff429c30f300..303734ab7ef4e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -185,8 +185,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct 
intel_encoder *encoder,
struct drm_connector_state 
*conn_state,
struct link_config_limits 
*limits)
 {
-   struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
-   struct intel_dp *intel_dp = _mst->primary->dp;
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
@@ -209,7 +207,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct 
intel_encoder *encoder,
max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
min_bpp = limits->pipe.min_bpp;
 
-   num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+   num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
   dsc_bpc);
 
drm_dbg_kms(>drm, "DSC Source supported min bpp %d max bpp %d\n",
-- 
2.39.2

[Intel-gfx] [PATCH 07/19] drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_fec()

[Imre Deak]

Use the connector's DSC DPCD capabilities in intel_dp_supports_fec().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 00f5fecdbf386..8450856e5618d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1370,10 +1370,11 @@ static bool intel_dp_source_supports_fec(struct 
intel_dp *intel_dp,
 }
 
 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_connector *connector,
  const struct intel_crtc_state *pipe_config)
 {
return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
-   drm_dp_sink_supports_fec(intel_dp->fec_capable);
+   drm_dp_sink_supports_fec(connector->dp.fec_capability);
 }
 
 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
@@ -2110,12 +2111,14 @@ int intel_dp_dsc_compute_config(struct intel_dp 
*intel_dp,
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+   const struct intel_connector *connector =
+   to_intel_connector(conn_state->connector);
const struct drm_display_mode *adjusted_mode =
_config->hw.adjusted_mode;
int ret;
 
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
-   intel_dp_supports_fec(intel_dp, pipe_config);
+   intel_dp_supports_fec(intel_dp, connector, pipe_config);
 
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
-- 
2.39.2

[Intel-gfx] [PATCH 08/19] drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_dsc()

[Imre Deak]

Use the connector's DSC DPCD capabilities in intel_dp_supports_dsc().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8450856e5618d..437bd972fb040 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1377,14 +1377,14 @@ static bool intel_dp_supports_fec(struct intel_dp 
*intel_dp,
drm_dp_sink_supports_fec(connector->dp.fec_capability);
 }
 
-static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
+static bool intel_dp_supports_dsc(const struct intel_connector *connector,
  const struct intel_crtc_state *crtc_state)
 {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && 
!crtc_state->fec_enable)
return false;
 
return intel_dsc_source_support(crtc_state) &&
-   drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
+   drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
 }
 
 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
@@ -2120,7 +2120,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
intel_dp_supports_fec(intel_dp, connector, pipe_config);
 
-   if (!intel_dp_supports_dsc(intel_dp, pipe_config))
+   if (!intel_dp_supports_dsc(connector, pipe_config))
return -EINVAL;
 
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
-- 
2.39.2

[Intel-gfx] [PATCH 05/19] drm/i915/dp: Use connector DSC DPCD in i915_dsc_fec_support_show()

[Imre Deak]

Use the connector's DSC DPCD capabilities in i915_dsc_fec_support_show()
instead of the version stored in the encoder. Atm the two are identical,
but a follow-up patch will store the (MST) connector specific version
in the connector.

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 834a8e50ea4fb..2836826f8c05f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1234,19 +1234,19 @@ static int i915_dsc_fec_support_show(struct seq_file 
*m, void *data)
seq_printf(m, "DSC_Enabled: %s\n",
   str_yes_no(crtc_state->dsc.compression_enable));
seq_printf(m, "DSC_Sink_Support: %s\n",
-  
str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
+  
str_yes_no(drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)));
seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s 
YCBCR420: %s YCBCR444: %s\n",
-  
str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+  
str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd,
  
DP_DSC_RGB)),
-  
str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+  
str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd,
  
DP_DSC_YCbCr420_Native)),
-  
str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+  
str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd,
  
DP_DSC_YCbCr444)));
seq_printf(m, "Force_DSC_Enable: %s\n",
   str_yes_no(intel_dp->force_dsc_en));
if (!intel_dp_is_edp(intel_dp))
seq_printf(m, "FEC_Sink_Support: %s\n",
-  
str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable)));
+  
str_yes_no(drm_dp_sink_supports_fec(connector->dp.fec_capability)));
} while (try_again);
 
drm_modeset_drop_locks();
-- 
2.39.2

[Intel-gfx] [PATCH 06/19] drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_max_bpp()

[Imre Deak]

Use the connector's DSC DPCD capabilities in intel_dp_dsc_compute_max_bpp()
instead of the version stored in the encoder.

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 13 -
 drivers/gpu/drm/i915/display/intel_dp.h |  3 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 +-
 3 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6e6b3fe593453..00f5fecdbf386 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1215,7 +1215,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 * TBD pass the connector BPC,
 * for now U8_MAX so that max BPC on that platform would be 
picked
 */
-   pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
+   pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
 
/*
 * Output bpp is stored in 6.4 format so right shift by 4 to 
get the
@@ -1577,9 +1577,10 @@ u8 intel_dp_dsc_max_src_input_bpc(struct 
drm_i915_private *i915)
return 0;
 }
 
-int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
+u8 max_req_bpc)
 {
-   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+   struct drm_i915_private *i915 = to_i915(connector->base.dev);
int i, num_bpc;
u8 dsc_bpc[3] = {0};
u8 dsc_max_bpc;
@@ -1591,7 +1592,7 @@ int intel_dp_dsc_compute_max_bpp(struct intel_dp 
*intel_dp, u8 max_req_bpc)
 
dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
 
-   num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+   num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
   dsc_bpc);
for (i = 0; i < num_bpc; i++) {
if (dsc_max_bpc >= dsc_bpc[i])
@@ -2056,6 +2057,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp 
*intel_dp,
  struct link_config_limits *limits)
 {
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+   struct intel_connector *connector =
+   to_intel_connector(conn_state->connector);
int pipe_bpp, forced_bpp;
int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
@@ -2068,7 +2071,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp 
*intel_dp,
int max_bpc = min(limits->pipe.max_bpp / 3, 
(int)conn_state->max_requested_bpc);
 
/* For eDP use max bpp that can be supported with DSC. */
-   pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, max_bpc);
+   pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, 
pipe_bpp)) {
drm_dbg_kms(>drm,
"Computed BPC is not in DSC BPC limits\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h 
b/drivers/gpu/drm/i915/display/intel_dp.h
index bd9cb9680b4cd..af87aa2a5ed67 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -116,7 +116,8 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
   struct intel_crtc_state *crtc_state,
   unsigned int type);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
-int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
+u8 dsc_max_bpc);
 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e01f669d2c8a1..3ff429c30f300 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1003,7 +1003,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
*connector,
 * TBD pass the connector BPC,
 * for now U8_MAX so that max BPC on that platform would be 
picked
 */
-   int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
+   int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, 
U8_MAX);
 
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_compressed_bpp =
-- 
2.39.2

[Intel-gfx] [PATCH 04/19] drm/i915/dp: Use i915/intel connector local variables in i915_dsc_fec_support_show()

[Imre Deak]

Cahce the i915 specific device and connector pointers in
i915_dsc_fec_support_show().

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index fbe75d47a1654..834a8e50ea4fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1191,8 +1191,8 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
 
 static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 {
-   struct drm_connector *connector = m->private;
-   struct drm_device *dev = connector->dev;
+   struct intel_connector *connector = to_intel_connector(m->private);
+   struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct drm_crtc *crtc;
struct intel_dp *intel_dp;
struct drm_modeset_acquire_ctx ctx;
@@ -1204,7 +1204,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, 
void *data)
 
do {
try_again = false;
-   ret = drm_modeset_lock(>mode_config.connection_mutex,
+   ret = drm_modeset_lock(>drm.mode_config.connection_mutex,
   );
if (ret) {
if (ret == -EDEADLK && !drm_modeset_backoff()) {
@@ -1213,8 +1213,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, 
void *data)
}
break;
}
-   crtc = connector->state->crtc;
-   if (connector->status != connector_status_connected || !crtc) {
+   crtc = connector->base.state->crtc;
+   if (connector->base.status != connector_status_connected || 
!crtc) {
ret = -ENODEV;
break;
}
@@ -1229,7 +1229,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, 
void *data)
} else if (ret) {
break;
}
-   intel_dp = intel_attached_dp(to_intel_connector(connector));
+   intel_dp = intel_attached_dp(connector);
crtc_state = to_intel_crtc_state(crtc->state);
seq_printf(m, "DSC_Enabled: %s\n",
   str_yes_no(crtc_state->dsc.compression_enable));
-- 
2.39.2

[Intel-gfx] [PATCH 03/19] drm/i915/dp_mst: Set connector DSC capabilities and decompression AUX

[Imre Deak]

Similarly to eDP and SST-DP connectors read out the DSC capabilities for
MST connectors as well. Atm these will match the root port's DSC caps
and only used after a follow-up change enables the decompression for
each stream separately (vs. the current way of enabling it only globally
in the first branch device downstream of the root port).

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c |  4 ++--
 drivers/gpu/drm/i915/display/intel_dp.h |  3 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +
 3 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index c7dd65a27a1b0..6e6b3fe593453 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3467,8 +3467,8 @@ bool intel_dp_get_colorimetry_status(struct intel_dp 
*intel_dp)
return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
 }
 
-static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp,
- struct intel_connector *connector)
+void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp,
+  struct intel_connector *connector)
 {
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h 
b/drivers/gpu/drm/i915/display/intel_dp.h
index 2cf3681bac64a..bd9cb9680b4cd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -162,4 +162,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp 
*intel_dp,
bool dsc,
struct link_config_limits *limits);
 
+void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp,
+  struct intel_connector *connector);
+
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 73e3977364632..e01f669d2c8a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1126,6 +1126,21 @@ static int intel_dp_mst_add_properties(struct intel_dp 
*intel_dp,
return drm_connector_set_path_property(connector, pathprop);
 }
 
+static void
+intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
+ struct intel_connector *connector)
+{
+   u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
+
+   if (!connector->dp.dsc_decompression_aux)
+   return;
+
+   if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, 
dpcd_caps) < 0)
+   return;
+
+   intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], intel_dp, connector);
+}
+
 static struct drm_connector *intel_dp_add_mst_connector(struct 
drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port 
*port,
const char *pathprop)
@@ -1159,6 +1174,14 @@ static struct drm_connector 
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
 
drm_connector_helper_add(connector, 
_dp_mst_connector_helper_funcs);
 
+   /*
+* TODO: set the AUX for the actual MST port decompressing the stream.
+* At the moment the driver only supports enabling this globally in the
+* first downstream MST branch, via intel_dp's (root port) AUX.
+*/
+   intel_connector->dp.dsc_decompression_aux = _dp->aux;
+   intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, 
intel_connector);
+
for_each_pipe(dev_priv, pipe) {
struct drm_encoder *enc =
_dp->mst_encoders[pipe]->base.base;
-- 
2.39.2

[Intel-gfx] [PATCH 02/19] drm/i915/dp: Store DSC DPCD capabilities in the connector

[Imre Deak]

In an MST topology the DSC capabilities are specific to each connector,
retrieved either from the sink if it decompresses the stream, or from a
branch device between the source and the sink in case this branch device
does the decompression. Accordingly each connector needs to cache its
own DSC DPCD and FEC capabilities, along with the AUX device through
which the decompression can be enabled. This patch prepares for that by
storing the capabilities and the DSC AUX device in the connector, for
now these just matching the version stored in intel_dp. The follow-up
patches will convert all users to look up these in the connector instead
of intel_dp, after which the intel_dp copies are removed.

Signed-off-by: Imre Deak 
---
 .../drm/i915/display/intel_display_types.h|  6 +++
 drivers/gpu/drm/i915/display/intel_dp.c   | 53 +--
 2 files changed, 43 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8d8b2f8d37a99..d6600079bcf74 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -620,6 +620,12 @@ struct intel_connector {
 
struct intel_dp *mst_port;
 
+   struct {
+   struct drm_dp_aux *dsc_decompression_aux;
+   u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+   u8 fec_capability;
+   } dp;
+
/* Work struct to schedule a uevent on link train failure */
struct work_struct modeset_retry_work;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1bd11f9e308c1..c7dd65a27a1b0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3467,7 +3467,8 @@ bool intel_dp_get_colorimetry_status(struct intel_dp 
*intel_dp)
return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
 }
 
-static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp)
+static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp,
+ struct intel_connector *connector)
 {
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
@@ -3475,35 +3476,46 @@ static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, 
struct intel_dp *intel_dp)
 * Clear the cached register set to avoid using stale values
 * for the sinks that do not support DSC.
 */
-   memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+   memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
 
/* Clear fec_capable to avoid using stale values */
-   intel_dp->fec_capable = 0;
+   connector->dp.fec_capability = 0;
 
/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
if ((intel_dp_is_edp(intel_dp) && dpcd_rev >= DP_EDP_14) ||
(!intel_dp_is_edp(intel_dp) && dpcd_rev >= 0x14)) {
-   if (drm_dp_dpcd_read(_dp->aux, DP_DSC_SUPPORT,
-intel_dp->dsc_dpcd,
-sizeof(intel_dp->dsc_dpcd)) < 0)
+   if (drm_dp_dpcd_read(connector->dp.dsc_decompression_aux,
+DP_DSC_SUPPORT,
+connector->dp.dsc_dpcd,
+sizeof(connector->dp.dsc_dpcd)) < 0)
drm_err(>drm,
"Failed to read DPCD register 0x%x\n",
DP_DSC_SUPPORT);
 
drm_dbg_kms(>drm, "DSC DPCD: %*ph\n",
-   (int)sizeof(intel_dp->dsc_dpcd),
-   intel_dp->dsc_dpcd);
+   (int)sizeof(connector->dp.dsc_dpcd),
+   connector->dp.dsc_dpcd);
 
/* FEC is supported only on DP 1.4 */
if (!intel_dp_is_edp(intel_dp) &&
-   drm_dp_dpcd_readb(_dp->aux, DP_FEC_CAPABILITY,
- _dp->fec_capable) < 0)
+   drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux,
+ DP_FEC_CAPABILITY,
+ >dp.fec_capability) < 0)
drm_err(>drm,
"Failed to read FEC DPCD register\n");
 
drm_dbg_kms(>drm, "FEC CAPABILITY: %x\n",
-   intel_dp->fec_capable);
+   connector->dp.fec_capability);
}
+
+   /*
+* TODO: remove the following intel_dp copies once all users
+* are converted to look up DSC DPCD/FEC capability via the
+* connector.
+*/
+   memcpy(intel_dp->dsc_dpcd, connector->dp.dsc_dpcd,
+  sizeof(intel_dp->dsc_dpcd));
+   intel_dp->fec_capable = connector->dp.fec_capability;
 }
 
 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,

[Intel-gfx] [PATCH 00/19] drm/i915: Store DSC DPCD capabilities in the connector

[Imre Deak]

This patchset moves the DSC DPCD capabilities from the encoder
(intel_dp) to the connector. This is required since in an MST topology
each connector has its own version of these capabilities, allowing
to configure/enable the DSC decompression for each stream separately.

The changes are needed for a follow-up patchset, fixing the MST DSC
functionality, making it also possible to enable the BW management on
MST links. The follow-up changes are based on patches 12-25 in

https://lore.kernel.org/all/20230914192659.757475-1-imre.d...@intel.com

Imre Deak (19):
  drm/i915/dp: Sanitize DPCD revision check in
intel_dp_get_dsc_sink_cap()
  drm/i915/dp: Store DSC DPCD capabilities in the connector
  drm/i915/dp_mst: Set connector DSC capabilities and decompression AUX
  drm/i915/dp: Use i915/intel connector local variables in
i915_dsc_fec_support_show()
  drm/i915/dp: Use connector DSC DPCD in i915_dsc_fec_support_show()
  drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_max_bpp()
  drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_fec()
  drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_dsc()
  drm/i915/dp: Use connector DSC DPCD in
intel_dp_dsc_max_sink_compressed_bppx16()
  drm/i915/dp: Pass connector DSC DPCD to
drm_dp_dsc_sink_supported_input_bpcs()
  drm/i915/dp: Pass only the required i915 to
intel_dp_source_dsc_version_minor()
  drm/i915/dp: Pass only the required DSC DPCD to
intel_dp_sink_dsc_version_minor()
  drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_params()
  drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_supports_format()
  drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_get_slice_count()
  drm/i915/dp: Use connector DSC DPCD in intel_dp_mode_valid()
  drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_config()
  drm/i915/dp_mst: Use connector DSC DPCD in
intel_dp_mst_mode_valid_ctx()
  drm/i915/dp: Remove unused DSC caps from intel_dp

 .../drm/i915/display/intel_display_debugfs.c  |  22 +--
 .../drm/i915/display/intel_display_types.h|   8 +-
 drivers/gpu/drm/i915/display/intel_dp.c   | 154 ++
 drivers/gpu/drm/i915/display/intel_dp.h   |   8 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  35 +++-
 5 files changed, 136 insertions(+), 91 deletions(-)

-- 
2.39.2

[Intel-gfx] [PATCH 01/19] drm/i915/dp: Sanitize DPCD revision check in intel_dp_get_dsc_sink_cap()

[Imre Deak]

Check only the eDP or the DP specific DPCD revision depending on the
sink type. Pass the corresponding revision to the function, which allows
getting the DSC caps of a branch device (in an MST topology, which has
its own DPCD and so DPCD revision).

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0ef7cb8134b66..1bd11f9e308c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3467,7 +3467,7 @@ bool intel_dp_get_colorimetry_status(struct intel_dp 
*intel_dp)
return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
 }
 
-static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
+static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp)
 {
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
@@ -3481,8 +3481,8 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp 
*intel_dp)
intel_dp->fec_capable = 0;
 
/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
-   if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
-   intel_dp->edp_dpcd[0] >= DP_EDP_14) {
+   if ((intel_dp_is_edp(intel_dp) && dpcd_rev >= DP_EDP_14) ||
+   (!intel_dp_is_edp(intel_dp) && dpcd_rev >= 0x14)) {
if (drm_dp_dpcd_read(_dp->aux, DP_DSC_SUPPORT,
 intel_dp->dsc_dpcd,
 sizeof(intel_dp->dsc_dpcd)) < 0)
@@ -3674,7 +3674,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
 
/* Read the eDP DSC DPCD registers */
if (HAS_DSC(dev_priv))
-   intel_dp_get_dsc_sink_cap(intel_dp);
+   intel_dp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
+ intel_dp);
 
/*
 * If needed, program our source OUI so we can make various 
Intel-specific AUX services
@@ -5384,7 +5385,8 @@ intel_dp_detect(struct drm_connector *connector,
 
/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
if (HAS_DSC(dev_priv))
-   intel_dp_get_dsc_sink_cap(intel_dp);
+   intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
+ intel_dp);
 
intel_dp_configure_mst(intel_dp);
 
-- 
2.39.2

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Remove xehpsdv support

[Andi Shyti]

Hi Tvrtko,

On Fri, Oct 06, 2023 at 09:31:03AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> XeHP SDV was a pre-production hardware used to bring up ATS and was not
> generally available. Since latter was since explicitly added, there is no

mmhh?

> need to keep the code for the former around.
> 
> Signed-off-by: Tvrtko Ursulin 

didn't spot anything odd... looks good:

Reviewed-by: Andi Shyti  

Andi

[Intel-gfx] [PATCH] drm/print: Add drm_dbg_ratelimited

[Andi Shyti]

From: Nirmoy Das 

Add a function for ratelimitted debug print.

Cc: Maarten Lankhorst 
Cc: Maxime Ripard 
Cc: Thomas Zimmermann 
Cc: David Airlie 
Cc: Daniel Vetter 
Reviewed-by: Matthew Auld 
Reviewed-by: Andi Shyti 
Signed-off-by: Nirmoy Das 
Signed-off-by: Andi Shyti 
---
 include/drm/drm_print.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index a93a387f8a1a..ad77ac4b6808 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -602,6 +602,9 @@ void __drm_err(const char *format, ...);
drm_dev_printk(drm_ ? drm_->dev : NULL, KERN_DEBUG, fmt, ## 
__VA_ARGS__);   \
 })
 
+#define drm_dbg_ratelimited(drm, fmt, ...) \
+   __DRM_DEFINE_DBG_RATELIMITED(DRIVER, drm, fmt, ## __VA_ARGS__)
+
 #define drm_dbg_kms_ratelimited(drm, fmt, ...) \
__DRM_DEFINE_DBG_RATELIMITED(KMS, drm, fmt, ## __VA_ARGS__)
 
-- 
2.40.1

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Display state checker cleanup (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Display state checker cleanup (rev3)
URL   : https://patchwork.freedesktop.org/series/124616/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13719_full -> Patchwork_124616v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_124616v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_124616v3_full, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_124616v3_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hangcheck:
- shard-tglu: [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-tglu-2/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124616v3/shard-tglu-8/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3:
- shard-dg2:  [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-dg2-6/igt@kms_flip@flip-vs-suspend-interrupti...@a-hdmi-a3.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124616v3/shard-dg2-5/igt@kms_flip@flip-vs-suspend-interrupti...@a-hdmi-a3.html

  
New tests
-

  New tests have been introduced between CI_DRM_13719_full and 
Patchwork_124616v3_full:

### New IGT tests (4) ###

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@d-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_124616v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@crc32:
- shard-dg1:  NOTRUN -> [SKIP][5] ([i915#6230])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124616v3/shard-dg1-18/igt@api_intel...@crc32.html

  * igt@drm_fdinfo@busy@vcs1:
- shard-dg1:  NOTRUN -> [SKIP][6] ([i915#8414]) +4 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124616v3/shard-dg1-18/igt@drm_fdinfo@b...@vcs1.html

  * igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2:  NOTRUN -> [SKIP][7] ([i915#8414]) +10 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124616v3/shard-dg2-2/igt@drm_fdinfo@most-busy-check-...@bcs0.html

  * igt@gem_ccs@ctrl-surf-copy:
- shard-mtlp: NOTRUN -> [SKIP][8] ([i915#3555])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124616v3/shard-mtlp-4/igt@gem_...@ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
- shard-dg2:  [PASS][9] -> [INCOMPLETE][10] ([i915#7297])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-dg2-11/igt@gem_ccs@suspend-res...@linear-compressed-compfmt0-lmem0-lmem0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124616v3/shard-dg2-6/igt@gem_ccs@suspend-res...@linear-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_create@create-ext-cpu-access-big:
- shard-dg2:  NOTRUN -> [INCOMPLETE][11] ([i915#9364])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124616v3/shard-dg2-11/igt@gem_cre...@create-ext-cpu-access-big.html

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl:  [PASS][12] -> [FAIL][13] ([i915#6268])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-rkl-2/igt@gem_ctx_e...@basic-nohangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124616v3/shard-rkl-7/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-dg1:  [PASS][14] -> [FAIL][15] ([fdo#103375]) +2 other 
tests fail
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-dg1-19/igt@gem_ctx_isolation@preservation...@vcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124616v3/shard-dg1-15/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
- shard-mtlp: [PASS][16] -> [ABORT][17] ([i915#9414])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13719/shard-mtlp-3/igt@gem_ctx_persistence@legacy-engines-h...@blt.html
   [17]: 

Re: [Intel-gfx] [PATCH v7 2/5] drm/i915: Define and use GuC and CTB TLB invalidation routines

[Tvrtko Ursulin]

On 06/10/2023 11:11, Tvrtko Ursulin wrote:


Hi,


Andi asked me to summarize what I think is unaddressed review feedback 
so far in order to consolidate and enable hopefully things to move 
forward. So I will try to re-iterate the comments and questions below.


But also note that there is a bunch of new valid comments from John 
against v7 which I will not repeat.


On 05/10/2023 20:35, Jonathan Cavitt wrote:

From: Prathap Kumar Valsan 

The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation.  We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back to GT invalidation when the GuC is
disabled.
The invalidation is done by sending a request directly to the GuC
tlb_lookup that invalidates the table.  The invalidation is submitted as
a wait request and is performed in the CT event handler.  This means we
cannot perform this TLB invalidation path if the CT is not enabled.
If the request isn't fulfilled in two seconds, this would constitute
an error in the invalidation as that would constitute either a lost
request or a severe GuC overload.
The tlb_lookup table is allocated as an xarray because the set of
pending TLB invalidations may have no upper bound.  The consequence of
this is that all actions interfacing with this table need to use the
xarray functions, such as xa_alloc_cyclic_irq for array insertion.

With this new invalidation routine, we can perform GuC-based GGTT
invalidations.  GuC-based GGTT invalidation is incompatible with
MMIO invalidation so we should not perform MMIO invalidation when
GuC-based GGTT invalidation is expected.


On the commit message, I was asking that it describes the justification 
for the complexity patch adds with the wait queue management. It is 
non-trivial code, open-coded-almost-copy-of wait_token(), etc, so it 
needs explanation.


Today we have all threads serialize their invalidation under 
gt->tlb.invalidate_lock. With this patch that remains, but it allows a 
little bit of de-serialization in waiting. I suspect this is because 
with mmio i915 has direct access to invalidation, where with GuC the 
requests are competing for latency with other CT requests too (not 
invalidations).


Simpler patch could be doing the same as the GFP_ATOMIC fallback path in 
guc_send_invalidate_tlb - ie. serialize it all against one CT 
invalidation "slot". Are the gains of allowing multiple wait slots 
significant enough to warrant the complexity etc needs to be documented 
and the above problem space explained in the commit message.


Also, any gains from the invidual waiters are limited to 
ggtt->invalidate() callers right? Because the put_pages invalidations 
are serialized at the top-level in intel_gt_invalidate_tlb_full() anyway.


And how frequent or relevant are ggtt invalidations at runtime? It is 
just context creation and such, no (rings, contexts state)? Are page 
flips / framebuffers relevant too?


Question is whether a simpler scheme, with a single wait queue (no open 
coded wait_token(), xarray etc) and just waking up all waiters on 
processing CT done, where each waiters check the seqno and goes back to 
sleep if it's invalidation hasn't been completed yet, would be sufficient.


Regards,

Tvrtko




Signed-off-by: Prathap Kumar Valsan 
Signed-off-by: Bruce Chang 
Signed-off-by: Chris Wilson 
Signed-off-by: Umesh Nerlige Ramappa 
Signed-off-by: Jonathan Cavitt 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Fei Yang 
CC: Andi Shyti 
---
  drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 ++-
  drivers/gpu/drm/i915/gt/intel_tlb.c   |  14 +-
  .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 +++
  drivers/gpu/drm/i915/gt/uc/intel_guc.h    |  22 ++
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 211 +-
  7 files changed, 307 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c

index 4d7d88b92632b..18f23f27f1572 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -206,22 +206,38 @@ static void gen8_ggtt_invalidate(struct 
i915_ggtt *ggtt)
  intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, 
GFX_FLSH_CNTL_EN);

  }
+static void guc_ggtt_ct_invalidate(struct intel_gt *gt)
+{
+    struct intel_uncore *uncore = gt->uncore;
+    intel_wakeref_t wakeref;
+
+    with_intel_runtime_pm_if_active(uncore->rpm, wakeref) {
+    struct intel_guc *guc = >uc.guc;
+
+    intel_guc_invalidate_tlb(guc);
+    }
+}
+
  static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
  {
  struct drm_i915_private *i915 = ggtt->vm.i915;
+    struct intel_gt *gt;
-    gen8_ggtt_invalidate(ggtt);
-
-    if (GRAPHICS_VER(i915) >= 12) {
-    struct intel_gt *gt;
+    if 

[Intel-gfx] [PATCH 2/2] drm/i915: enable W=1 warnings by default

[Jani Nikula]

We enable a bunch more compiler warnings than the kernel
defaults. However, they've drifted to become a unique set of warnings,
and have increasingly fallen behind from the W=1 set.

Align with the W=1 warnings from scripts/Makefile.extrawarn for clarity,
by copy-pasting them with s/KBUILD_CFLAGS/subdir-ccflags-y/ to make it
easier to compare in the future.

Cc: Arnd Bergmann 
Cc: Nick Desaulniers 
Cc: Nathan Chancellor 
Cc: Masahiro Yamada 
Signed-off-by: Jani Nikula 

---

An alternative or future option would be to have Makefile.extrawarn
assign W=1 etc. flags to intermediate variables, say KBUILD_CFLAGS_W1,
like this:

KBUILD_CFLAGS_W1 += -Wextra -Wunused -Wno-unused-parameter
etc...

export KBUILD_CFLAGS_W1

ifneq ($(findstring 1, $(KBUILD_EXTRA_WARN)),)

KBUILD_CFLAGS += $(KBUILD_CFLAGS_W1)

else
etc...

and then drivers and subsystems could simply use:

subdir-ccflags-y += $(KBUILD_CFLAGS_W1)

to enable and remain up-to-date with W=1 warnings.
---
 drivers/gpu/drm/i915/Makefile | 33 ++---
 1 file changed, 18 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 623f81217442..0485157054fc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -3,22 +3,25 @@
 # Makefile for the drm device driver.  This driver provides support for the
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 
-# Add a set of useful warning flags and enable -Werror for CI to prevent
-# trivial mistakes from creeping in. We have to do this piecemeal as we reject
-# any patch that isn't warning clean, so turning on -Wextra (or W=1) we
-# need to filter out dubious warnings.  Still it is our interest
-# to keep running locally with W=1 C=1 until we are completely clean.
-#
-# Note the danger in using -Wextra is that when CI updates gcc we
-# will most likely get a sudden build breakage... Hopefully we will fix
-# new warnings before CI updates!
-subdir-ccflags-y := -Wextra
-subdir-ccflags-y += -Wno-unused-parameter
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-missing-field-initializers
-subdir-ccflags-y += -Wno-sign-compare
-subdir-ccflags-y += -Wno-shift-negative-value
+# Unconditionally enable W=1 warnings locally
+# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
+subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
+subdir-ccflags-y += -Wmissing-declarations
+subdir-ccflags-y += $(call cc-option, -Wrestrict)
+subdir-ccflags-y += -Wmissing-format-attribute
+subdir-ccflags-y += -Wmissing-prototypes
+subdir-ccflags-y += -Wold-style-definition
+subdir-ccflags-y += -Wmissing-include-dirs
 subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
+subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
+subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
+subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
+subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
+subdir-ccflags-y += $(call cc-option, -Wstringop-overflow)
+subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
+# --- end copy-paste
+
+# Enable -Werror in CI and development
 subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
 
 # Fine grained warnings disable
-- 
2.39.2

Re: [Intel-gfx] [PATCH] drm/i915/lnl: Remove watchdog timers for PSR

[Kahola, Mika]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Friday, October 6, 2023 3:29 PM
> To: Kahola, Mika 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/lnl: Remove watchdog timers for PSR
> 
> On Fri, Oct 06, 2023 at 02:42:10PM +0300, Mika Kahola wrote:
> > Currently we are not using watchdog timers for PSR/PSR2.
> > The patch disables these timers so they are not in use.
> 
> I can't figure out what you're saying here. What bspec seems to be saying is 
> that the max_sleep thing got nuked from the hw so we
> no longer need to mask it.

Well, my understanding was that we would need to remove these from the driver 
as these are irrelevant.

> 
> >
> > BSpec: 69895
> >
> > Signed-off-by: Mika Kahola 
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 24
> > +---
> >  1 file changed, 17 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 850b11f20285..13b58dceb2bf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -672,11 +672,15 @@ static void hsw_activate_psr1(struct intel_dp 
> > *intel_dp)
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> > u32 max_sleep_time = 0x1f;
> > -   u32 val = EDP_PSR_ENABLE;
> > +   u32 val = 0;
> >
> > -   val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> >
> > -   val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
> > +   if (DISPLAY_VER(dev_priv) < 20) {
> > +   val =  EDP_PSR_ENABLE;
> 
> That would mean you never enable PSR1 on lnl+
> 
> > +   val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
> > +   }
> > +
> > +   val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > if (IS_HASWELL(dev_priv))
> > val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> >
> > @@ -1398,10 +1402,16 @@ static void intel_psr_enable_source(struct intel_dp 
> > *intel_dp,
> >  * runtime_pm besides preventing  other hw tracking issues now we
> >  * can rely on frontbuffer tracking.
> >  */
> > -   mask = EDP_PSR_DEBUG_MASK_MEMUP |
> > -  EDP_PSR_DEBUG_MASK_HPD |
> > -  EDP_PSR_DEBUG_MASK_LPSP |
> > -  EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> > +   if (DISPLAY_VER(dev_priv) >= 20)
> > +   mask = EDP_PSR_DEBUG_MASK_MEMUP |
> > +  EDP_PSR_DEBUG_MASK_HPD |
> > +  EDP_PSR_DEBUG_MASK_LPSP;
> > +   else
> > +   mask = EDP_PSR_DEBUG_MASK_MEMUP |
> > +  EDP_PSR_DEBUG_MASK_HPD |
> > +  EDP_PSR_DEBUG_MASK_LPSP |
> > +  EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> 
> The hpd mask bit also seems gone now, though there is no explanation why it 
> disappeared.
> 
> > +
> >
> > /*
> >  * No separate pipe reg write mask on hsw/bdw, so have to unmask all
> > --
> > 2.34.1
> 
> --
> Ville Syrjälä
> Intel

[Intel-gfx] [PATCH 1/2] drm/i915: drop -Wall and related disables from cflags as redundant

[Jani Nikula]

The kernel top level Makefile, and recently scripts/Makefile.extrawarn,
have included -Wall, and the disables -Wno-format-security and
$(call cc-disable-warning,frame-address,) for a very long time. They're
redundant in our local subdir-ccflags-y and can be dropped.

Cc: Arnd Bergmann 
Cc: Nick Desaulniers 
Cc: Nathan Chancellor 
Cc: Masahiro Yamada 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/Makefile | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index dec78efa452a..623f81217442 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -5,22 +5,20 @@
 
 # Add a set of useful warning flags and enable -Werror for CI to prevent
 # trivial mistakes from creeping in. We have to do this piecemeal as we reject
-# any patch that isn't warning clean, so turning on -Wall -Wextra (or W=1) we
+# any patch that isn't warning clean, so turning on -Wextra (or W=1) we
 # need to filter out dubious warnings.  Still it is our interest
 # to keep running locally with W=1 C=1 until we are completely clean.
 #
-# Note the danger in using -Wall -Wextra is that when CI updates gcc we
+# Note the danger in using -Wextra is that when CI updates gcc we
 # will most likely get a sudden build breakage... Hopefully we will fix
 # new warnings before CI updates!
-subdir-ccflags-y := -Wall -Wextra
-subdir-ccflags-y += -Wno-format-security
+subdir-ccflags-y := -Wextra
 subdir-ccflags-y += -Wno-unused-parameter
 subdir-ccflags-y += -Wno-type-limits
 subdir-ccflags-y += -Wno-missing-field-initializers
 subdir-ccflags-y += -Wno-sign-compare
 subdir-ccflags-y += -Wno-shift-negative-value
 subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
-subdir-ccflags-y += $(call cc-disable-warning, frame-address)
 subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
 
 # Fine grained warnings disable
-- 
2.39.2

[Intel-gfx] [PATCH 0/2] drm/i915: align with W=1 warnings

[Jani Nikula]

Update i915 extra warnings to align with W=1 warnings.

Cc'ing some folks who have contributed to i915 warnings in the past. I'm
only running gcc 12 locally, so I may not hit all issues that other gcc
or clang versions might hit.

BR,
Jani.


Cc: Arnd Bergmann 
Cc: Nick Desaulniers 
Cc: Nathan Chancellor 
Cc: Masahiro Yamada 

Jani Nikula (2):
  drm/i915: drop -Wall and related disables from cflags as redundant
  drm/i915: enable W=1 warnings by default

 drivers/gpu/drm/i915/Makefile | 35 ++-
 1 file changed, 18 insertions(+), 17 deletions(-)

-- 
2.39.2

Re: [Intel-gfx] [PATCH] drm/i915/display: Reset message bus after each read/write operation

[Kahola, Mika]

> -Original Message-
> From: Sousa, Gustavo 
> Sent: Friday, October 6, 2023 2:57 PM
> To: Kahola, Mika ; Vivi, Rodrigo 
> 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/display: Reset message bus after 
> each read/write operation
> 
> Quoting Kahola, Mika (2023-10-06 03:49:15-03:00)
> >> -Original Message-
> >> From: Vivi, Rodrigo 
> >> Sent: Thursday, October 5, 2023 7:10 PM
> >> To: Sousa, Gustavo 
> >> Cc: Kahola, Mika ;
> >> intel-gfx@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Reset message bus
> >> after each read/write operation
> >>
> >> On Thu, Oct 05, 2023 at 12:40:35PM -0300, Gustavo Sousa wrote:
> >> > Quoting Rodrigo Vivi (2023-10-05 12:13:34-03:00)
> >> > >On Thu, Oct 05, 2023 at 03:05:31AM -0400, Kahola, Mika wrote:
> >> > >> > -Original Message-
> >> > >> > From: Vivi, Rodrigo 
> >> > >> > Sent: Wednesday, October 4, 2023 3:56 PM
> >> > >> > To: Kahola, Mika 
> >> > >> > Cc: intel-gfx@lists.freedesktop.org
> >> > >> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Reset
> >> > >> > message bus after each read/write operation
> >> > >> >
> >> > >> > On Wed, Oct 04, 2023 at 01:25:04PM +0300, Mika Kahola wrote:
> >> > >> > > Every know and then we receive the following error when
> >> > >> > > running for example IGT test kms_flip.
> >> > >> > >
> >> > >> > > [drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
> >> > >> > > [drm] *ERROR* PHY G Write 0d81 failed after 3 retries.
> >> > >> > >
> >> > >> > > Since the error is sporadic in nature, the patch proposes to
> >> > >> > > reset the message bus after every successful or unsuccessful
> >> > >> > > read or write operation. However, testing revealed that this
> >> > >> > > alone is not sufficient method an additiona delay is also
> >> > >> > > introduces anything from 200us to 300us. This delay is
> >> > >> > > experimental value and has no specification to back it up.
> >> > >> >
> >> > >> > have you tried the delays without the bus_reset?
> >> > >> Yes, we have bumped up the delay, first from 0x100 to 0x200 and
> >> > >> then as per BSpec change 0xa000 and I have tried 0xf000.
> >> > >> Increasing the timeout reduces the frequency of this error but 
> >> > >> doesn't solve this issue.
> >> > >
> >> > >what is exactly this BSPec's 0xa000? where can I see it? So maybe
> >> > >you can update the message above removing the 'no specification to back 
> >> > >it up'.
> >> >
> >> > (Resending this because I got a delivery failure notification)
> >> >
> >> > I think we are confusing "delay" with the "timeout parameter" of the 
> >> > msgbus.
> >> >
> >> > The PHY has a register to control the timeout parameter of msgbus
> >> > transactions (BSpec 65156). It's default value is 0x100. With
> >> > commit e028d7a4235d
> >> > ("drm/i915/cx0: Check and increase msgbus timeout threshold"), we
> >> > had integrated a workaround that bumped the timeout value to 0x200
> >> > in case timeouts were observed. Later on, there was a BSpec update
> >> > with the formal timeout value to be programmed to 0xa000, which was
> >> > incorporated with commit e35628968032
> >> > ("drm/i915/cx0: Add step for programming msgbus timer").
> >> >
> >> > I *believe* what Rodrigo has asked was about the usleep_range()
> >> > calls added with this patch, if we tried to only keep the usleed_range() 
> >> > without the bus reset.
> >>
> >> yes, that was my original question.
> >
> >I have no good explanation why usleep_range() is needed. Without it,
> >the kms_flip test eventually throws these read/write failures. As these
> >are a bit sporadic in nature, it takes some time to catch these errors.
> 
> I think the question is whether the bus reset is really necessary. Maybe only 
> the usleep_range() hack would be "enough" to
> mitigate the issue?

I have been scratching my head with this. I tested without reset and left only 
the delay i.e. usleep_range() in place but still I had these read/write 
failures. The same thing vice versa. It's like we would need both of them. I 
would like to understand why or is there something else that we are missing 
from our sequence?


> 
> --
> Gustavo Sousa
> 
> >
> >The patch is a hack and my idea was to set message bus at reset state after 
> >each read/write operation.
> >Unfortunately, this alone is not enough to pass kms_flip without these dmesg 
> >errors on read/write.
> >However, the kms_flip test itself, which triggers these, passes without 
> >issues.
> >
> >And I missed to mention that these errors show up (at least more
> >frequently) when 2x 4k monitors are connected. These may not be visible
> >with only one monitor connected. For such a system, I haven't been testing 
> >that much.
> >
> >-Mika-
> >
> >>
> >> >
> >> > --
> >> > Gustavo Sousa
> >> >
> >> > >
> >> > >Oh, and my english is bad, but it looks to me that 'empirical'
> >> > >might sound better than 'experimental' for this case, since you
> >> > >really did a lot of 

Re: [Intel-gfx] [PATCH] drm/i915/lnl: Remove watchdog timers for PSR

[Ville Syrjälä]

On Fri, Oct 06, 2023 at 02:42:10PM +0300, Mika Kahola wrote:
> Currently we are not using watchdog timers for PSR/PSR2.
> The patch disables these timers so they are not in use.

I can't figure out what you're saying here. What bspec seems to be
saying is that the max_sleep thing got nuked from the hw so we no
longer need to mask it.

> 
> BSpec: 69895
> 
> Signed-off-by: Mika Kahola 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 24 +---
>  1 file changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 850b11f20285..13b58dceb2bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -672,11 +672,15 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>   enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
>   u32 max_sleep_time = 0x1f;
> - u32 val = EDP_PSR_ENABLE;
> + u32 val = 0;
>  
> - val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
>  
> - val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
> + if (DISPLAY_VER(dev_priv) < 20) {
> + val =  EDP_PSR_ENABLE;

That would mean you never enable PSR1 on lnl+

> + val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
> + }
> +
> + val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
>   if (IS_HASWELL(dev_priv))
>   val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>  
> @@ -1398,10 +1402,16 @@ static void intel_psr_enable_source(struct intel_dp 
> *intel_dp,
>* runtime_pm besides preventing  other hw tracking issues now we
>* can rely on frontbuffer tracking.
>*/
> - mask = EDP_PSR_DEBUG_MASK_MEMUP |
> -EDP_PSR_DEBUG_MASK_HPD |
> -EDP_PSR_DEBUG_MASK_LPSP |
> -EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> + if (DISPLAY_VER(dev_priv) >= 20)
> + mask = EDP_PSR_DEBUG_MASK_MEMUP |
> +EDP_PSR_DEBUG_MASK_HPD |
> +EDP_PSR_DEBUG_MASK_LPSP;
> + else
> + mask = EDP_PSR_DEBUG_MASK_MEMUP |
> +EDP_PSR_DEBUG_MASK_HPD |
> +EDP_PSR_DEBUG_MASK_LPSP |
> +EDP_PSR_DEBUG_MASK_MAX_SLEEP;

The hpd mask bit also seems gone now, though there is no explanation
why it disappeared.

> +
>  
>   /*
>* No separate pipe reg write mask on hsw/bdw, so have to unmask all
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH] drm/i915/lnl: Remove watchdog timers for PSR

[Hogander, Jouni]

On Fri, 2023-10-06 at 14:42 +0300, Mika Kahola wrote:
> Currently we are not using watchdog timers for PSR/PSR2.
> The patch disables these timers so they are not in use.
> 
> BSpec: 69895
> 
> Signed-off-by: Mika Kahola 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 24 +-
> --
>  1 file changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 850b11f20285..13b58dceb2bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -672,11 +672,15 @@ static void hsw_activate_psr1(struct intel_dp
> *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> u32 max_sleep_time = 0x1f;
> -   u32 val = EDP_PSR_ENABLE;
> +   u32 val = 0;

This is not related to the commit message. I.e. PSR1 is left disabled
completely for DISPLAY_VER >= 20.
>  
> -   val |=
> EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
>  
> -   val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
> +   if (DISPLAY_VER(dev_priv) < 20) {
> +   val =  EDP_PSR_ENABLE;
> +   val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
> +   }
> +
> +   val |=
> EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> if (IS_HASWELL(dev_priv))
> val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>  
> @@ -1398,10 +1402,16 @@ static void intel_psr_enable_source(struct
> intel_dp *intel_dp,
>  * runtime_pm besides preventing  other hw tracking issues
> now we
>  * can rely on frontbuffer tracking.
>  */
> -   mask = EDP_PSR_DEBUG_MASK_MEMUP |
> -  EDP_PSR_DEBUG_MASK_HPD |
> -  EDP_PSR_DEBUG_MASK_LPSP |
> -  EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> +   if (DISPLAY_VER(dev_priv) >= 20)
> +   mask = EDP_PSR_DEBUG_MASK_MEMUP |
> +  EDP_PSR_DEBUG_MASK_HPD |
> +  EDP_PSR_DEBUG_MASK_LPSP;
> +   else
> +   mask = EDP_PSR_DEBUG_MASK_MEMUP |
> +  EDP_PSR_DEBUG_MASK_HPD |
> +  EDP_PSR_DEBUG_MASK_LPSP |
> +  EDP_PSR_DEBUG_MASK_MAX_SLEEP;

I would choose this:

   mask = EDP_PSR_DEBUG_MASK_MEMUP |
  EDP_PSR_DEBUG_MASK_HPD |
  EDP_PSR_DEBUG_MASK_LPSP;

   if (DISPLAY_VER(dev_priv) < 20)
   mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;

BR,

Jouni Högander

> +
>  
> /*
>  * No separate pipe reg write mask on hsw/bdw, so have to
> unmask all

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Remove incomplete PVC plumbing

[Andi Shyti]

Hi Tvrtko,

On Fri, Oct 06, 2023 at 09:31:02AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> PVC support will not be coming to i915 so get rid of its partial
> enablement and reduce the driver maintenance burden.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Andi Shyti  

Andi

Re: [Intel-gfx] [PATCH v7 2/5] drm/i915: Define and use GuC and CTB TLB invalidation routines

[Andi Shyti]

Hi,

> > +   /* Preallocate a shared id for use under memory pressure. */
> > +   err = xa_alloc_cyclic_irq(>tlb_lookup, >serial_slot, wait,
> > + xa_limit_32b, >next_seqno, GFP_KERNEL);
> > +   if (err == -ENOMEM) {
> > +   kfree(wait);
> > +   return err;
> > +   }
> What about any other error? Even if xa_alloc... is currently defined as not
> returning anything other than zero or ENOMEM, it is bad practice to assume
> that it can never produce any other error.

it can return -EBUSY when we run out of free spots. In such case
we neeed to wait a bit the queue to clear up.

Andi

Re: [Intel-gfx] [PATCH] drm/i915/display: Reset message bus after each read/write operation

[Gustavo Sousa]

Quoting Kahola, Mika (2023-10-06 03:49:15-03:00)
>> -Original Message-
>> From: Vivi, Rodrigo 
>> Sent: Thursday, October 5, 2023 7:10 PM
>> To: Sousa, Gustavo 
>> Cc: Kahola, Mika ; intel-gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Reset message bus after 
>> each read/write operation
>> 
>> On Thu, Oct 05, 2023 at 12:40:35PM -0300, Gustavo Sousa wrote:
>> > Quoting Rodrigo Vivi (2023-10-05 12:13:34-03:00)
>> > >On Thu, Oct 05, 2023 at 03:05:31AM -0400, Kahola, Mika wrote:
>> > >> > -Original Message-
>> > >> > From: Vivi, Rodrigo 
>> > >> > Sent: Wednesday, October 4, 2023 3:56 PM
>> > >> > To: Kahola, Mika 
>> > >> > Cc: intel-gfx@lists.freedesktop.org
>> > >> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Reset message
>> > >> > bus after each read/write operation
>> > >> >
>> > >> > On Wed, Oct 04, 2023 at 01:25:04PM +0300, Mika Kahola wrote:
>> > >> > > Every know and then we receive the following error when running
>> > >> > > for example IGT test kms_flip.
>> > >> > >
>> > >> > > [drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
>> > >> > > [drm] *ERROR* PHY G Write 0d81 failed after 3 retries.
>> > >> > >
>> > >> > > Since the error is sporadic in nature, the patch proposes to
>> > >> > > reset the message bus after every successful or unsuccessful
>> > >> > > read or write operation. However, testing revealed that this
>> > >> > > alone is not sufficient method an additiona delay is also
>> > >> > > introduces anything from 200us to 300us. This delay is
>> > >> > > experimental value and has no specification to back it up.
>> > >> >
>> > >> > have you tried the delays without the bus_reset?
>> > >> Yes, we have bumped up the delay, first from 0x100 to 0x200 and
>> > >> then as per BSpec change 0xa000 and I have tried 0xf000. Increasing
>> > >> the timeout reduces the frequency of this error but doesn't solve this 
>> > >> issue.
>> > >
>> > >what is exactly this BSPec's 0xa000? where can I see it? So maybe you
>> > >can update the message above removing the 'no specification to back it 
>> > >up'.
>> >
>> > (Resending this because I got a delivery failure notification)
>> >
>> > I think we are confusing "delay" with the "timeout parameter" of the 
>> > msgbus.
>> >
>> > The PHY has a register to control the timeout parameter of msgbus
>> > transactions (BSpec 65156). It's default value is 0x100. With commit
>> > e028d7a4235d
>> > ("drm/i915/cx0: Check and increase msgbus timeout threshold"), we had
>> > integrated a workaround that bumped the timeout value to 0x200 in case
>> > timeouts were observed. Later on, there was a BSpec update with the
>> > formal timeout value to be programmed to 0xa000, which was
>> > incorporated with commit e35628968032
>> > ("drm/i915/cx0: Add step for programming msgbus timer").
>> >
>> > I *believe* what Rodrigo has asked was about the usleep_range() calls
>> > added with this patch, if we tried to only keep the usleed_range() without 
>> > the bus reset.
>> 
>> yes, that was my original question.
>
>I have no good explanation why usleep_range() is needed. Without it, the 
>kms_flip test eventually
>throws these read/write failures. As these are a bit sporadic in nature, it 
>takes some time to catch
>these errors.

I think the question is whether the bus reset is really necessary. Maybe only
the usleep_range() hack would be "enough" to mitigate the issue?

--
Gustavo Sousa

>
>The patch is a hack and my idea was to set message bus at reset state after 
>each read/write operation.
>Unfortunately, this alone is not enough to pass kms_flip without these dmesg 
>errors on read/write.
>However, the kms_flip test itself, which triggers these, passes without issues.
>  
>And I missed to mention that these errors show up (at least more frequently) 
>when 2x 4k monitors are
>connected. These may not be visible with only one monitor connected. For such 
>a system, I haven't
>been testing that much.
>
>-Mika-
>
>> 
>> >
>> > --
>> > Gustavo Sousa
>> >
>> > >
>> > >Oh, and my english is bad, but it looks to me that 'empirical' might
>> > >sound better than 'experimental' for this case, since you really did
>> > >a lot of experiments before coming to this final conclusion.
>> > >
>> > >>
>> > >> > have you talked to hw architects about this?
>> > >> Yes, HW guys requested traces which I provided but based on these
>> > >> the sequence we use in i915 is correct.
>> > >>
>> > >> >
>> > >> > I wonder if we should add the delay inside the bus_reset itself?
>> > >> > although the bit 15 clear check should be enough by itself and it
>> > >> > doesn't look like it is a hw/fw reset involved to justify the extra 
>> > >> > delay.
>> > >> That should be enough. To me, it looks like when reading/writing to
>> > >> the bus maybe too fast, the hw cannot handle that and we need to reset 
>> > >> and let things settle down before trying again.
>> > >>
>> > >> >
>> > >> > well, at least some /* FIXME: */ or /* XXX: */ comments is

[Intel-gfx] [PATCH] drm/i915/lnl: Remove watchdog timers for PSR

[Mika Kahola]

Currently we are not using watchdog timers for PSR/PSR2.
The patch disables these timers so they are not in use.

BSpec: 69895

Signed-off-by: Mika Kahola 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 24 +---
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 850b11f20285..13b58dceb2bf 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -672,11 +672,15 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
u32 max_sleep_time = 0x1f;
-   u32 val = EDP_PSR_ENABLE;
+   u32 val = 0;
 
-   val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
 
-   val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
+   if (DISPLAY_VER(dev_priv) < 20) {
+   val =  EDP_PSR_ENABLE;
+   val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
+   }
+
+   val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
@@ -1398,10 +1402,16 @@ static void intel_psr_enable_source(struct intel_dp 
*intel_dp,
 * runtime_pm besides preventing  other hw tracking issues now we
 * can rely on frontbuffer tracking.
 */
-   mask = EDP_PSR_DEBUG_MASK_MEMUP |
-  EDP_PSR_DEBUG_MASK_HPD |
-  EDP_PSR_DEBUG_MASK_LPSP |
-  EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+   if (DISPLAY_VER(dev_priv) >= 20)
+   mask = EDP_PSR_DEBUG_MASK_MEMUP |
+  EDP_PSR_DEBUG_MASK_HPD |
+  EDP_PSR_DEBUG_MASK_LPSP;
+   else
+   mask = EDP_PSR_DEBUG_MASK_MEMUP |
+  EDP_PSR_DEBUG_MASK_HPD |
+  EDP_PSR_DEBUG_MASK_LPSP |
+  EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+
 
/*
 * No separate pipe reg write mask on hsw/bdw, so have to unmask all
-- 
2.34.1

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Remove early/pre-production Haswell code

[Tvrtko Ursulin]

On 06/10/2023 11:46, Ville Syrjälä wrote:

On Fri, Oct 06, 2023 at 09:31:01AM +0100, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

It is not our policy to keep pre-production hardware support for this long
so I guess this one was just forgotten.


This is about detecting pre-prod hw, not supporting it. I think keeping
the detection forever is a good idea since otherwise we may end up
mistakenly debugging pre-prod hw without even realizing it.


Hmm it was before my time, but surely HSW SDVs never left the company 
and you don't expect any internal systems to be using them after what 
10+ years?


Regards,

Tvrtko



Signed-off-by: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/i915_driver.c | 1 -
  drivers/gpu/drm/i915/i915_drv.h| 2 --
  2 files changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index ccbb2834cde0..78a42c8a8509 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -175,7 +175,6 @@ static void intel_detect_preproduction_hw(struct 
drm_i915_private *dev_priv)
  {
bool pre = false;
  
-	pre |= IS_HASWELL_EARLY_SDV(dev_priv);

pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb60fc9cf873..9d493ff1685a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -590,8 +590,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
  #define IS_RAPTORLAKE_U(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
-#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
-   (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
  #define IS_BROADWELL_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
  #define IS_BROADWELL_ULX(i915) \
--
2.39.2

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Create the guc_to_i915() wrapper (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Create the guc_to_i915() wrapper (rev2)
URL   : https://patchwork.freedesktop.org/series/124686/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13722 -> Patchwork_124686v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/index.html

Participating hosts (39 -> 40)
--

  Additional (2): fi-kbl-soraka bat-dg2-9 
  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_124686v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-hsw-4770:[PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-hsw-4770/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0@lmem0:
- bat-dg2-9:  NOTRUN -> [INCOMPLETE][3] ([i915#9275])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][6] ([i915#4083])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#6621])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_heartbeat:
- bat-jsl-3:  [PASS][10] -> [DMESG-FAIL][11] ([i915#5334])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-jsl-3/igt@i915_selftest@live@gt_heartbeat.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-jsl-3/igt@i915_selftest@live@gt_heartbeat.html
- fi-apl-guc: [PASS][12] -> [DMESG-FAIL][13] ([i915#5334])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][14] ([i915#1886])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@requests:
- bat-mtlp-8: [PASS][15] -> [ABORT][16] ([i915#9414])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-adls-5: [PASS][17] -> [FAIL][18] ([fdo#103375]) +3 other 
tests fail
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13722/bat-adls-5/igt@i915_susp...@basic-s3-without-i915.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-adls-5/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][19] ([i915#5190])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][20] ([i915#4215] / [i915#5190])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][21] ([i915#4212]) +6 other tests skip
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124686v2/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][22] 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Create the guc_to_i915() wrapper (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Create the guc_to_i915() wrapper (rev2)
URL   : https://patchwork.freedesktop.org/series/124686/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Remove early/pre-production Haswell code

[Ville Syrjälä]

On Fri, Oct 06, 2023 at 09:31:01AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> It is not our policy to keep pre-production hardware support for this long
> so I guess this one was just forgotten.

This is about detecting pre-prod hw, not supporting it. I think keeping
the detection forever is a good idea since otherwise we may end up
mistakenly debugging pre-prod hw without even realizing it.

> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_driver.c | 1 -
>  drivers/gpu/drm/i915/i915_drv.h| 2 --
>  2 files changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> b/drivers/gpu/drm/i915/i915_driver.c
> index ccbb2834cde0..78a42c8a8509 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -175,7 +175,6 @@ static void intel_detect_preproduction_hw(struct 
> drm_i915_private *dev_priv)
>  {
>   bool pre = false;
>  
> - pre |= IS_HASWELL_EARLY_SDV(dev_priv);
>   pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
>   pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
>   pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cb60fc9cf873..9d493ff1685a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -590,8 +590,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
>  #define IS_RAPTORLAKE_U(i915) \
>   IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> -#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
> - (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
>  #define IS_BROADWELL_ULT(i915) \
>   IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
>  #define IS_BROADWELL_ULX(i915) \
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel