[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/8] drm/i915/migrate: don't check the scratch page

[Patchwork]

== Series Details ==

Series: series starting with [1/8] drm/i915/migrate: don't check the scratch 
page
URL   : https://patchwork.freedesktop.org/series/97504/
State : failure

== Summary ==

Applying: drm/i915/migrate: don't check the scratch page
Applying: drm/i915/gtt: add xehpsdv_ppgtt_insert_entry
Applying: drm/i915/gtt: add gtt mappable plumbing
Applying: drm/i915/migrate: fix offset calculation
Applying: drm/i915/migrate: fix length calculation
Applying: drm/i915/selftests: handle object rounding
Applying: drm/i915/migrate: add acceleration support for DG2
error: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/gt/intel_migrate.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0007 drm/i915/migrate: add acceleration support for DG2
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

[Intel-gfx] [PULL] drm-intel-fixes

[Rodrigo Vivi]

Hi Dave and Daniel,

Here goes drm-intel-fixes-2021-12-02:

- Fixing a regression where the backlight brightness control stopped working.

- Fix the Intel HDR backlight support detection.

- Reverting a w/a to fix a gpu Hang in TGL. The w/a itself was also
for a hang, but in a much rarer scenario. The proper solution need
to be done with help from user space and it will be addressed later.

Thanks,
Rodrigo.

The following changes since commit d58071a8a76d779eedab38033ae4c821c30295a5:

  Linux 5.16-rc3 (2021-11-28 14:09:19 -0800)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2021-12-02

for you to fetch changes up to 72641d8d60401a5f1e1a0431ceaf928680d34418:

  Revert "drm/i915: Implement Wa_1508744258" (2021-12-02 09:56:34 -0500)


- Fixing a regression where the backlight brightness control stopped working.

- Fix the Intel HDR backlight support detection.

- Reverting a w/a to fix a gpu Hang in TGL. The w/a itself was also
for a hang, but in a much rarer scenario. The proper solution need
to be done with help from user space and it will be addressed later.


José Roberto de Souza (1):
  Revert "drm/i915: Implement Wa_1508744258"

Lyude Paul (2):
  drm/i915: Add support for panels with VESA backlights with PWM 
enable/disable
  drm/i915/dp: Perform 30ms delay after source OUI write

 drivers/gpu/drm/i915/display/intel_display_types.h |  3 ++
 drivers/gpu/drm/i915/display/intel_dp.c| 11 
 drivers/gpu/drm/i915/display/intel_dp.h|  2 ++
 .../gpu/drm/i915/display/intel_dp_aux_backlight.c  | 32 ++
 drivers/gpu/drm/i915/gt/intel_workarounds.c|  7 -
 5 files changed, 42 insertions(+), 13 deletions(-)

Re: [Intel-gfx] [PATCH] drm/i915/snps: use div32 version of MPLLB word clock for UHBR

[Ville Syrjälä]

On Thu, Dec 02, 2021 at 04:44:56PM +0200, Jani Nikula wrote:
> The mode set sequence for 128b/132b requires setting the div32 version
> of MPLLB clock.
> 
> Bspec: 53880, 54128

Weird place for that information when all the other bits are listed
in the clock programming section :/

> Signed-off-by: Jani Nikula 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 ++
>  drivers/gpu/drm/i915/i915_reg.h   | 1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c 
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index c2251218a39e..09f405e4d363 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -186,6 +186,7 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_100 = 
> {
>   REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>   REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
>   REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
>   REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
>   .mpllb_div2 =
>   REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
> @@ -369,6 +370,7 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 
> = {
>   REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>   REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
>   REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
>   REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
>   .mpllb_div2 =
>   REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3450818802c2..1fad1d593e13 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2265,6 +2265,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define   SNPS_PHY_MPLLB_DP2_MODEREG_BIT(9)
>  #define   SNPS_PHY_MPLLB_WORD_DIV2_ENREG_BIT(8)
>  #define   SNPS_PHY_MPLLB_TX_CLK_DIV  REG_GENMASK(7, 5)
> +#define   SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL  REG_BIT(0)
>  
>  #define SNPS_PHY_MPLLB_FRACN1(phy)   _MMIO_SNPS(phy, 0x168008)
>  #define   SNPS_PHY_MPLLB_FRACN_ENREG_BIT(31)
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH] drm/i915: replace X86_FEATURE_PAT with pat_enabled()

[Souza, Jose]

On Wed, 2021-12-01 at 16:30 -0800, Lucas De Marchi wrote:
> PAT can be disabled on boot with "nopat" in the command line. Replace
> one x86-ism with another, which is slightly more correct to prepare for
> supporting other architectures.

Reviewed-by: José Roberto de Souza 

> 
> Cc: Matt Roper 
> Signed-off-by: Lucas De Marchi 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_mman.c  | 8 
>  drivers/gpu/drm/i915/gem/i915_gem_pages.c | 3 +--
>  2 files changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index 65fc6ff5f59d..c0c509e5c0ae 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -72,7 +72,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
>   if (args->flags & ~(I915_MMAP_WC))
>   return -EINVAL;
>  
> - if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
> + if (args->flags & I915_MMAP_WC && !pat_enabled())
>   return -ENODEV;
>  
>   obj = i915_gem_object_lookup(file, args->handle);
> @@ -736,7 +736,7 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
>  
>   if (HAS_LMEM(to_i915(dev)))
>   mmap_type = I915_MMAP_TYPE_FIXED;
> - else if (boot_cpu_has(X86_FEATURE_PAT))
> + else if (pat_enabled())
>   mmap_type = I915_MMAP_TYPE_WC;
>   else if (!i915_ggtt_has_aperture(_i915(dev)->ggtt))
>   return -ENODEV;
> @@ -792,7 +792,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void 
> *data,
>   break;
>  
>   case I915_MMAP_OFFSET_WC:
> - if (!boot_cpu_has(X86_FEATURE_PAT))
> + if (!pat_enabled())
>   return -ENODEV;
>   type = I915_MMAP_TYPE_WC;
>   break;
> @@ -802,7 +802,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void 
> *data,
>   break;
>  
>   case I915_MMAP_OFFSET_UC:
> - if (!boot_cpu_has(X86_FEATURE_PAT))
> + if (!pat_enabled())
>   return -ENODEV;
>   type = I915_MMAP_TYPE_UC;
>   break;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> index 49c6e55c68ce..89b70f5cde7a 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> @@ -424,8 +424,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object 
> *obj,
>   goto err_unpin;
>   }
>  
> - if (GEM_WARN_ON(type == I915_MAP_WC &&
> - !static_cpu_has(X86_FEATURE_PAT)))
> + if (GEM_WARN_ON(type == I915_MAP_WC && !pat_enabled()))
>   ptr = ERR_PTR(-ENODEV);
>   else if (i915_gem_object_has_struct_page(obj))
>   ptr = i915_gem_object_map_page(obj, type);

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Re-use i915 macros for checking PTEs (rev11)

[Cheng, Michael]

Hey Lakshmi,

I believe the following errors are unrelated to my change, could you please 
help update the CI?

Thanks,

Michael Cheng

From: Patchwork 
Sent: 02 December 2021 12:28
To: Cheng, Michael 
Cc: intel-gfx@lists.freedesktop.org 
Subject: ✗ Fi.CI.BAT: failure for drm/i915: Re-use i915 macros for checking 
PTEs (rev11)

Patch Details
Series: drm/i915: Re-use i915 macros for checking PTEs (rev11)
URL:https://patchwork.freedesktop.org/series/97090/
State:  failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/index.html
CI Bug Log - changes from CI_DRM_10956 -> Patchwork_21734
Summary

FAILURE

Serious unknown changes coming with Patchwork_21734 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21734, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/index.html

Participating hosts (39 -> 33)

Missing (6): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-4 bat-jsl-2 bat-jsl-1

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_21734:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@gem_contexts:

 *   fi-skl-6600u: NOTRUN -> 
DMESG-FAIL

 *   fi-bsw-kefka: 
PASS
 -> 
DMESG-FAIL

 *   fi-glk-dsi: 
PASS
 -> 
DMESG-FAIL

 *   fi-skl-6700k2: 
PASS
 -> 
DMESG-FAIL

 *   fi-cfl-8700k: 
PASS
 -> 
DMESG-FAIL

 *   fi-bsw-n3050: 
PASS
 -> 
DMESG-FAIL

 *   fi-kbl-7567u: 
PASS
 -> 
DMESG-FAIL

 *   fi-cfl-guc: 
PASS
 -> 
DMESG-FAIL

 *   fi-bxt-dsi: 
PASS
 -> 
DMESG-FAIL

 *   fi-bdw-5557u: 
PASS
 -> 
DMESG-FAIL

 *   fi-kbl-7500u: 
PASS
 -> 
DMESG-FAIL

Known issues

Here are the changes found in Patchwork_21734 that come from known issues:

IGT changes
Issues hit

  *   igt@amdgpu/amd_cs_nop@sync-fork-gfx0:

 *   fi-skl-6600u: NOTRUN -> 
SKIP
 (fdo#109271) +18 similar 
issues
  *   igt@i915_selftest@live@execlists:

 *   fi-bsw-nick: 
PASS
 -> 
INCOMPLETE
 (i915#2940)
  *   igt@runner@aborted:

 *   fi-bsw-nick: NOTRUN -> 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm: get rid of DRM_DEBUG_* log calls in drm core, files drm_a*.c

[Patchwork]

== Series Details ==

Series: drm: get rid of DRM_DEBUG_* log calls in drm core, files drm_a*.c
URL   : https://patchwork.freedesktop.org/series/97498/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10956_full -> Patchwork_21730_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_21730_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21730_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21730_full:

### IGT changes ###

 Warnings 

  * igt@kms_psr2_su@page_flip-p010:
- shard-iclb: [SKIP][1] ([i915#658]) -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-iclb6/igt@kms_psr2_su@page_flip-p010.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html

  
Known issues


  Here are the changes found in Patchwork_21730_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@display-4x:
- shard-apl:  NOTRUN -> [SKIP][3] ([fdo#109271]) +51 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-apl6/igt@feature_discov...@display-4x.html

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
- shard-skl:  NOTRUN -> [SKIP][4] ([fdo#109271]) +159 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-skl6/igt@gem_ctx_persistence@legacy-engines-h...@blt.html

  * igt@gem_ctx_persistence@legacy-engines-persistence:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-persistence.html

  * igt@gem_ctx_sseu@invalid-sseu:
- shard-tglb: NOTRUN -> [SKIP][6] ([i915#280])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-tglb8/igt@gem_ctx_s...@invalid-sseu.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#3063] / [i915#3648])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-tglb3/igt@gem_...@unwedge-stress.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-tglb1/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-glk:  NOTRUN -> [SKIP][9] ([fdo#109271]) +35 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-glk8/igt@gem_exec_balan...@parallel-out-fence.html
- shard-iclb: NOTRUN -> [SKIP][10] ([i915#4525])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-iclb5/igt@gem_exec_balan...@parallel-out-fence.html
- shard-tglb: NOTRUN -> [SKIP][11] ([i915#4525])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-tglb8/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][12] -> [INCOMPLETE][13] ([i915#4547])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-skl10/igt@gem_exec_capture@p...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-skl6/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
- shard-glk:  [PASS][16] -> [FAIL][17] ([i915#2842])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-glk2/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: NOTRUN -> [FAIL][18] ([i915#2842])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-tglb8/igt@gem_exec_fair@basic-none-...@rcs0.html
- shard-iclb: NOTRUN -> [FAIL][19] ([i915#2842])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-iclb5/igt@gem_exec_fair@basic-none-...@rcs0.html
- shard-glk:  NOTRUN -> [FAIL][20] ([i915#2842])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/shard-glk8/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-apl:  

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Re-use i915 macros for checking PTEs (rev11)

[Patchwork]

== Series Details ==

Series: drm/i915: Re-use i915 macros for checking PTEs (rev11)
URL   : https://patchwork.freedesktop.org/series/97090/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
13238fd0ba2e drm/i915: Re-use i915 macros for checking PTEs
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#6: 
Certain gen8 ppgtt/gtt functions are using _PAGE_RW and _PAGE_PRESENT to check

total: 0 errors, 1 warnings, 0 checks, 72 lines checked

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Re-use i915 macros for checking PTEs (rev11)

[Patchwork]

== Series Details ==

Series: drm/i915: Re-use i915 macros for checking PTEs (rev11)
URL   : https://patchwork.freedesktop.org/series/97090/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10956 -> Patchwork_21734


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21734 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21734, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/index.html

Participating hosts (39 -> 33)
--

  Missing(6): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-4 bat-jsl-2 
bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_21734:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gem_contexts:
- fi-skl-6600u:   NOTRUN -> [DMESG-FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-kefka:   [PASS][2] -> [DMESG-FAIL][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
- fi-glk-dsi: [PASS][4] -> [DMESG-FAIL][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-skl-6700k2:  [PASS][6] -> [DMESG-FAIL][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-8700k:   [PASS][8] -> [DMESG-FAIL][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-n3050:   [PASS][10] -> [DMESG-FAIL][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-7567u:   [PASS][12] -> [DMESG-FAIL][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-guc: [PASS][14] -> [DMESG-FAIL][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-bxt-dsi: [PASS][16] -> [DMESG-FAIL][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-bdw-5557u:   [PASS][18] -> [DMESG-FAIL][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-7500u:   [PASS][20] -> [DMESG-FAIL][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html

  
Known issues


  Here are the changes found in Patchwork_21734 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u:   NOTRUN -> [SKIP][22] ([fdo#109271]) +18 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][23] -> [INCOMPLETE][24] ([i915#2940])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21734/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> 

Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/dg2: Add Wa_16011777198

[Clint Taylor]

Correct,

Reviewed-by: Clint Taylor 

-Clint



On 11/16/21 9:48 AM, Matt Roper wrote:

Coarse power gating for render should not be enabled on some DG2
steppings.

Bspec: 52698
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++
  1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 43093dd2d0c9..c3155ee58689 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -117,10 +117,17 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
GEN6_RC_CTL_RC6_ENABLE |
GEN6_RC_CTL_EI_MODE(1);
  
-	pg_enable =

-   GEN9_RENDER_PG_ENABLE |
-   GEN9_MEDIA_PG_ENABLE |
-   GEN11_MEDIA_SAMPLER_PG_ENABLE;
+   /* Wa_16011777198 - Render powergating must remain disabled */
+   if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
+   IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
+   pg_enable =
+   GEN9_MEDIA_PG_ENABLE |
+   GEN11_MEDIA_SAMPLER_PG_ENABLE;
+   else
+   pg_enable =
+   GEN9_RENDER_PG_ENABLE |
+   GEN9_MEDIA_PG_ENABLE |
+   GEN11_MEDIA_SAMPLER_PG_ENABLE;
  
  	if (GRAPHICS_VER(gt->i915) >= 12) {

for (i = 0; i < I915_MAX_VCS; i++)

Re: [Intel-gfx] [PATCH v3 2/5] drm/i915/dg2: Add Wa_14010547955

[Clint Taylor]

Looks correct.

Reviewed-by: Clint Taylor 

-Clint


On 11/16/21 9:48 AM, Matt Roper wrote:

This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the driver really needs
to do is program a chicken bit to reenable some internal behavior.

Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/display/intel_display.c | 4 
  drivers/gpu/drm/i915/i915_reg.h  | 5 +++--
  2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 0ceee8ac6671..1639bdbe2091 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -988,6 +988,10 @@ static void icl_set_pipe_chicken(const struct 
intel_crtc_state *crtc_state)
else if (DISPLAY_VER(dev_priv) >= 13)
tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
  
+	/* Wa_14010547955:dg2 */

+   if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
+   tmp |= DG2_RENDER_CCSTAG_4_3_EN;
+
intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
  }
  
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h

index f15ffc53e858..c187ec122fdb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8568,8 +8568,9 @@ enum {
   _PIPEB_CHICKEN)
  #define   UNDERRUN_RECOVERY_DISABLE_ADLP  REG_BIT(30)
  #define   UNDERRUN_RECOVERY_ENABLE_DG2REG_BIT(30)
-#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
-#define   PER_PIXEL_ALPHA_BYPASS_EN(1 << 7)
+#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
+#define   DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
+#define   PER_PIXEL_ALPHA_BYPASS_ENREG_BIT(7)
  
  #define VFLSKPD_MMIO(0x62a8)

  #define   DIS_OVER_FETCH_CACHEREG_BIT(1)

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix possible null ptr dereferences

[Patchwork]

== Series Details ==

Series: drm/i915: Fix possible null ptr dereferences
URL   : https://patchwork.freedesktop.org/series/97496/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10955_full -> Patchwork_21729_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21729_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21729_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21729_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_userptr_blits@huge-split:
- shard-snb:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/shard-snb7/igt@gem_userptr_bl...@huge-split.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-snb4/igt@gem_userptr_bl...@huge-split.html

  
Known issues


  Here are the changes found in Patchwork_21729_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl:  [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +2 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/shard-kbl7/igt@gem_ctx_isolation@preservation...@bcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-kbl7/igt@gem_ctx_isolation@preservation...@bcs0.html

  * igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#3063])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/shard-tglb1/igt@gem_...@in-flight-contexts-immediate.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-tglb3/igt@gem_...@in-flight-contexts-immediate.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][7] -> [TIMEOUT][8] ([i915#2481] / [i915#3070])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/shard-iclb8/igt@gem_...@unwedge-stress.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-iclb6/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][9] -> [INCOMPLETE][10] ([i915#4547])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/shard-skl4/igt@gem_exec_capture@p...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-skl4/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#2846])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/shard-glk3/igt@gem_exec_f...@basic-deadline.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-glk5/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-glk:  [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar 
issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-glk1/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl:  [PASS][15] -> [SKIP][16] ([fdo#109271])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs1.html
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2842])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/shard-tglb2/igt@gem_exec_fair@basic-p...@vcs1.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-tglb8/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_params@secure-non-master:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#112283])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-tglb5/igt@gem_exec_par...@secure-non-master.html

  * igt@gem_huc_copy@huc-copy:
- shard-glk:  NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#2190])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/shard-glk9/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-multi:
- shard-skl:  NOTRUN -> [SKIP][23] 

Re: [Intel-gfx] [PATCH v3 4/5] drm/i915/dg2: Add Wa_16013000631

[Clint Taylor]

Reviewed-by: Clint Taylor 

-Clint


On 11/16/21 9:48 AM, Matt Roper wrote:

From: Ramalingam C 

Invalidate IC cache through pipe control command as part of the ctx
restore flow through indirect ctx pointer.

v2:
  - Move pipe control from xcs indirect context to the rcs indirect
context.  We'll eventually need this on the CCS engines too, but
support for those hasn't landed yet.

Cc: Chris Wilson 
Signed-off-by: Ramalingam C 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 56156cf18c41..b3489599e4de 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1167,6 +1167,11 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context 
*ce, u32 *cs)
cs = gen12_emit_cmd_buf_wa(ce, cs);
cs = gen12_emit_restore_scratch(ce, cs);
  
+	/* Wa_16013000631:dg2 */

+   if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) ||
+   IS_DG2_G11(ce->engine->i915))
+   cs = gen8_emit_pipe_control(cs, 
PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0);
+
return cs;
  }
  

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix possible null ptr dereferences

[Patchwork]

== Series Details ==

Series: drm/i915: Fix possible null ptr dereferences
URL   : https://patchwork.freedesktop.org/series/97496/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10955 -> Patchwork_21729


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/index.html

Participating hosts (40 -> 33)
--

  Additional (1): fi-kbl-soraka 
  Missing(8): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 
fi-pnv-d510 bat-jsl-2 bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_21729:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gem:
- {fi-jsl-1}: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/fi-jsl-1/igt@i915_selftest@l...@gem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-jsl-1/igt@i915_selftest@l...@gem.html

  
Known issues


  Here are the changes found in Patchwork_21729 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850:   NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-blb-e6850/igt@amdgpu/amd_ba...@cs-multi-fence.html

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u:   NOTRUN -> [SKIP][5] ([fdo#109271]) +18 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271]) +8 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4:  [PASS][7] -> [FAIL][8] ([i915#1888])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   [PASS][11] -> [INCOMPLETE][12] ([i915#2940])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][13] ([i915#1886] / [i915#2291])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[PASS][14] -> [DMESG-FAIL][15] ([i915#2927] / 
[i915#3428])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [PASS][17] -> [DMESG-WARN][18] ([i915#4269])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10955/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#533])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21729/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][20] 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Re-use i915 macros for checking PTEs (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915: Re-use i915 macros for checking PTEs (rev10)
URL   : https://patchwork.freedesktop.org/series/97090/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10956 -> Patchwork_21732


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21732 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21732, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/index.html

Participating hosts (39 -> 32)
--

  Missing(7): bat-dg1-6 bat-dg1-5 fi-icl-u2 fi-bsw-cyan bat-adlp-4 
bat-jsl-2 bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_21732:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gem_contexts:
- fi-bsw-kefka:   [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
- fi-glk-dsi: [PASS][3] -> [DMESG-FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-skl-6700k2:  [PASS][5] -> [DMESG-FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-8700k:   [PASS][7] -> [DMESG-FAIL][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-n3050:   [PASS][9] -> [DMESG-FAIL][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-7567u:   [PASS][11] -> [DMESG-FAIL][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-guc: [PASS][13] -> [DMESG-FAIL][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-bxt-dsi: [PASS][15] -> [DMESG-FAIL][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-7500u:   [PASS][17] -> [DMESG-FAIL][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html

  
Known issues


  Here are the changes found in Patchwork_21732 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [PASS][19] -> [FAIL][20] ([i915#4547])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][21] -> [DMESG-FAIL][22] ([i915#4528])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@runner@aborted:
- fi-bdw-5557u:   NOTRUN -> [FAIL][23] ([i915#2426] / [i915#4312])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-bdw-5557u/igt@run...@aborted.html
- fi-blb-e6850:   NOTRUN -> [FAIL][24] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21732/fi-blb-e6850/igt@run...@aborted.html

  
 Possible fixes 

  * 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: get rid of DRM_DEBUG_* log calls in drm core, files drm_a*.c

[Patchwork]

== Series Details ==

Series: drm: get rid of DRM_DEBUG_* log calls in drm core, files drm_a*.c
URL   : https://patchwork.freedesktop.org/series/97498/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10956 -> Patchwork_21730


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/index.html

Participating hosts (39 -> 35)
--

  Additional (2): fi-kbl-soraka fi-pnv-d510 
  Missing(6): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-4 bat-jsl-2 
bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_21730 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u:   [PASS][7] -> [DMESG-WARN][8] ([i915#295]) +12 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][10] ([fdo#109271]) +57 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-pnv-d510/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-bwr-2160:[FAIL][11] ([i915#3194]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html

  * igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [INCOMPLETE][13] ([i915#4432]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html

  
 Warnings 

  * igt@kms_psr@primary_page_flip:
- fi-skl-6600u:   [FAIL][15] ([i915#4547]) -> [INCOMPLETE][16] 
([i915#198])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21730/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Re-use i915 macros for checking PTEs (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915: Re-use i915 macros for checking PTEs (rev10)
URL   : https://patchwork.freedesktop.org/series/97090/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
ccb569c471b6 drm/i915: Re-use i915 macros for checking PTEs
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#6: 
Certain gen8 ppgtt/gtt functions are using _PAGE_RW and _PAGE_PRESENT to check

total: 0 errors, 1 warnings, 0 checks, 72 lines checked

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Reject 5k on HDR planes for planar fb formats (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev9)
URL   : https://patchwork.freedesktop.org/series/97053/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10954_full -> Patchwork_21728_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21728_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21728_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21728_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gtt:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-iclb5/igt@i915_selftest@l...@gtt.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/shard-iclb7/igt@i915_selftest@l...@gtt.html

  
 Warnings 

  * igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [SKIP][3] ([i915#658]) -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-iclb1/igt@kms_psr2_su@page_flip-nv12.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html

  
Known issues


  Here are the changes found in Patchwork_21728_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][5], [PASS][6], [PASS][7], [PASS][8], 
[PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], 
[PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], 
[PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], 
[PASS][27], [PASS][28], [PASS][29]) -> ([PASS][30], [PASS][31], [PASS][32], 
[PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], 
[PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], 
[PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], 
[PASS][51], [PASS][52], [PASS][53], [FAIL][54]) ([i915#4386])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl1/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl1/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl2/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl2/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl3/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl3/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl3/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl3/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl4/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl4/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl4/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl6/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl7/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl7/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl7/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl7/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl8/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl8/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/shard-apl8/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/shard-apl1/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/shard-apl8/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/shard-apl8/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/shard-apl8/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/shard-apl8/boot.html
   [35]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/snps: use div32 version of MPLLB word clock for UHBR

[Patchwork]

== Series Details ==

Series: drm/i915/snps: use div32 version of MPLLB word clock for UHBR
URL   : https://patchwork.freedesktop.org/series/97499/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/snps: use div32 version of MPLLB word clock for UHBR

[Patchwork]

== Series Details ==

Series: drm/i915/snps: use div32 version of MPLLB word clock for UHBR
URL   : https://patchwork.freedesktop.org/series/97499/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10956 -> Patchwork_21731


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/index.html

Participating hosts (39 -> 33)
--

  Missing(6): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-4 bat-jsl-2 
bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_21731 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [PASS][1] -> [FAIL][2] ([i915#4547])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-bwr-2160:[FAIL][3] ([i915#3194]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [DMESG-WARN][5] ([i915#4269]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547


Build changes
-

  * Linux: CI_DRM_10956 -> Patchwork_21731

  CI-20190529: 20190529
  CI_DRM_10956: 3e61582553e3b43064fa2069f20307a9df91a0d2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6299: 0933b7ccdb2bb054b6a8154171e35315d84299b7 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21731: 53eb587906eea66ebe9a356358415c148e77b63f @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

53eb587906ee drm/i915/snps: use div32 version of MPLLB word clock for UHBR

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/index.html

Re: [Intel-gfx] [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width

[Srinivas, Vidya]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Thursday, December 2, 2021 6:37 PM
> To: Srinivas, Vidya 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
> 
> On Thu, Dec 02, 2021 at 04:38:36PM +0530, Vidya Srinivas wrote:
> > PLANE_CUS_CTL has a restriction of 4096 width even though PLANE_SIZE
> > and scaler size registers supports max 5120.
> > Take care of this restriction in max_width.
> >
> > Without this patch, when 5k content is sent on HDR plane with NV12
> > content, FIFO underrun is seen and screen blanks out.
> >
> > v2: Addressed review comments from Ville. Added separate functions for
> > max_width - for HDR and SDR
> >
> > v3: Addressed review comments from Ville. Changed names of HDR and
> SDR
> > max_width functions to icl_hdr_plane_max_width and
> > icl_sdr_plane_max_width
> >
> > v4: Fixed paranthesis alignment. No code change
> >
> > Reviewed-by: Ville Syrjälä 
> > Signed-off-by: Vidya Srinivas 
> 
> Pushed to drm-intel-next. Thanks.

Hello Ville, thank you very much for all the help.

Regards
Vidya
> 
> > ---
> >  .../drm/i915/display/skl_universal_plane.c| 21 +++
> >  1 file changed, 17 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 28890876bdeb..e717eb58b105 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -420,9 +420,19 @@ static int icl_plane_min_width(const struct
> drm_framebuffer *fb,
> > }
> >  }
> >
> > -static int icl_plane_max_width(const struct drm_framebuffer *fb,
> > -  int color_plane,
> > -  unsigned int rotation)
> > +static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
> > +   int color_plane,
> > +   unsigned int rotation)
> > +{
> > +   if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> > +   return 4096;
> > +   else
> > +   return 5120;
> > +}
> > +
> > +static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
> > +   int color_plane,
> > +   unsigned int rotation)
> >  {
> > return 5120;
> >  }
> > @@ -2108,7 +2118,10 @@ skl_universal_plane_create(struct
> > drm_i915_private *dev_priv,
> >
> > if (DISPLAY_VER(dev_priv) >= 11) {
> > plane->min_width = icl_plane_min_width;
> > -   plane->max_width = icl_plane_max_width;
> > +   if (icl_is_hdr_plane(dev_priv, plane_id))
> > +   plane->max_width = icl_hdr_plane_max_width;
> > +   else
> > +   plane->max_width = icl_sdr_plane_max_width;
> > plane->max_height = icl_plane_max_height;
> > plane->min_cdclk = icl_plane_min_cdclk;
> > } else if (DISPLAY_VER(dev_priv) >= 10) {
> > --
> > 2.33.0
> 
> --
> Ville Syrjälä
> Intel

[Intel-gfx] [PATCH 2/8] drm/i915/gtt: add xehpsdv_ppgtt_insert_entry

[Matthew Auld]

If this is LMEM then we get a 32 entry PT, with each PTE pointing to
some 64K block of memory, otherwise it's just the usual 512 entry PT.
This very much assumes the caller knows what they are doing.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ramalingam C 
---
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 50 ++--
 1 file changed, 48 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index bd3ca0996a23..312b2267bf87 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -728,13 +728,56 @@ static void gen8_ppgtt_insert_entry(struct 
i915_address_space *vm,
gen8_pdp_for_page_index(vm, idx);
struct i915_page_directory *pd =
i915_pd_entry(pdp, gen8_pd_index(idx, 2));
+   struct i915_page_table *pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
gen8_pte_t *vaddr;
 
-   vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+   GEM_BUG_ON(pt->is_compact);
+
+   vaddr = px_vaddr(pt);
vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
clflush_cache_range([gen8_pd_index(idx, 0)], sizeof(*vaddr));
 }
 
+static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
+   dma_addr_t addr,
+   u64 offset,
+   enum i915_cache_level level,
+   u32 flags)
+{
+   u64 idx = offset >> GEN8_PTE_SHIFT;
+   struct i915_page_directory * const pdp =
+   gen8_pdp_for_page_index(vm, idx);
+   struct i915_page_directory *pd =
+   i915_pd_entry(pdp, gen8_pd_index(idx, 2));
+   struct i915_page_table *pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
+   gen8_pte_t *vaddr;
+
+   GEM_BUG_ON(!IS_ALIGNED(addr, SZ_64K));
+   GEM_BUG_ON(!IS_ALIGNED(offset, SZ_64K));
+
+   if (!pt->is_compact) {
+   vaddr = px_vaddr(pd);
+   vaddr[gen8_pd_index(idx, 1)] |= GEN12_PDE_64K;
+   pt->is_compact = true;
+   }
+
+   vaddr = px_vaddr(pt);
+   vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
+}
+
+static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
+  dma_addr_t addr,
+  u64 offset,
+  enum i915_cache_level level,
+  u32 flags)
+{
+   if (flags & PTE_LM)
+   return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
+  level, flags);
+
+   return gen8_ppgtt_insert_entry(vm, addr, offset, level, flags);
+}
+
 static int gen8_init_scratch(struct i915_address_space *vm)
 {
u32 pte_flags;
@@ -937,7 +980,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
 
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
-   ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
+   if (HAS_64K_PAGES(gt->i915))
+   ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
+   else
+   ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
ppgtt->vm.clear_range = gen8_ppgtt_clear;
ppgtt->vm.foreach = gen8_ppgtt_foreach;
-- 
2.31.1

[Intel-gfx] [PATCH 3/8] drm/i915/gtt: add gtt mappable plumbing

[Matthew Auld]

With object clearing/copying we need to be able to modify the PTEs on
the fly via some batch buffer, which means we need to be able to map the
paging structures(or at the very least the PT, but being able to also
map the PD might also be useful at some point) into the GTT. And since
the paging structures must reside in LMEM on discrete, we need to ensure
that these objects have correct physical alignment, as per any min page
restrictions, like on DG2. This is potentially costly, but this should
be limited to the special migrate_vm, which only needs to a few fixed
sized windows.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ramalingam C 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c |  4 ++--
 drivers/gpu/drm/i915/gem/selftests/huge_pages.c |  2 +-
 drivers/gpu/drm/i915/gt/gen6_ppgtt.c|  2 +-
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c|  3 ++-
 drivers/gpu/drm/i915/gt/gen8_ppgtt.h|  1 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c|  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gtt.c |  7 +++
 drivers/gpu/drm/i915/gt/intel_gtt.h |  9 +
 drivers/gpu/drm/i915/gt/intel_migrate.c |  4 +++-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c   | 17 -
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c|  2 +-
 drivers/gpu/drm/i915/gvt/scheduler.c|  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c   |  4 ++--
 14 files changed, 44 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ebd775cb1661..b394954726b0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1559,7 +1559,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
 
-   ppgtt = i915_ppgtt_create(>gt, 0);
+   ppgtt = i915_ppgtt_create(>gt, 0, 0);
if (IS_ERR(ppgtt)) {
drm_dbg(>drm, "PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
@@ -1742,7 +1742,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void 
*data,
if (args->flags)
return -EINVAL;
 
-   ppgtt = i915_ppgtt_create(>gt, 0);
+   ppgtt = i915_ppgtt_create(>gt, 0, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
 
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index bd8dc1a28022..c1b86c7a4754 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1764,7 +1764,7 @@ int i915_gem_huge_page_mock_selftests(void)
mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
mkwrite_device_info(dev_priv)->ppgtt_size = 48;
 
-   ppgtt = i915_ppgtt_create(_priv->gt, 0);
+   ppgtt = i915_ppgtt_create(_priv->gt, 0, 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_unlock;
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index c0d149f04949..778472e563aa 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -443,7 +443,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
 
mutex_init(>flush);
 
-   ppgtt_init(>base, gt, 0);
+   ppgtt_init(>base, gt, 0, 0);
ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
ppgtt->base.vm.top = 1;
 
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 312b2267bf87..dfca803b4ff1 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -912,6 +912,7 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
  *
  */
 struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+unsigned long vm_flags,
 unsigned long lmem_pt_obj_flags)
 {
struct i915_ppgtt *ppgtt;
@@ -921,7 +922,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
if (!ppgtt)
return ERR_PTR(-ENOMEM);
 
-   ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
+   ppgtt_init(ppgtt, gt, vm_flags, lmem_pt_obj_flags);
ppgtt->vm.top = i915_vm_is_4lvl(>vm) ? 3 : 2;
ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
 
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
index f541d19264b4..c0af12593576 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
@@ -13,6 +13,7 @@ struct intel_gt;
 enum i915_cache_level;
 
 struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+unsigned long vm_flags,

[Intel-gfx] [PATCH 5/8] drm/i915/migrate: fix length calculation

[Matthew Auld]

No need to insert PTEs for the PTE window itself, also foreach expects a
length not an end offset, which could be gigantic here with a second
engine.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ramalingam C 
---
 drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c 
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index cb0bb3b94644..2076e24e0489 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -136,7 +136,7 @@ static struct i915_address_space *migrate_vm(struct 
intel_gt *gt)
goto err_vm;
 
/* Now allow the GPU to rewrite the PTE via its own ppGTT */
-   vm->vm.foreach(>vm, base, base + sz, insert_pte, );
+   vm->vm.foreach(>vm, base, d.offset - base, insert_pte, );
}
 
return >vm;
-- 
2.31.1

[Intel-gfx] [PATCH 7/8] drm/i915/migrate: add acceleration support for DG2

[Matthew Auld]

This is all kinds of awkward since we now have to contend with using 64K
GTT pages when mapping anything in LMEM(including the page-tables
themselves).

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ramalingam C 
---
 drivers/gpu/drm/i915/gt/intel_migrate.c | 186 +++-
 1 file changed, 147 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c 
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 2076e24e0489..a804c57b61df 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -33,6 +33,38 @@ static bool engine_supports_migration(struct intel_engine_cs 
*engine)
return true;
 }
 
+static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
+   struct i915_page_table *pt,
+   void *data)
+{
+   struct insert_pte_data *d = data;
+
+   /*
+* Insert a dummy PTE into every PT that will map to LMEM to ensure
+* we have a correctly setup PDE structure for later use.
+*/
+   vm->insert_page(vm, 0, d->offset, I915_CACHE_NONE, PTE_LM);
+   GEM_BUG_ON(!pt->is_compact);
+   d->offset += SZ_2M;
+}
+
+static void xehpsdv_insert_pte(struct i915_address_space *vm,
+  struct i915_page_table *pt,
+  void *data)
+{
+   struct insert_pte_data *d = data;
+
+   /*
+* We are playing tricks here, since the actual pt, from the hw
+* pov, is only 256bytes with 32 entries, or 4096bytes with 512
+* entries, but we are still guaranteed that the physical
+* alignment is 64K underneath for the pt, and we are careful
+* not to access the space in the void.
+*/
+   vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE, PTE_LM);
+   d->offset += SZ_64K;
+}
+
 static void insert_pte(struct i915_address_space *vm,
   struct i915_page_table *pt,
   void *data)
@@ -75,7 +107,12 @@ static struct i915_address_space *migrate_vm(struct 
intel_gt *gt)
 * i.e. within the same non-preemptible window so that we do not switch
 * to another migration context that overwrites the PTE.
 *
-* TODO: Add support for huge LMEM PTEs
+* On platforms with HAS_64K_PAGES support we have three windows, and
+* dedicate two windows just for mapping lmem pages(smem <-> smem is not
+* a thing), since we are forced to use 64K GTT pages underneath which
+* requires also modifying the PDE. An alternative might be to instead
+* map the PD into the GTT, and then on the fly toggle the 4K/64K mode
+* in the PDE from the same batch that also modifies the PTEs.
 */
 
vm = i915_ppgtt_create(gt,
@@ -108,14 +145,20 @@ static struct i915_address_space *migrate_vm(struct 
intel_gt *gt)
 * We copy in 8MiB chunks. Each PDE covers 2MiB, so we need
 * 4x2 page directories for source/destination.
 */
-   sz = 2 * CHUNK_SZ;
+   if (HAS_64K_PAGES(gt->i915))
+   sz = 3 * CHUNK_SZ;
+   else
+   sz = 2 * CHUNK_SZ;
d.offset = base + sz;
 
/*
 * We need another page directory setup so that we can write
 * the 8x512 PTE in each chunk.
 */
-   sz += (sz >> 12) * sizeof(u64);
+   if (HAS_64K_PAGES(gt->i915))
+   sz += (sz / SZ_2M) * SZ_64K;
+   else
+   sz += (sz >> 12) * sizeof(u64);
 
err = i915_vm_alloc_pt_stash(>vm, , sz);
if (err)
@@ -136,7 +179,18 @@ static struct i915_address_space *migrate_vm(struct 
intel_gt *gt)
goto err_vm;
 
/* Now allow the GPU to rewrite the PTE via its own ppGTT */
-   vm->vm.foreach(>vm, base, d.offset - base, insert_pte, );
+   if (HAS_64K_PAGES(gt->i915)) {
+   vm->vm.foreach(>vm, base, d.offset - base,
+  xehpsdv_insert_pte, );
+   d.offset = base + CHUNK_SZ;
+   vm->vm.foreach(>vm,
+  d.offset,
+  2 * CHUNK_SZ,
+  xehpsdv_toggle_pdes, );
+   } else {
+   vm->vm.foreach(>vm, base, d.offset - base,
+  insert_pte, );
+   }
}
 
return >vm;
@@ -274,19 +328,38 @@ static int emit_pte(struct i915_request *rq,
u64 offset,
int length)
 {
+   bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
const u64 encode = rq->context->vm->pte_encode(0, cache_level,
   

[Intel-gfx] [PATCH 8/8] drm/i915/migrate: turn on acceleration for DG2

[Matthew Auld]

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ramalingam C 
---
 drivers/gpu/drm/i915/gt/intel_migrate.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c 
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index a804c57b61df..0da27ec808dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -242,8 +242,6 @@ int intel_migrate_init(struct intel_migrate *m, struct 
intel_gt *gt)
 
memset(m, 0, sizeof(*m));
 
-   return 0;
-
ce = pinned_context(gt);
if (IS_ERR(ce))
return PTR_ERR(ce);
-- 
2.31.1

[Intel-gfx] [PATCH 4/8] drm/i915/migrate: fix offset calculation

[Matthew Auld]

Ensure we add the engine base only after we calculate the qword offset
into the PTE window.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ramalingam C 
---
 drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c 
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index d553b76b1168..cb0bb3b94644 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -284,10 +284,10 @@ static int emit_pte(struct i915_request *rq,
GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
 
/* Compute the page directory offset for the target address range */
-   offset += (u64)rq->engine->instance << 32;
offset >>= 12;
offset *= sizeof(u64);
offset += 2 * CHUNK_SZ;
+   offset += (u64)rq->engine->instance << 32;
 
cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
-- 
2.31.1

[Intel-gfx] [PATCH 6/8] drm/i915/selftests: handle object rounding

[Matthew Auld]

Ensure we account for any object rounding due to min_page_size
restrictions.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ramalingam C 
---
 drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c 
b/drivers/gpu/drm/i915/gt/selftest_migrate.c
index 12ef2837c89b..e21787301bbd 100644
--- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -49,6 +49,7 @@ static int copy(struct intel_migrate *migrate,
if (IS_ERR(src))
return 0;
 
+   sz = src->base.size;
dst = i915_gem_object_create_internal(i915, sz);
if (IS_ERR(dst))
goto err_free_src;
-- 
2.31.1

[Intel-gfx] [PATCH 1/8] drm/i915/migrate: don't check the scratch page

[Matthew Auld]

The scratch page might not be allocated in LMEM(like on DG2), so instead
of using that as the deciding factor for where the paging structures
live, let's just query the pt before mapping it.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ramalingam C 
---
 drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c 
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 765c6d48fe52..2d3188a398dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -13,7 +13,6 @@
 
 struct insert_pte_data {
u64 offset;
-   bool is_lmem;
 };
 
 #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
@@ -41,7 +40,7 @@ static void insert_pte(struct i915_address_space *vm,
struct insert_pte_data *d = data;
 
vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
-   d->is_lmem ? PTE_LM : 0);
+   i915_gem_object_is_lmem(pt->base) ? PTE_LM : 0);
d->offset += PAGE_SIZE;
 }
 
@@ -135,7 +134,6 @@ static struct i915_address_space *migrate_vm(struct 
intel_gt *gt)
goto err_vm;
 
/* Now allow the GPU to rewrite the PTE via its own ppGTT */
-   d.is_lmem = i915_gem_object_is_lmem(vm->vm.scratch[0]);
vm->vm.foreach(>vm, base, base + sz, insert_pte, );
}
 
-- 
2.31.1

Re: [Intel-gfx] [PATCH 4/4] drm/i915/guc: Don't go bang in GuC log if no GuC

[Lucas De Marchi]

On Thu, Dec 02, 2021 at 04:06:23PM -0800, john.c.harri...@intel.com wrote:

From: John Harrison 

If the GuC has failed to load for any reason and then the user pokes
the debugfs GuC log interface, a BUG and/or null pointer deref can
occur. Don't let that happen.

Signed-off-by: John Harrison 



Reviewed-by: Lucas De Marchi 

Lucas De Marchi


---
drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
index 46026c2c1722..8fd068049376 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
@@ -31,7 +31,7 @@ static int guc_log_level_get(void *data, u64 *val)
{
struct intel_guc_log *log = data;

-   if (!intel_guc_is_used(log_to_guc(log)))
+   if (!log->vma)
return -ENODEV;

*val = intel_guc_log_get_level(log);
@@ -43,7 +43,7 @@ static int guc_log_level_set(void *data, u64 val)
{
struct intel_guc_log *log = data;

-   if (!intel_guc_is_used(log_to_guc(log)))
+   if (!log->vma)
return -ENODEV;

return intel_guc_log_set_level(log, val);
--
2.25.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Re-use i915 macros for checking PTEs (rev12)

[Patchwork]

== Series Details ==

Series: drm/i915: Re-use i915 macros for checking PTEs (rev12)
URL   : https://patchwork.freedesktop.org/series/97090/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
11b7af9a808e drm/i915: Re-use i915 macros for checking PTEs
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#6: 
Certain gen8 ppgtt/gtt functions are using _PAGE_RW and _PAGE_PRESENT to check

total: 0 errors, 1 warnings, 0 checks, 72 lines checked

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/snps: use div32 version of MPLLB word clock for UHBR

[Patchwork]

== Series Details ==

Series: drm/i915/snps: use div32 version of MPLLB word clock for UHBR
URL   : https://patchwork.freedesktop.org/series/97499/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10956_full -> Patchwork_21731_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_21731_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21731_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21731_full:

### IGT changes ###

 Warnings 

  * igt@kms_psr2_su@page_flip-p010:
- shard-iclb: [SKIP][1] ([i915#658]) -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-iclb6/igt@kms_psr2_su@page_flip-p010.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html

  
Known issues


  Here are the changes found in Patchwork_21731_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[FAIL][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4392])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk1/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk2/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk2/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk2/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk3/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk3/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk4/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk4/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk5/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk8/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk8/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk8/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk9/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10956/shard-glk9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/shard-glk2/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/shard-glk9/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/shard-glk9/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/shard-glk8/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/shard-glk8/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/shard-glk8/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/shard-glk7/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/shard-glk7/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21731/shard-glk7/boot.html
   [37]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for Assorted fixes/tweaks to GuC support

[Patchwork]

== Series Details ==

Series: Assorted fixes/tweaks to GuC support
URL   : https://patchwork.freedesktop.org/series/97514/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10957 -> Patchwork_21735


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/index.html

Participating hosts (38 -> 32)
--

  Missing(6): bat-dg1-6 bat-dg1-5 fi-icl-u2 fi-bsw-cyan bat-jsl-2 bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_21735 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-skl-6700k2:  NOTRUN -> [SKIP][1] ([fdo#109271]) +23 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/fi-skl-6700k2/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-ivb-3770:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/fi-ivb-3770/igt@amdgpu/amd_cs_...@fork-compute0.html

  * igt@gem_exec_suspend@basic-s3:
- fi-bdw-5557u:   [PASS][3] -> [INCOMPLETE][4] ([i915#146])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][5] -> [DMESG-FAIL][6] ([i915#4528])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@runner@aborted:
- fi-blb-e6850:   NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/fi-blb-e6850/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}:   [DMESG-FAIL][8] ([i915#541]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
- fi-ivb-3770:[INCOMPLETE][10] ([i915#3303]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2:  [INCOMPLETE][12] ([i915#198]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Build changes
-

  * Linux: CI_DRM_10957 -> Patchwork_21735

  CI-20190529: 20190529
  CI_DRM_10957: 10716ba5171eb4158a11d1c4fa773254751023e9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6299: 0933b7ccdb2bb054b6a8154171e35315d84299b7 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21735: 687c22d86d1674969b6a2e6bfea05366d340d01d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

687c22d86d16 drm/i915/guc: Don't go bang in GuC log if no GuC
fa97e9d77b1b drm/i915/guc: Increase GuC log size for CONFIG_DEBUG_GEM
1b7f2b22f34a drm/i915/guc: Request RP0 before loading firmware
394709d4751f drm/i915/uc: Allow platforms to have GuC but not HuC

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/index.html

[Intel-gfx] ✗ Fi.CI.IGT: failure for Assorted fixes/tweaks to GuC support

[Patchwork]

== Series Details ==

Series: Assorted fixes/tweaks to GuC support
URL   : https://patchwork.freedesktop.org/series/97514/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10957_full -> Patchwork_21735_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21735_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21735_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_21735_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_eio@kms:
- shard-glk:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/shard-glk2/igt@gem_...@kms.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-glk9/igt@gem_...@kms.html

  * igt@i915_pm_rps@reset:
- shard-tglb: [PASS][3] -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/shard-tglb8/igt@i915_pm_...@reset.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-tglb2/igt@i915_pm_...@reset.html

  * igt@i915_pm_rps@waitboost:
- shard-tglb: NOTRUN -> [FAIL][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-tglb8/igt@i915_pm_...@waitboost.html

  * igt@kms_atomic_transition@modeset-transition@1x-outputs:
- shard-tglb: [PASS][6] -> [INCOMPLETE][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/shard-tglb3/igt@kms_atomic_transition@modeset-transit...@1x-outputs.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-tglb8/igt@kms_atomic_transition@modeset-transit...@1x-outputs.html

  
Known issues


  Here are the changes found in Patchwork_21735_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@unwedge-stress:
- shard-skl:  [PASS][8] -> [TIMEOUT][9] ([i915#3063])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/shard-skl8/igt@gem_...@unwedge-stress.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-skl10/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][10] ([i915#4547])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-skl2/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/shard-tglb6/igt@gem_exec_fair@basic-p...@vecs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_params@secure-non-master:
- shard-tglb: NOTRUN -> [SKIP][14] ([fdo#112283])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-tglb2/igt@gem_exec_par...@secure-non-master.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-skl6/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_pread@exhaustion:
- shard-skl:  NOTRUN -> [WARN][16] ([i915#2658])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-skl10/igt@gem_pr...@exhaustion.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3323])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-kbl6/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@input-checking:
- shard-iclb: NOTRUN -> [DMESG-WARN][18] ([i915#3002])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-iclb8/igt@gem_userptr_bl...@input-checking.html

  * igt@gen7_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#109289]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21735/shard-tglb8/igt@gen7_exec_pa...@cmd-crossing-page.html

  * igt@gen9_exec_parse@allowed-single:
- shard-skl:  [PASS][20] -> [DMESG-WARN][21] ([i915#1436] / 
[i915#716])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/shard-skl8/igt@gen9_exec_pa...@allowed-single.html
   [21]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Assorted fixes/tweaks to GuC support

[Patchwork]

== Series Details ==

Series: Assorted fixes/tweaks to GuC support
URL   : https://patchwork.freedesktop.org/series/97514/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Assorted fixes/tweaks to GuC support

[Patchwork]

== Series Details ==

Series: Assorted fixes/tweaks to GuC support
URL   : https://patchwork.freedesktop.org/series/97514/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
394709d4751f drm/i915/uc: Allow platforms to have GuC but not HuC
-:36: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#36: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:51:
+#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \
+   fw_def(ALDERLAKE_P,  0, guc_def(adlp, 62, 0, 3)) \
+   fw_def(ALDERLAKE_S,  0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(DG1,  0, guc_def(dg1,  62, 0, 0)) \
+   fw_def(ROCKETLAKE,   0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(TIGERLAKE,0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(JASPERLAKE,   0, guc_def(ehl,  62, 0, 0)) \
+   fw_def(ELKHARTLAKE,  0, guc_def(ehl,  62, 0, 0)) \
+   fw_def(ICELAKE,  0, guc_def(icl,  62, 0, 0)) \
+   fw_def(COMETLAKE,5, guc_def(cml,  62, 0, 0)) \
+   fw_def(COMETLAKE,0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(COFFEELAKE,   0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(GEMINILAKE,   0, guc_def(glk,  62, 0, 0)) \
+   fw_def(KABYLAKE, 0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(BROXTON,  0, guc_def(bxt,  62, 0, 0)) \
+   fw_def(SKYLAKE,  0, guc_def(skl,  62, 0, 0))

-:36: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fw_def' - possible 
side-effects?
#36: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:51:
+#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \
+   fw_def(ALDERLAKE_P,  0, guc_def(adlp, 62, 0, 3)) \
+   fw_def(ALDERLAKE_S,  0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(DG1,  0, guc_def(dg1,  62, 0, 0)) \
+   fw_def(ROCKETLAKE,   0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(TIGERLAKE,0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(JASPERLAKE,   0, guc_def(ehl,  62, 0, 0)) \
+   fw_def(ELKHARTLAKE,  0, guc_def(ehl,  62, 0, 0)) \
+   fw_def(ICELAKE,  0, guc_def(icl,  62, 0, 0)) \
+   fw_def(COMETLAKE,5, guc_def(cml,  62, 0, 0)) \
+   fw_def(COMETLAKE,0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(COFFEELAKE,   0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(GEMINILAKE,   0, guc_def(glk,  62, 0, 0)) \
+   fw_def(KABYLAKE, 0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(BROXTON,  0, guc_def(bxt,  62, 0, 0)) \
+   fw_def(SKYLAKE,  0, guc_def(skl,  62, 0, 0))

-:36: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'guc_def' - possible 
side-effects?
#36: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:51:
+#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \
+   fw_def(ALDERLAKE_P,  0, guc_def(adlp, 62, 0, 3)) \
+   fw_def(ALDERLAKE_S,  0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(DG1,  0, guc_def(dg1,  62, 0, 0)) \
+   fw_def(ROCKETLAKE,   0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(TIGERLAKE,0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(JASPERLAKE,   0, guc_def(ehl,  62, 0, 0)) \
+   fw_def(ELKHARTLAKE,  0, guc_def(ehl,  62, 0, 0)) \
+   fw_def(ICELAKE,  0, guc_def(icl,  62, 0, 0)) \
+   fw_def(COMETLAKE,5, guc_def(cml,  62, 0, 0)) \
+   fw_def(COMETLAKE,0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(COFFEELAKE,   0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(GEMINILAKE,   0, guc_def(glk,  62, 0, 0)) \
+   fw_def(KABYLAKE, 0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(BROXTON,  0, guc_def(bxt,  62, 0, 0)) \
+   fw_def(SKYLAKE,  0, guc_def(skl,  62, 0, 0))

-:53: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#53: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:68:
+#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \
+   fw_def(ALDERLAKE_P,  0, huc_def(tgl,  7, 9, 3)) \
+   fw_def(ALDERLAKE_S,  0, huc_def(tgl,  7, 9, 3)) \
+   fw_def(DG1,  0, huc_def(dg1,  7, 9, 3)) \
+   fw_def(ROCKETLAKE,   0, huc_def(tgl,  7, 9, 3)) \
+   fw_def(TIGERLAKE,0, huc_def(tgl,  7, 9, 3)) \
+   fw_def(JASPERLAKE,   0, huc_def(ehl,  9, 0, 0)) \
+   fw_def(ELKHARTLAKE,  0, huc_def(ehl,  9, 0, 0)) \
+   fw_def(ICELAKE,  0, huc_def(icl,  9, 0, 0)) \
+   fw_def(COMETLAKE,5, huc_def(cml,  4, 0, 0)) \
+   fw_def(COMETLAKE,0, huc_def(kbl,  4, 0, 0)) \
+   fw_def(COFFEELAKE,   0, huc_def(kbl,  4, 0, 0)) \
+   fw_def(GEMINILAKE,   0, huc_def(glk,  4, 0, 0)) \
+   fw_def(KABYLAKE, 0, huc_def(kbl,  4, 0, 0)) \
+   fw_def(BROXTON,  0, huc_def(bxt,  2, 0, 0)) \
+   fw_def(SKYLAKE,  0, huc_def(skl,  2, 0, 0))

-:53: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fw_def' - possible 
side-effects?
#53: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:68:
+#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \
+   fw_def(ALDERLAKE_P,  0, huc_def(tgl,  7, 9, 3)) \
+   fw_def(ALDERLAKE_S,  0, huc_def(tgl,  7, 9, 3)) \
+   fw_def(DG1,  0, huc_def(dg1,  7, 9, 3)) \
+   fw_def(ROCKETLAKE,   0, huc_def(tgl,  7, 9, 3)) \
+   

Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/dg2: extend Wa_1409120013 to DG2

[Clint Taylor]

Reviewed-by: Clint Taylor 

-Clint

On 11/16/21 9:48 AM, Matt Roper wrote:

From: Matt Atwood 

Extend existing workaround 1409120013 to DG2.

Cc: José Roberto de Souza 
Signed-off-by: Matt Atwood 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/intel_pm.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89dc7f69baf3..e721c421cc58 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7444,9 +7444,9 @@ static void icl_init_clock_gating(struct drm_i915_private 
*dev_priv)
  
  static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)

  {
-   /* Wa_1409120013:tgl,rkl,adl-s,dg1 */
+   /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
-   IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
+   IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
intel_uncore_write(_priv->uncore, ILK_DPFC_CHICKEN,
   DPFC_CHICKEN_COMP_DUMMY_PIXEL);
  

[Intel-gfx] [PATCH 3/4] drm/i915/guc: Increase GuC log size for CONFIG_DEBUG_GEM

[John . C . Harrison]

From: John Harrison 

Lots of testing is done with the DEBUG_GEM config option enabled but
not the DEBUG_GUC option. That means we only get teeny-tiny GuC logs
which are not hugely useful. Enabling full DEBUG_GUC also spews lots
of other detailed output that is not generally desired. However,
bigger GuC logs are extremely useful for almost any regression debug.
So enable bigger logs for DEBUG_GEM builds as well.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
index ac1ee1d5ce10..fe6ab7550a14 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
@@ -15,9 +15,12 @@
 
 struct intel_guc;
 
-#ifdef CONFIG_DRM_I915_DEBUG_GUC
+#if defined(CONFIG_DRM_I915_DEBUG_GUC)
 #define CRASH_BUFFER_SIZE  SZ_2M
 #define DEBUG_BUFFER_SIZE  SZ_16M
+#elif defined(CONFIG_DRM_I915_DEBUG_GEM)
+#define CRASH_BUFFER_SIZE  SZ_1M
+#define DEBUG_BUFFER_SIZE  SZ_2M
 #else
 #define CRASH_BUFFER_SIZE  SZ_8K
 #define DEBUG_BUFFER_SIZE  SZ_64K
-- 
2.25.1

[Intel-gfx] [PATCH 2/4] drm/i915/guc: Request RP0 before loading firmware

[John . C . Harrison]

From: Vinay Belgaumkar 

By default, GT (and GuC) run at RPn. Requesting for RP0
before firmware load can speed up DMA and HuC auth as well.
In addition to writing to 0xA008, we also need to enable
swreq in 0xA024 so that Punit will pay heed to our request.

Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/intel_rps.c   | 59 +++
 drivers/gpu/drm/i915/gt/intel_rps.h   |  2 +
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  6 +++
 drivers/gpu/drm/i915/i915_reg.h   |  4 ++
 4 files changed, 71 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 07ff7ba7b2b7..4f7fe079ed4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2226,6 +2226,65 @@ u32 intel_rps_read_state_cap(struct intel_rps *rps)
return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
 }
 
+static void intel_rps_set_manual(struct intel_rps *rps, bool enable)
+{
+   struct intel_uncore *uncore = rps_to_uncore(rps);
+   u32 state = enable ? GEN9_RPSWCTL_ENABLE : GEN9_RPSWCTL_DISABLE;
+
+   if (enable)
+   intel_rps_clear_timer(rps);
+
+   /* Allow punit to process software requests */
+   intel_uncore_write(uncore, GEN6_RP_CONTROL, state);
+
+   if (!enable)
+   intel_rps_set_timer(rps);
+}
+
+void intel_rps_raise_unslice(struct intel_rps *rps)
+{
+   struct intel_uncore *uncore = rps_to_uncore(rps);
+   u32 rp0_unslice_req;
+
+   intel_rps_set_manual(rps, true);
+
+   /* RP limits have not been read yet */
+   if (!rps->rp0_freq)
+   rp0_unslice_req = ((intel_rps_read_state_cap(rps) >> 0)
+  & 0xff) * GEN9_FREQ_SCALER;
+   else
+   rp0_unslice_req = rps->rp0_freq;
+
+   intel_uncore_write(uncore, GEN6_RPNSWREQ,
+  ((rp0_unslice_req <<
+  GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) |
+  GEN9_IGNORE_SLICE_RATIO));
+
+   intel_rps_set_manual(rps, false);
+}
+
+void intel_rps_lower_unslice(struct intel_rps *rps)
+{
+   struct intel_uncore *uncore = rps_to_uncore(rps);
+   u32 rpn_unslice_req;
+
+   intel_rps_set_manual(rps, true);
+
+   /* RP limits have not been read yet */
+   if (!rps->min_freq)
+   rpn_unslice_req = ((intel_rps_read_state_cap(rps) >> 16)
+  & 0xff) * GEN9_FREQ_SCALER;
+   else
+   rpn_unslice_req = rps->min_freq;
+
+   intel_uncore_write(uncore, GEN6_RPNSWREQ,
+  ((rpn_unslice_req <<
+  GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) |
+  GEN9_IGNORE_SLICE_RATIO));
+
+   intel_rps_set_manual(rps, false);
+}
+
 /* External interface for intel_ips.ko */
 
 static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h 
b/drivers/gpu/drm/i915/gt/intel_rps.h
index aee12f37d38a..c6d76a3d1331 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -45,6 +45,8 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
 u32 intel_rps_read_punit_req(struct intel_rps *rps);
 u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
 u32 intel_rps_read_state_cap(struct intel_rps *rps);
+void intel_rps_raise_unslice(struct intel_rps *rps);
+void intel_rps_lower_unslice(struct intel_rps *rps);
 
 void gen5_rps_irq_handler(struct intel_rps *rps);
 void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 2fef3b0bbe95..ed7180b79a6f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -8,6 +8,7 @@
 #include "intel_guc.h"
 #include "intel_guc_ads.h"
 #include "intel_guc_submission.h"
+#include "gt/intel_rps.h"
 #include "intel_uc.h"
 
 #include "i915_drv.h"
@@ -462,6 +463,8 @@ static int __uc_init_hw(struct intel_uc *uc)
else
attempts = 1;
 
+   intel_rps_raise_unslice(_to_gt(uc)->rps);
+
while (attempts--) {
/*
 * Always reset the GuC just before (re)loading, so
@@ -529,6 +532,9 @@ static int __uc_init_hw(struct intel_uc *uc)
 err_log_capture:
__uc_capture_load_err_log(uc);
 err_out:
+   /* Return GT back to RPn */
+   intel_rps_lower_unslice(_to_gt(uc)->rps);
+
__uc_sanitize(uc);
 
if (!ret) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3450818802c2..229d33a65891 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9415,6 +9415,7 @@ enum {
 #define   GEN6_OFFSET(x)   ((x) << 19)
 #define   GEN6_AGGRESSIVE_TURBO(0 << 15)
 #define   GEN9_SW_REQ_UNSLICE_RATIO_SHIFT  23
+#define   GEN9_IGNORE_SLICE_RATIO  (0 << 0)
 
 

[Intel-gfx] [PATCH 0/4] Assorted fixes/tweaks to GuC support

[John . C . Harrison]

From: John Harrison 

Fix a potential null pointer dereference, improve debug crash reports,
improve code separation, improve GuC/HuC load performance.

Signed-off-by: John Harrison 



John Harrison (3):
  drm/i915/uc: Allow platforms to have GuC but not HuC
  drm/i915/guc: Increase GuC log size for CONFIG_DEBUG_GEM
  drm/i915/guc: Don't go bang in GuC log if no GuC

Vinay Belgaumkar (1):
  drm/i915/guc: Request RP0 before loading firmware

 drivers/gpu/drm/i915/gt/intel_rps.c   | 59 
 drivers/gpu/drm/i915/gt/intel_rps.h   |  2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h|  5 +-
 .../drm/i915/gt/uc/intel_guc_log_debugfs.c|  4 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  6 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 93 +--
 drivers/gpu/drm/i915/i915_reg.h   |  4 +
 7 files changed, 140 insertions(+), 33 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH 1/4] drm/i915/uc: Allow platforms to have GuC but not HuC

[John . C . Harrison]

From: John Harrison 

It is possible for platforms to require GuC but not HuC firmware.
Also, the firmware versions for GuC and HuC advance independently. So
split the macros up to allow the lists to be maintained separately.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 93 
 1 file changed, 63 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 3aa87be4f2e4..a7788ce50736 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -48,22 +48,39 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same
  * firmware as TGL.
  */
-#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
-   fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3), huc_def(tgl, 7, 9, 3)) \
-   fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 9, 3)) \
-   fw_def(DG1, 0, guc_def(dg1, 62, 0, 0), huc_def(dg1,  7, 9, 3)) \
-   fw_def(ROCKETLAKE,  0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 9, 3)) \
-   fw_def(TIGERLAKE,   0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 9, 3)) \
-   fw_def(JASPERLAKE,  0, guc_def(ehl, 62, 0, 0), huc_def(ehl,  9, 0, 0)) \
-   fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl,  9, 0, 0)) \
-   fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0), huc_def(icl,  9, 0, 0)) \
-   fw_def(COMETLAKE,   5, guc_def(cml, 62, 0, 0), huc_def(cml,  4, 0, 0)) \
-   fw_def(COMETLAKE,   0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
-   fw_def(COFFEELAKE,  0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
-   fw_def(GEMINILAKE,  0, guc_def(glk, 62, 0, 0), huc_def(glk,  4, 0, 0)) \
-   fw_def(KABYLAKE,0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
-   fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0), huc_def(bxt,  2, 0, 0)) \
-   fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0), huc_def(skl,  2, 0, 0))
+#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \
+   fw_def(ALDERLAKE_P,  0, guc_def(adlp, 62, 0, 3)) \
+   fw_def(ALDERLAKE_S,  0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(DG1,  0, guc_def(dg1,  62, 0, 0)) \
+   fw_def(ROCKETLAKE,   0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(TIGERLAKE,0, guc_def(tgl,  62, 0, 0)) \
+   fw_def(JASPERLAKE,   0, guc_def(ehl,  62, 0, 0)) \
+   fw_def(ELKHARTLAKE,  0, guc_def(ehl,  62, 0, 0)) \
+   fw_def(ICELAKE,  0, guc_def(icl,  62, 0, 0)) \
+   fw_def(COMETLAKE,5, guc_def(cml,  62, 0, 0)) \
+   fw_def(COMETLAKE,0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(COFFEELAKE,   0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(GEMINILAKE,   0, guc_def(glk,  62, 0, 0)) \
+   fw_def(KABYLAKE, 0, guc_def(kbl,  62, 0, 0)) \
+   fw_def(BROXTON,  0, guc_def(bxt,  62, 0, 0)) \
+   fw_def(SKYLAKE,  0, guc_def(skl,  62, 0, 0))
+
+#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \
+   fw_def(ALDERLAKE_P,  0, huc_def(tgl,  7, 9, 3)) \
+   fw_def(ALDERLAKE_S,  0, huc_def(tgl,  7, 9, 3)) \
+   fw_def(DG1,  0, huc_def(dg1,  7, 9, 3)) \
+   fw_def(ROCKETLAKE,   0, huc_def(tgl,  7, 9, 3)) \
+   fw_def(TIGERLAKE,0, huc_def(tgl,  7, 9, 3)) \
+   fw_def(JASPERLAKE,   0, huc_def(ehl,  9, 0, 0)) \
+   fw_def(ELKHARTLAKE,  0, huc_def(ehl,  9, 0, 0)) \
+   fw_def(ICELAKE,  0, huc_def(icl,  9, 0, 0)) \
+   fw_def(COMETLAKE,5, huc_def(cml,  4, 0, 0)) \
+   fw_def(COMETLAKE,0, huc_def(kbl,  4, 0, 0)) \
+   fw_def(COFFEELAKE,   0, huc_def(kbl,  4, 0, 0)) \
+   fw_def(GEMINILAKE,   0, huc_def(glk,  4, 0, 0)) \
+   fw_def(KABYLAKE, 0, huc_def(kbl,  4, 0, 0)) \
+   fw_def(BROXTON,  0, huc_def(bxt,  2, 0, 0)) \
+   fw_def(SKYLAKE,  0, huc_def(skl,  2, 0, 0))
 
 #define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
"i915/" \
@@ -79,11 +96,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
__MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
 
 /* All blobs need to be declared via MODULE_FIRMWARE() */
-#define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
-   MODULE_FIRMWARE(guc_); \
-   MODULE_FIRMWARE(huc_);
+#define INTEL_UC_MODULE_FW(platform_, revid_, uc_) \
+   MODULE_FIRMWARE(uc_);
 
-INTEL_UC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH, MAKE_HUC_FW_PATH)
+INTEL_GUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH)
+INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH)
 
 /* The below structs and macros are used to iterate across the list of blobs */
 struct __packed uc_fw_blob {
@@ -106,31 +123,47 @@ struct __packed uc_fw_blob {
 struct __packed uc_fw_platform_requirement {
enum intel_platform p;
u8 rev; /* first platform rev using this FW */
-   const struct uc_fw_blob 

[Intel-gfx] [PATCH 4/4] drm/i915/guc: Don't go bang in GuC log if no GuC

[John . C . Harrison]

From: John Harrison 

If the GuC has failed to load for any reason and then the user pokes
the debugfs GuC log interface, a BUG and/or null pointer deref can
occur. Don't let that happen.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
index 46026c2c1722..8fd068049376 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
@@ -31,7 +31,7 @@ static int guc_log_level_get(void *data, u64 *val)
 {
struct intel_guc_log *log = data;
 
-   if (!intel_guc_is_used(log_to_guc(log)))
+   if (!log->vma)
return -ENODEV;
 
*val = intel_guc_log_get_level(log);
@@ -43,7 +43,7 @@ static int guc_log_level_set(void *data, u64 val)
 {
struct intel_guc_log *log = data;
 
-   if (!intel_guc_is_used(log_to_guc(log)))
+   if (!log->vma)
return -ENODEV;
 
return intel_guc_log_set_level(log, val);
-- 
2.25.1

[Intel-gfx] [CI] PR for new GuC v69.0.0

[John . C . Harrison]

The following changes since commit b0e898fbaf377c99a36aac6fdeb7250003648ca4:

  linux-firmware: Update firmware file for Intel Bluetooth 9462 (2021-11-23 
12:31:45 -0500)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware guc_v69

for you to fetch changes up to 36c3001997776f4e6b8225a110849c7f61a51acb:

  i915: Add GuC v69.0.0 for all platforms (2021-12-02 16:16:09 -0800)


John Harrison (1):
  i915: Add GuC v69.0.0 for all platforms

 WHENCE   |  30 ++
 i915/adlp_guc_69.0.0.bin | Bin 0 -> 356992 bytes
 i915/bxt_guc_69.0.0.bin  | Bin 0 -> 216128 bytes
 i915/cml_guc_69.0.0.bin  | Bin 0 -> 217024 bytes
 i915/dg1_guc_69.0.0.bin  | Bin 0 -> 324864 bytes
 i915/ehl_guc_69.0.0.bin  | Bin 0 -> 344576 bytes
 i915/glk_guc_69.0.0.bin  | Bin 0 -> 216640 bytes
 i915/icl_guc_69.0.0.bin  | Bin 0 -> 344576 bytes
 i915/kbl_guc_69.0.0.bin  | Bin 0 -> 217024 bytes
 i915/skl_guc_69.0.0.bin  | Bin 0 -> 216064 bytes
 i915/tgl_guc_69.0.0.bin  | Bin 0 -> 344128 bytes
 11 files changed, 30 insertions(+)
 create mode 100644 i915/adlp_guc_69.0.0.bin
 create mode 100644 i915/bxt_guc_69.0.0.bin
 create mode 100644 i915/cml_guc_69.0.0.bin
 create mode 100644 i915/dg1_guc_69.0.0.bin
 create mode 100644 i915/ehl_guc_69.0.0.bin
 create mode 100644 i915/glk_guc_69.0.0.bin
 create mode 100644 i915/icl_guc_69.0.0.bin
 create mode 100644 i915/kbl_guc_69.0.0.bin
 create mode 100644 i915/skl_guc_69.0.0.bin
 create mode 100644 i915/tgl_guc_69.0.0.bin

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Re-use i915 macros for checking PTEs (rev12)

[Patchwork]

== Series Details ==

Series: drm/i915: Re-use i915 macros for checking PTEs (rev12)
URL   : https://patchwork.freedesktop.org/series/97090/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10957 -> Patchwork_21736


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_21736 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21736, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/index.html

Participating hosts (38 -> 35)
--

  Additional (2): fi-kbl-soraka fi-pnv-d510 
  Missing(5): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-jsl-2 bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_21736:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gem_contexts:
- fi-skl-6600u:   [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-kefka:   [PASS][3] -> [DMESG-FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
- fi-glk-dsi: [PASS][5] -> [DMESG-FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-skl-6700k2:  NOTRUN -> [DMESG-FAIL][7]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-8700k:   [PASS][8] -> [DMESG-FAIL][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-n3050:   [PASS][10] -> [DMESG-FAIL][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-7567u:   [PASS][12] -> [DMESG-FAIL][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html
- fi-cfl-guc: [PASS][14] -> [DMESG-FAIL][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-bxt-dsi: [PASS][16] -> [DMESG-FAIL][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-kbl-7500u:   [PASS][18] -> [DMESG-FAIL][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10957/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html

  
Known issues


  Here are the changes found in Patchwork_21736 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-skl-6700k2:  NOTRUN -> [SKIP][20] ([fdo#109271]) +23 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-skl-6700k2/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-ivb-3770:NOTRUN -> [SKIP][21] ([fdo#109271]) +17 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-ivb-3770/igt@amdgpu/amd_cs_...@fork-compute0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][22] ([fdo#109271]) +8 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21736/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#2190])
   [23]: 

[Intel-gfx] [PATCH] drm/i915: Fix possible null ptr dereferences

[Pallavi Mishra]

add null ptr checks to prevent crash/exceptions.

Signed-off-by: Pallavi Mishra 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c  | 3 +++
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 3 ++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 218a9b3037c7..997fe73c205b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -906,6 +906,8 @@ vm_access_ttm(struct vm_area_struct *area, unsigned long 
addr,
struct drm_i915_gem_object *obj =
i915_ttm_to_gem(area->vm_private_data);
 
+   GEM_BUG_ON(!obj);
+
if (i915_gem_object_is_readonly(obj) && write)
return -EACCES;
 
@@ -966,6 +968,7 @@ static const struct drm_i915_gem_object_ops 
i915_gem_ttm_obj_ops = {
 void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
 {
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+   GEM_BUG_ON(!obj);
 
i915_gem_object_release_memory_region(obj);
mutex_destroy(>ttm.get_io_page.lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 80df9f592407..2b684903a9f5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -371,6 +371,7 @@ int i915_ttm_move_notify(struct ttm_buffer_object *bo)
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
int ret;
 
+   GEM_BUG_ON(!obj);
ret = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
if (ret)
return ret;
@@ -506,7 +507,7 @@ static void i915_ttm_memcpy_init(struct i915_ttm_memcpy_arg 
*arg,
 
dst_reg = i915_ttm_region(bo->bdev, dst_mem->mem_type);
src_reg = i915_ttm_region(bo->bdev, bo->resource->mem_type);
-   GEM_BUG_ON(!dst_reg || !src_reg);
+   GEM_BUG_ON(!dst_reg || !src_reg || !obj);
 
arg->dst_iter = !i915_ttm_cpu_maps_iomem(dst_mem) ?
ttm_kmap_iter_tt_init(>_dst_iter.tt, dst_ttm) :
-- 
2.25.1

Re: [Intel-gfx] [PATCH bpf v2] treewide: add missing includes masked by cgroup -> bpf dependency

[Christoph Hellwig]

Thanks, always good to see someone else helping to unwind our include
dependency mess..

Reviewed-by: Christoph Hellwig 

[Intel-gfx] [v2] drm/i915/adl_p: Fix ddc pin mapping

[ravitejax . goud . talla]

From: Tejas Upadhyay 

>From VBT, ddc pin info suggests the following mapping:
VBTDRIVER
DDI TC1->ddc_pin=3 should translate to PORT_TC1->0x9
DDI TC2->ddc_pin=4 should translate to PORT_TC2->0xa
DDI TC3->ddc_pin=5 should translate to PORT_TC3->0xb
DDI TC4->ddc_pin=6 should translate to PORT_TC4->0xc

Adding pin map to facilitate this translation as we cannot use existing
icl ddc pin map due to conflict with DDI C and DDI TC1 info.

Bspec:20124

v2:
  - Changed Author to Tejas Upadhyay

Cc: Clinton Taylor 
Cc: Matt Atwood 
Cc: Matt Roper 
Acked-by: Imre Deak 
Signed-off-by: Lee Shawn C 
Signed-off-by: Tejas Upadhyay 
Signed-off-by: Raviteja Goud Talla 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 14 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++-
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 2b1423a43437..9d989c9f5da4 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1555,12 +1555,24 @@ static const u8 gen9bc_tgp_ddc_pin_map[] = {
[DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP,
 };
 
+static const u8 adlp_ddc_pin_map[] = {
+   [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+   [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+   [ADLP_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
+   [ADLP_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
+   [ADLP_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
+   [ADLP_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
+};
+
 static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
 {
const u8 *ddc_pin_map;
int n_entries;
 
-   if (IS_ALDERLAKE_S(i915)) {
+   if (IS_ALDERLAKE_P(i915)) {
+   ddc_pin_map = adlp_ddc_pin_map;
+   n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
+   } else if (IS_ALDERLAKE_S(i915)) {
ddc_pin_map = adls_ddc_pin_map;
n_entries = ARRAY_SIZE(adls_ddc_pin_map);
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index a2108a8f544d..f043d85ba64d 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -330,7 +330,12 @@ enum vbt_gmbus_ddi {
ADLS_DDC_BUS_PORT_TC1 = 0x2,
ADLS_DDC_BUS_PORT_TC2,
ADLS_DDC_BUS_PORT_TC3,
-   ADLS_DDC_BUS_PORT_TC4
+   ADLS_DDC_BUS_PORT_TC4,
+   ADLP_DDC_BUS_PORT_TC1 = 0x3,
+   ADLP_DDC_BUS_PORT_TC2,
+   ADLP_DDC_BUS_PORT_TC3,
+   ADLP_DDC_BUS_PORT_TC4
+
 };
 
 #define DP_AUX_A 0x40
-- 
2.34.1

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Additional DG2 workarounds (rev3)

[Matt Roper]

On Wed, Nov 17, 2021 at 04:50:33AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: i915: Additional DG2 workarounds (rev3)
> URL   : https://patchwork.freedesktop.org/series/96824/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_10888_full -> Patchwork_21604_full
> 
> 
> Summary
> ---
> 
>   **SUCCESS**
> 
>   No regressions found.
> 

Thanks Clint and Jani for the reviews.  Applied to drm-intel-next
(#1, #2, #5) and drm-intel-gt-next (#3, #4)


Matt

>   
> 
> Participating hosts (11 -> 10)
> --
> 
>   Missing(1): shard-rkl 
> 
> Known issues
> 
> 
>   Here are the changes found in Patchwork_21604_full that come from known 
> issues:
> 
> ### CI changes ###
> 
>  Issues hit 
> 
>   * boot:
> - shard-apl:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
> [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], 
> [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], 
> [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], 
> [PASS][23], [PASS][24], [PASS][25]) -> ([FAIL][26], [PASS][27], [PASS][28], 
> [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], 
> [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], 
> [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], 
> [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4386])
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl8/boot.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl8/boot.html
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl8/boot.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl7/boot.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl7/boot.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl7/boot.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl6/boot.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl6/boot.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl6/boot.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl6/boot.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl4/boot.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl4/boot.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl4/boot.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl4/boot.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl3/boot.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl3/boot.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl3/boot.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl3/boot.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl3/boot.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl2/boot.html
>[21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl2/boot.html
>[22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl2/boot.html
>[23]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl1/boot.html
>[24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl1/boot.html
>[25]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10888/shard-apl1/boot.html
>[26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl1/boot.html
>[27]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl1/boot.html
>[28]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl1/boot.html
>[29]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl1/boot.html
>[30]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl1/boot.html
>[31]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl2/boot.html
>[32]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl2/boot.html
>[33]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl2/boot.html
>[34]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl3/boot.html
>[35]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl3/boot.html
>[36]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl3/boot.html
>[37]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl4/boot.html
>[38]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21604/shard-apl4/boot.html
>[39]: 
> 

[Intel-gfx] [v3 1/3] drm/i915/rpl-s: Add PCI IDS for Raptor Lake S

[Anusha Srivatsa]

Raptor Lake S(RPL-S) is a version 12
Display, Media and Render. For all i915
purposes it is the same as Alder Lake S (ADL-S).

Introduce RPL-S as a subplatform
of ADL-S. This patch adds PCI ids for RPL-S.

v2: Update PCI IDs.
- Add more description to commit message (Jani)

v3: s/IS_RAPTORLAKE/IS_ADLS_RPLS (Jani)
- Fix comment (Tvrtko)

BSpec: 53655

Cc: x...@kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: Ingo Molnar 
Cc: Borislav Petkov 
Cc: Dave Hansen 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Cc: Matt Roper 
Cc: Jani Nikula 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: José Roberto de Souza 
---
 arch/x86/kernel/early-quirks.c   | 1 +
 drivers/gpu/drm/i915/i915_drv.h  | 2 ++
 drivers/gpu/drm/i915/i915_pci.c  | 1 +
 drivers/gpu/drm/i915/intel_device_info.c | 7 +++
 drivers/gpu/drm/i915/intel_device_info.h | 3 +++
 include/drm/i915_pciids.h| 9 +
 6 files changed, 23 insertions(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 391a4e2b8604..fd2d3ab38ebb 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -554,6 +554,7 @@ static const struct pci_device_id intel_early_ids[] 
__initconst = {
INTEL_RKL_IDS(_early_ops),
INTEL_ADLS_IDS(_early_ops),
INTEL_ADLP_IDS(_early_ops),
+   INTEL_RPLS_IDS(_early_ops),
 };
 
 struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 
0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e1192aeef90..fe36d0f5da67 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1469,6 +1469,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 #define IS_DG2_G11(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
+#define IS_ADLS_RPLS(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f01cba4ec283..061b2e076373 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1131,6 +1131,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_ADLS_IDS(_s_info),
INTEL_ADLP_IDS(_p_info),
INTEL_DG1_IDS(_info),
+   INTEL_RPLS_IDS(_s_info),
{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index e6605b5181a5..a3446a2abcb2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -170,6 +170,10 @@ static const u16 subplatform_portf_ids[] = {
INTEL_ICL_PORT_F_IDS(0),
 };
 
+static const u16 subplatform_rpls_ids[] = {
+   INTEL_RPLS_IDS(0),
+};
+
 static bool find_devid(u16 id, const u16 *p, unsigned int num)
 {
for (; num; num--, p++) {
@@ -206,6 +210,9 @@ void intel_device_info_subplatform_init(struct 
drm_i915_private *i915)
} else if (find_devid(devid, subplatform_portf_ids,
  ARRAY_SIZE(subplatform_portf_ids))) {
mask = BIT(INTEL_SUBPLATFORM_PORTF);
+   } else if (find_devid(devid, subplatform_rpls_ids,
+ ARRAY_SIZE(subplatform_rpls_ids))) {
+   mask = BIT(INTEL_SUBPLATFORM_RPL_S);
}
 
if (IS_TIGERLAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 669f0d26c3c3..2bedf73e0a7d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -110,6 +110,9 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_G10  0
 #define INTEL_SUBPLATFORM_G11  1
 
+/* ADL-S */
+#define INTEL_SUBPLATFORM_RPL_S0
+
 enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index c00ac54692d7..baf3d1d3d566 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -666,4 +666,13 @@
INTEL_VGA_DEVICE(0x46C2, info), \
INTEL_VGA_DEVICE(0x46C3, info)
 
+/* RPL-S */
+#define INTEL_RPLS_IDS(info) \
+   INTEL_VGA_DEVICE(0xA780, info), \
+   INTEL_VGA_DEVICE(0xA781, info), \
+   INTEL_VGA_DEVICE(0xA782, info), \
+   INTEL_VGA_DEVICE(0xA783, info), \
+   INTEL_VGA_DEVICE(0xA788, info), \
+   INTEL_VGA_DEVICE(0xA789, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
2.25.1

[Intel-gfx] [v3 2/3] drm/i915/rpl-s: Add PCH Support for Raptor Lake S

[Anusha Srivatsa]

Add the PCH ID for RPL-S.

v2: Self contained commit message (Jani)

Cc: dri-de...@lists.freedesktop.org
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/intel_pch.c | 1 +
 drivers/gpu/drm/i915/intel_pch.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index d1d4b97b86f5..da8f82c2342f 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -129,6 +129,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, 
unsigned short id)
return PCH_JSP;
case INTEL_PCH_ADP_DEVICE_ID_TYPE:
case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
+   case INTEL_PCH_ADP3_DEVICE_ID_TYPE:
drm_dbg_kms(_priv->drm, "Found Alder Lake PCH\n");
drm_WARN_ON(_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
!IS_ALDERLAKE_P(dev_priv));
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 7c0d83d292dc..6bff77521094 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -57,6 +57,7 @@ enum intel_pch {
 #define INTEL_PCH_JSP2_DEVICE_ID_TYPE  0x3880
 #define INTEL_PCH_ADP_DEVICE_ID_TYPE   0x7A80
 #define INTEL_PCH_ADP2_DEVICE_ID_TYPE  0x5180
+#define INTEL_PCH_ADP3_DEVICE_ID_TYPE  0x7A00
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE   0x7100
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE   0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE  0x2900 /* qemu q35 has 2918 */
-- 
2.25.1

[Intel-gfx] [v3 0/3] Introduce Raptor Lake S

[Anusha Srivatsa]

Raptor Lake S(RPL-S) is a version 12
Display, Media and Render. For all i915
purposes it is the same as Alder Lake S (ADL-S).

The series introduces it as a subplatform
of ADL-S. The one difference is the GuC
submission which is default on RPL-S but
was not the case with ADL-S.

All patches are reviewed. Jani has acked the series.
Looking for other acks in order to merge these to
respective branches.

Cc: x...@kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: Ingo Molnar 
Cc: Borislav Petkov 
Cc: Dave Hansen 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Acked-by: Jani Nikula 

Anusha Srivatsa (3):
  drm/i915/rpl-s: Add PCI IDS for Raptor Lake S
  drm/i915/rpl-s: Add PCH Support for Raptor Lake S
  drm/i915/rpl-s: Enable guc submission by default

 arch/x86/kernel/early-quirks.c   | 1 +
 drivers/gpu/drm/i915/gt/uc/intel_uc.c| 2 +-
 drivers/gpu/drm/i915/i915_drv.h  | 2 ++
 drivers/gpu/drm/i915/i915_pci.c  | 1 +
 drivers/gpu/drm/i915/intel_device_info.c | 7 +++
 drivers/gpu/drm/i915/intel_device_info.h | 3 +++
 drivers/gpu/drm/i915/intel_pch.c | 1 +
 drivers/gpu/drm/i915/intel_pch.h | 1 +
 include/drm/i915_pciids.h| 9 +
 9 files changed, 26 insertions(+), 1 deletion(-)

-- 
2.25.1

[Intel-gfx] [v3 3/3] drm/i915/rpl-s: Enable guc submission by default

[Anusha Srivatsa]

Though, RPL-S is defined as subplatform of ADL-S, unlike
ADL-S, it has GuC submission by default.

v2: Remove extra parenthesis (Jani)
v3: s/IS_RAPTORLAKE/IS_ADLS_RPLS (Jani)

Cc: dri-de...@lists.freedesktop.org
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 2fef3b0bbe95..8f17005ce85f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -35,7 +35,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
}
 
/* Intermediate platforms are HuC authentication only */
-   if (IS_ALDERLAKE_S(i915)) {
+   if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
return;
}
-- 
2.25.1

Re: [Intel-gfx] [PATCH bpf v2] treewide: add missing includes masked by cgroup -> bpf dependency

[Greg KH]

On Thu, Dec 02, 2021 at 12:34:00PM -0800, Jakub Kicinski wrote:
> cgroup.h (therefore swap.h, therefore half of the universe)
> includes bpf.h which in turn includes module.h and slab.h.
> Since we're about to get rid of that dependency we need
> to clean things up.
> 
> v2: drop the cpu.h include from cacheinfo.h, it's not necessary
> and it makes riscv sensitive to ordering of include files.
> 
> Link: https://lore.kernel.org/all/20211120035253.72074-1-k...@kernel.org/  # 
> v1
> Link: https://lore.kernel.org/all/20211120165528.197359-1-k...@kernel.org/ # 
> cacheinfo discussion
> Acked-by: Krzysztof Wilczyński 
> Acked-by: Peter Chen 
> Acked-by: SeongJae Park 
> Acked-by: Jani Nikula 
> Signed-off-by: Jakub Kicinski 

Acked-by: Greg Kroah-Hartman 

[Intel-gfx] [PULL] drm-misc-fixes

[Maxime Ripard]

Hi Dave, Daniel,

Here's this week drm-misc-fixes PR

Maxime

drm-misc-fixes-2021-12-02:
Switch back to drm_poll for virtio, multiple fixes (memory leak,
improper error check, some functional fixes too) for vc4, memory leak
fix in dma-buf,
The following changes since commit e048834c209a02e3776bcc47d43c6d863e3a67ca:

  drm/hyperv: Fix device removal on Gen1 VMs (2021-11-23 10:56:12 -0800)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2021-12-02

for you to fetch changes up to 679d94cd7d900871e5bc9cf780bd5b73af35ab42:

  dma-buf: system_heap: Use 'for_each_sgtable_sg' in pages free flow 
(2021-12-01 15:30:10 +0530)


Switch back to drm_poll for virtio, multiple fixes (memory leak,
improper error check, some functional fixes too) for vc4, memory leak
fix in dma-buf,


Guangming (1):
  dma-buf: system_heap: Use 'for_each_sgtable_sg' in pages free flow

Gurchetan Singh (2):
  drm/virtgpu api: define a dummy fence signaled event
  drm/virtio: use drm_poll(..) instead of virtio_gpu_poll(..)

Maxime Ripard (6):
  drm/vc4: kms: Wait for the commit before increasing our clock rate
  drm/vc4: kms: Fix return code check
  drm/vc4: kms: Add missing drm_crtc_commit_put
  drm/vc4: kms: Clear the HVS FIFO commit pointer once done
  drm/vc4: kms: Don't duplicate pending commit
  drm/vc4: kms: Fix previous HVS commit wait

 drivers/dma-buf/heaps/system_heap.c|  2 +-
 drivers/gpu/drm/vc4/vc4_kms.c  | 42 +++---
 drivers/gpu/drm/virtio/virtgpu_drv.c   | 42 +-
 drivers/gpu/drm/virtio/virtgpu_drv.h   |  1 -
 drivers/gpu/drm/virtio/virtgpu_ioctl.c |  2 +-
 include/uapi/drm/virtgpu_drm.h |  7 ++
 6 files changed, 29 insertions(+), 67 deletions(-)


signature.asc
Description: PGP signature

[Intel-gfx] ✓ Fi.CI.BAT: success for Replace VT-d workaround with guard pages

[Patchwork]

== Series Details ==

Series: Replace VT-d workaround with guard pages
URL   : https://patchwork.freedesktop.org/series/97492/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10953 -> Patchwork_21726


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/index.html

Participating hosts (38 -> 31)
--

  Additional (1): fi-bdw-gvtdvm 
  Missing(8): fi-kbl-soraka fi-tgl-dsi bat-dg1-6 bat-dg1-5 fi-bsw-cyan 
bat-adlp-6 bat-jsl-2 bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_21726 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@write:
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][1] ([fdo#109271]) +5 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-bdw-gvtdvm/igt@fb...@write.html

  * igt@gem_exec_suspend@basic-s0:
- fi-bdw-gvtdvm:  NOTRUN -> [INCOMPLETE][2] ([i915#146] / [i915#2539])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s0.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u:   NOTRUN -> [SKIP][6] ([fdo#109271]) +2 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u:   NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_page_flip:
- fi-skl-6600u:   NOTRUN -> [FAIL][8] ([i915#4547])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  * igt@runner@aborted:
- fi-skl-6600u:   NOTRUN -> [FAIL][9] ([i915#3363] / [i915#4312])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-skl-6600u/igt@run...@aborted.html
- fi-bdw-5557u:   NOTRUN -> [FAIL][10] ([i915#2426] / [i915#4312])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-bdw-5557u/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4:  [FAIL][11] ([i915#1888]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html

  * igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u:   [INCOMPLETE][13] ([i915#4547]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21726/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-

  * Linux: CI_DRM_10953 -> Patchwork_21726

  CI-20190529: 20190529
  CI_DRM_10953: 494fe33df24acee4952c6ea1c946320aac86b7ba @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6298: f062f4ae60ecf47af4b037c8f9952a1360662579 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21726: 3ab5c1e98b0767df26d9643961ce970ad880113a @ 
git://anongit.freedesktop.org/gfx-ci/linux

[Intel-gfx] ✓ Fi.CI.IGT: success for static analysis failure

[Patchwork]

== Series Details ==

Series: static analysis failure
URL   : https://patchwork.freedesktop.org/series/97486/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10953_full -> Patchwork_21724_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_21724_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-glk:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [FAIL][22], [PASS][23], 
[PASS][24], [PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], 
[PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], 
[PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], 
[PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], 
[PASS][47], [PASS][48], [PASS][49], [PASS][50])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk9/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk9/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk8/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk8/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk7/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk6/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk5/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk3/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk2/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk2/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk2/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk1/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk1/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk1/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk3/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk3/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk2/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk2/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk2/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk1/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk1/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk1/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk9/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk9/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk8/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk8/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk7/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk7/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk7/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk6/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk6/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/shard-glk6/boot.html
   [44]: 

[Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma

[Tejas Upadhyay]

From: Chris Wilson 

Introduce the concept of padding the i915_vma with guard pages before
and aft. The major consequence is that all ordinary uses of i915_vma
must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
directly, as the drm_mm_node will include the guard pages that surround
our object.

The biggest connundrum is how exactly to mix requesting a fixed address
with guard pages, particularly through the existing uABI. The user does
not know about guard pages, so such must be transparent to the user, and
so the execobj.offset must be that of the object itself excluding the
guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
The caveat is that some placements will be impossible with guard pages,
as wrap arounds need to be avoided, and the vma itself will require a
larger node. We must we not report EINVAL but ENOSPC as these are
unavailable locations within the GTT rather than conflicting user
requirements.

In the next patch, we start using guard pages for scanout objects. While
these are limited to GGTT vma, on a few platforms these vma (or at least
an alias of the vma) is shared with userspace, so we may leak the
existence of such guards if we are not careful to ensure that the
execobj.offset is transparent and excludes the guards. (On such platforms
like ivb, without full-ppgtt, userspace has to use relocations so the
presence of more untouchable regions within its GTT such be of no further
issue.)

v2: Include the guard range in the overflow checks and placement
restrictions.

v3: Fix the check on the placement upper bound. The request user offset
is relative to the guard offset (not the node.start) and so we should
not include the initial guard offset again when computing the upper
bound of the node.

Signed-off-by: Chris Wilson 
Cc: Matthew Auld 
Reviewed-by: Matthew Auld 
Signed-off-by: Tejas Upadhyay 
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c  | 12 ++--
 drivers/gpu/drm/i915/i915_vma.c   | 26 +-
 drivers/gpu/drm/i915/i915_vma.h   |  5 +++--
 drivers/gpu/drm/i915/i915_vma_types.h |  3 ++-
 4 files changed, 36 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 07133f0c529e..282ed6dd3ca2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -256,8 +256,12 @@ static void gen8_ggtt_insert_entries(struct 
i915_address_space *vm,
 
gte = (gen8_pte_t __iomem *)ggtt->gsm;
gte += vma->node.start / I915_GTT_PAGE_SIZE;
-   end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
 
+   end = gte + vma->guard / I915_GTT_PAGE_SIZE;
+   while (gte < end)
+   gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+   end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, iter, vma->pages)
gen8_set_pte(gte++, pte_encode | addr);
GEM_BUG_ON(gte > end);
@@ -307,8 +311,12 @@ static void gen6_ggtt_insert_entries(struct 
i915_address_space *vm,
 
gte = (gen6_pte_t __iomem *)ggtt->gsm;
gte += vma->node.start / I915_GTT_PAGE_SIZE;
-   end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
 
+   end = gte + vma->guard / I915_GTT_PAGE_SIZE;
+   while (gte < end)
+   gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+   end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, iter, vma->pages)
iowrite32(vm->pte_encode(addr, level, flags), gte++);
GEM_BUG_ON(gte > end);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 10473ce8a047..080ffa583edf 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -658,7 +658,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, 
unsigned long color)
 static int
 i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
 {
-   unsigned long color;
+   unsigned long color, guard;
u64 start, end;
int ret;
 
@@ -666,7 +666,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 
alignment, u64 flags)
GEM_BUG_ON(drm_mm_node_allocated(>node));
 
size = max(size, vma->size);
-   alignment = max(alignment, vma->display_alignment);
+   alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
if (flags & PIN_MAPPABLE) {
size = max_t(typeof(size), size, vma->fence_size);
alignment = max_t(typeof(alignment),
@@ -677,6 +677,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 
alignment, u64 flags)
GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
GEM_BUG_ON(!is_power_of_2(alignment));
 
+   guard = vma->guard; /* retain guard across rebinds */
+   guard = ALIGN(guard, alignment);
+
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
GEM_BUG_ON(!IS_ALIGNED(start, 

[Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size

[Tejas Upadhyay]

From: Chris Wilson 

We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_node
allocation. That is we will offset the vma->pages so that the first page
is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
All users must then not use i915_vma.node.start directly, but compute
the guard offset, thus all users are converted to use a
i915_vma_offset() wrapper.

The notable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.

Signed-off-by: Chris Wilson 
Reviewed-by: Matthew Auld 
Signed-off-by: Tejas Upadhyay 
---
 drivers/gpu/drm/i915/display/intel_dpt.c  |  4 +--
 drivers/gpu/drm/i915/display/intel_fbdev.c|  6 ++--
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 34 ++-
 drivers/gpu/drm/i915/gem/i915_gem_mman.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c|  4 +--
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |  2 +-
 .../i915/gem/selftests/i915_gem_client_blt.c  | 15 
 .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++
 .../drm/i915/gem/selftests/i915_gem_mman.c|  2 +-
 .../drm/i915/gem/selftests/igt_gem_utils.c|  6 ++--
 drivers/gpu/drm/i915/gt/gen6_ppgtt.c  |  2 +-
 drivers/gpu/drm/i915/gt/gen7_renderclear.c|  2 +-
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  |  8 ++---
 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  5 +--
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |  3 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  5 +--
 drivers/gpu/drm/i915/gt/intel_renderstate.c   |  2 +-
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  2 +-
 drivers/gpu/drm/i915/gt/selftest_engine_cs.c  |  8 ++---
 drivers/gpu/drm/i915/gt/selftest_execlists.c  | 18 +-
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c  | 15 
 drivers/gpu/drm/i915/gt/selftest_lrc.c| 16 -
 .../drm/i915/gt/selftest_ring_submission.c|  2 +-
 drivers/gpu/drm/i915/gt/selftest_rps.c| 12 +++
 .../gpu/drm/i915/gt/selftest_workarounds.c|  8 ++---
 drivers/gpu/drm/i915/i915_cmd_parser.c|  4 +--
 drivers/gpu/drm/i915/i915_debugfs.c   |  2 +-
 drivers/gpu/drm/i915/i915_perf.c  |  2 +-
 drivers/gpu/drm/i915/i915_vma.c   | 21 ++--
 drivers/gpu/drm/i915/i915_vma.h   | 23 +++--
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 ++-
 drivers/gpu/drm/i915/selftests/i915_request.c | 20 +--
 drivers/gpu/drm/i915/selftests/igt_spinner.c  |  8 ++---
 34 files changed, 169 insertions(+), 127 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c 
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 963ca7155b06..1bb99ef4ce2d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -64,7 +64,7 @@ static void dpt_insert_entries(struct i915_address_space *vm,
 * not to allow the user to override access to a read only page.
 */
 
-   i = vma->node.start / I915_GTT_PAGE_SIZE;
+   i = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, sgt_iter, vma->pages)
gen8_set_pte([i++], pte_encode | addr);
 }
@@ -104,7 +104,7 @@ static void dpt_bind_vma(struct i915_address_space *vm,
 
 static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
 {
-   vm->clear_range(vm, vma->node.start, vma->size);
+   vm->clear_range(vm, i915_vma_offset(vma), vma->size);
 }
 
 static void dpt_cleanup(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c 
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..0583dcd538ae 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -261,8 +261,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
 
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
-   (unsigned long)(ggtt->gmadr.start + vma->node.start);
-   info->fix.smem_len = vma->node.size;
+   (unsigned long)(ggtt->gmadr.start + 
i915_ggtt_offset(vma));
+   info->fix.smem_len = vma->size;
}
 
vaddr = i915_vma_pin_iomap(vma);
@@ -273,7 +273,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out_unpin;
}
info->screen_base = vaddr;
-   info->screen_size = vma->node.size;
+   info->screen_size = vma->size;
 
drm_fb_helper_fill_info(info, >helper, sizes);
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 6a0ed537c199..d024b88da608 100644

[Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

[Tejas Upadhyay]

From: Chris Wilson 

VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 168 PTE,
warning that the accesses will wrap around the ends of the GGTT.
Currently, we fill the entire GGTT with scratch pages when using VT-d to
always ensure there are valid entries around every vma, including
scanout. However, writing every PTE is slow as on recent devices we
perform 8MiB of uncached writes, incurring an extra 100ms during resume.

If instead we focus on only putting guard pages around scanout, we can
avoid touching the whole GGTT. To avoid having to introduce extra nodes
around each scanout vma, we adjust the scanout drm_mm_node to be smaller
than the allocated space, and fixup the extra PTE during dma binding.

v2: Move the guard from modifying drm_mm_node.start which is still used
by the drm_mm itself, into an adjustment of node.start at the point of
use.

v3: Pass the requested guard padding from the caller, so we can drop the
VT-d w/a knowledge from the i915_vma allocator.

v4: Bump minimum padding to 168 PTE and cautiously ensure that a full
tile row around the vma is included with the guard.

Signed-off-by: Chris Wilson 
Cc: Ville Syrjälä 
Cc: Matthew Auld 
Cc: Imre Deak 
Reviewed-by: Matthew Auld 
Signed-off-by: Tejas Upadhyay 
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++
 drivers/gpu/drm/i915/gt/intel_ggtt.c   | 25 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h|  1 +
 drivers/gpu/drm/i915/i915_vma.c|  8 +++
 4 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c 
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 26532c07d467..0e014f186807 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -16,6 +16,8 @@
 #include "i915_gem_lmem.h"
 #include "i915_gem_mman.h"
 
+#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
+
 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
 {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
@@ -423,6 +425,17 @@ i915_gem_object_pin_to_display_plane(struct 
drm_i915_gem_object *obj,
if (ret)
return ERR_PTR(ret);
 
+   /* VT-d may overfetch before/after the vma, so pad with scratch */
+   if (intel_scanout_needs_vtd_wa(i915)) {
+   unsigned int guard = VTD_GUARD;
+
+   if (i915_gem_object_is_tiled(obj))
+   guard = max(guard,
+   i915_gem_object_get_tile_row_size(obj));
+
+   flags |= PIN_OFFSET_GUARD | guard;
+   }
+
/*
 * As the user may map the buffer once pinned in the display plane
 * (e.g. libkms for the bootup splash), we have to ensure that we
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 282ed6dd3ca2..4a0f916ab03f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -337,27 +337,6 @@ static void nop_clear_range(struct i915_address_space *vm,
 {
 }
 
-static void gen8_ggtt_clear_range(struct i915_address_space *vm,
- u64 start, u64 length)
-{
-   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-   unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
-   unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
-   const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
-   gen8_pte_t __iomem *gtt_base =
-   (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
-   const int max_entries = ggtt_total_entries(ggtt) - first_entry;
-   int i;
-
-   if (WARN(num_entries > max_entries,
-"First entry = %d; Num entries = %d (max=%d)\n",
-first_entry, num_entries, max_entries))
-   num_entries = max_entries;
-
-   for (i = 0; i < num_entries; i++)
-   gen8_set_pte(_base[i], scratch_pte);
-}
-
 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
 {
/*
@@ -956,8 +935,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.cleanup = gen6_gmch_remove;
ggtt->vm.insert_page = gen8_ggtt_insert_page;
ggtt->vm.clear_range = nop_clear_range;
-   if (intel_scanout_needs_vtd_wa(i915))
-   ggtt->vm.clear_range = gen8_ggtt_clear_range;
 
ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
 
@@ -1105,7 +1082,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
 
ggtt->vm.clear_range = nop_clear_range;
-   if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
+   if (!HAS_FULL_PPGTT(i915))
ggtt->vm.clear_range = gen6_ggtt_clear_range;
ggtt->vm.insert_page = gen6_ggtt_insert_page;

[Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages

[Tejas Upadhyay]

Replace filling the GGTT entirely with scratch pages to avoid invalid
accesses from VT-d overfetch of scanout by only surrounding scanout vma
with guard pages. This eliminates the 100+ms delay in resume where we
have to repopulate the GGTT with scratch.

This should also help in avoiding slow suspend/resume on GEN11/12
platforms. Which will also resolve issues with following reported 
errors : "slow framebuffer consoles issue impacts Linux S3"

Chris Wilson (3):
  drm/i915: Wrap all access to i915_vma.node.start|size
  drm/i915: Introduce guard pages to i915_vma
  drm/i915: Refine VT-d scanout workaround

 drivers/gpu/drm/i915/display/intel_dpt.c  |  4 +-
 drivers/gpu/drm/i915/display/intel_fbdev.c|  6 +-
 drivers/gpu/drm/i915/gem/i915_gem_domain.c| 13 +
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 34 ++--
 drivers/gpu/drm/i915/gem/i915_gem_mman.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c|  4 +-
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |  2 +-
 .../i915/gem/selftests/i915_gem_client_blt.c  | 15 ++---
 .../drm/i915/gem/selftests/i915_gem_context.c | 19 +--
 .../drm/i915/gem/selftests/i915_gem_mman.c|  2 +-
 .../drm/i915/gem/selftests/igt_gem_utils.c|  6 +-
 drivers/gpu/drm/i915/gt/gen6_ppgtt.c  |  2 +-
 drivers/gpu/drm/i915/gt/gen7_renderclear.c|  2 +-
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  |  8 +--
 drivers/gpu/drm/i915/gt/intel_ggtt.c  | 42 +-
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |  3 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  5 +-
 drivers/gpu/drm/i915/gt/intel_renderstate.c   |  2 +-
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  2 +-
 drivers/gpu/drm/i915/gt/selftest_engine_cs.c  |  8 +--
 drivers/gpu/drm/i915/gt/selftest_execlists.c  | 18 +++---
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c  | 15 ++---
 drivers/gpu/drm/i915/gt/selftest_lrc.c| 16 +++---
 .../drm/i915/gt/selftest_ring_submission.c|  2 +-
 drivers/gpu/drm/i915/gt/selftest_rps.c| 12 ++--
 .../gpu/drm/i915/gt/selftest_workarounds.c|  8 +--
 drivers/gpu/drm/i915/i915_cmd_parser.c|  4 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h   |  1 +
 drivers/gpu/drm/i915/i915_perf.c  |  2 +-
 drivers/gpu/drm/i915/i915_vma.c   | 55 ++-
 drivers/gpu/drm/i915/i915_vma.h   | 24 +++-
 drivers/gpu/drm/i915/i915_vma_types.h |  3 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 +++-
 drivers/gpu/drm/i915/selftests/i915_request.c | 20 +++
 drivers/gpu/drm/i915/selftests/igt_spinner.c  |  8 +--
 37 files changed, 226 insertions(+), 159 deletions(-)

-- 
2.31.1

Re: [Intel-gfx] [PATCH 0/1] static analysis failure

[Intel]

Hi,

On 12/2/21 05:38, Pallavi Mishra wrote:

fix for null ptr dereferences

Pallavi Mishra (1):
   static analysis failure


No need for cover letter for a single patch.



  drivers/gpu/drm/i915/gem/i915_gem_ttm.c  | 3 +++
  drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
  2 files changed, 6 insertions(+), 1 deletion(-)

Re: [Intel-gfx] [PATCH 1/1] static analysis failure

[Intel]

On 12/2/21 05:38, Pallavi Mishra wrote:

fix for null ptr dereferences.


Please describe the change as per the patch submission guidelines:

https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes

In particular, describe the *real* problems and the fixes, and not only 
that this silences a
static analysis tool. If the problems were found with such a tool, then 
that can be added as as a side note.





Signed-off-by: Pallavi Mishra 
---
  drivers/gpu/drm/i915/gem/i915_gem_ttm.c  | 3 +++
  drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
  2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 218a9b3037c7..997fe73c205b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -906,6 +906,8 @@ vm_access_ttm(struct vm_area_struct *area, unsigned long 
addr,
struct drm_i915_gem_object *obj =
i915_ttm_to_gem(area->vm_private_data);
  
+	GEM_BUG_ON(!obj);

+
if (i915_gem_object_is_readonly(obj) && write)
return -EACCES;
  
@@ -966,6 +968,7 @@ static const struct drm_i915_gem_object_ops i915_gem_ttm_obj_ops = {

  void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
  {
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+   GEM_BUG_ON(!obj);
  
  	i915_gem_object_release_memory_region(obj);

mutex_destroy(>ttm.get_io_page.lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 80df9f592407..12ba05d44d0f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -369,8 +369,10 @@ void i915_ttm_adjust_gem_after_move(struct 
drm_i915_gem_object *obj)
  int i915_ttm_move_notify(struct ttm_buffer_object *bo)
  {
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+

Stray blank line change.

int ret;
  
+	GEM_BUG_ON(!obj);

ret = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
if (ret)
return ret;
@@ -506,7 +508,7 @@ static void i915_ttm_memcpy_init(struct i915_ttm_memcpy_arg 
*arg,
  
  	dst_reg = i915_ttm_region(bo->bdev, dst_mem->mem_type);

src_reg = i915_ttm_region(bo->bdev, bo->resource->mem_type);
-   GEM_BUG_ON(!dst_reg || !src_reg);
+   GEM_BUG_ON(!dst_reg || !src_reg || !obj);
  
  	arg->dst_iter = !i915_ttm_cpu_maps_iomem(dst_mem) ?

ttm_kmap_iter_tt_init(>_dst_iter.tt, dst_ttm) :


Thanks,

Thomas

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Replace VT-d workaround with guard pages

[Patchwork]

== Series Details ==

Series: Replace VT-d workaround with guard pages
URL   : https://patchwork.freedesktop.org/series/97492/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages

[Tejas Upadhyay]

Replace filling the GGTT entirely with scratch pages to avoid invalid
accesses from VT-d overfetch of scanout by only surrounding scanout vma
with guard pages. This eliminates the 100+ms delay in resume where we
have to repopulate the GGTT with scratch.

This should also help in avoiding slow suspend/resume on GEN11/12
platforms. Which will also resolve issues with following reported 
errors : "slow framebuffer consoles issue impacts Linux S3"

V2: solved checkpatch warning

Chris Wilson (3):
  drm/i915: Wrap all access to i915_vma.node.start|size
  drm/i915: Introduce guard pages to i915_vma
  drm/i915: Refine VT-d scanout workaround

 drivers/gpu/drm/i915/display/intel_dpt.c  |  4 +-
 drivers/gpu/drm/i915/display/intel_fbdev.c|  6 +-
 drivers/gpu/drm/i915/gem/i915_gem_domain.c| 13 +
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 34 ++--
 drivers/gpu/drm/i915/gem/i915_gem_mman.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c|  4 +-
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |  2 +-
 .../i915/gem/selftests/i915_gem_client_blt.c  | 15 ++---
 .../drm/i915/gem/selftests/i915_gem_context.c | 19 +--
 .../drm/i915/gem/selftests/i915_gem_mman.c|  2 +-
 .../drm/i915/gem/selftests/igt_gem_utils.c|  6 +-
 drivers/gpu/drm/i915/gt/gen6_ppgtt.c  |  2 +-
 drivers/gpu/drm/i915/gt/gen7_renderclear.c|  2 +-
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  |  8 +--
 drivers/gpu/drm/i915/gt/intel_ggtt.c  | 42 +-
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |  3 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  5 +-
 drivers/gpu/drm/i915/gt/intel_renderstate.c   |  2 +-
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  2 +-
 drivers/gpu/drm/i915/gt/selftest_engine_cs.c  |  8 +--
 drivers/gpu/drm/i915/gt/selftest_execlists.c  | 18 +++---
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c  | 15 ++---
 drivers/gpu/drm/i915/gt/selftest_lrc.c| 16 +++---
 .../drm/i915/gt/selftest_ring_submission.c|  2 +-
 drivers/gpu/drm/i915/gt/selftest_rps.c| 12 ++--
 .../gpu/drm/i915/gt/selftest_workarounds.c|  8 +--
 drivers/gpu/drm/i915/i915_cmd_parser.c|  4 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h   |  1 +
 drivers/gpu/drm/i915/i915_perf.c  |  2 +-
 drivers/gpu/drm/i915/i915_vma.c   | 55 ++-
 drivers/gpu/drm/i915/i915_vma.h   | 24 +++-
 drivers/gpu/drm/i915/i915_vma_types.h |  3 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 +++-
 drivers/gpu/drm/i915/selftests/i915_request.c | 20 +++
 drivers/gpu/drm/i915/selftests/igt_spinner.c  |  8 +--
 37 files changed, 226 insertions(+), 159 deletions(-)

-- 
2.31.1

[Intel-gfx] [PATCH V2 1/3] drm/i915: Wrap all access to i915_vma.node.start|size

[Tejas Upadhyay]

From: Chris Wilson 

We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_node
allocation. That is we will offset the vma->pages so that the first page
is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
All users must then not use i915_vma.node.start directly, but compute
the guard offset, thus all users are converted to use a
i915_vma_offset() wrapper.

The notable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.

Signed-off-by: Chris Wilson 
Reviewed-by: Matthew Auld 
Signed-off-by: Tejas Upadhyay 
---
 drivers/gpu/drm/i915/display/intel_dpt.c  |  4 +--
 drivers/gpu/drm/i915/display/intel_fbdev.c|  6 ++--
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 34 ++-
 drivers/gpu/drm/i915/gem/i915_gem_mman.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c|  4 +--
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |  2 +-
 .../i915/gem/selftests/i915_gem_client_blt.c  | 15 
 .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++
 .../drm/i915/gem/selftests/i915_gem_mman.c|  2 +-
 .../drm/i915/gem/selftests/igt_gem_utils.c|  6 ++--
 drivers/gpu/drm/i915/gt/gen6_ppgtt.c  |  2 +-
 drivers/gpu/drm/i915/gt/gen7_renderclear.c|  2 +-
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  |  8 ++---
 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  5 +--
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |  3 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  5 +--
 drivers/gpu/drm/i915/gt/intel_renderstate.c   |  2 +-
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  2 +-
 drivers/gpu/drm/i915/gt/selftest_engine_cs.c  |  8 ++---
 drivers/gpu/drm/i915/gt/selftest_execlists.c  | 18 +-
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c  | 15 
 drivers/gpu/drm/i915/gt/selftest_lrc.c| 16 -
 .../drm/i915/gt/selftest_ring_submission.c|  2 +-
 drivers/gpu/drm/i915/gt/selftest_rps.c| 12 +++
 .../gpu/drm/i915/gt/selftest_workarounds.c|  8 ++---
 drivers/gpu/drm/i915/i915_cmd_parser.c|  4 +--
 drivers/gpu/drm/i915/i915_debugfs.c   |  2 +-
 drivers/gpu/drm/i915/i915_perf.c  |  2 +-
 drivers/gpu/drm/i915/i915_vma.c   | 21 ++--
 drivers/gpu/drm/i915/i915_vma.h   | 23 +++--
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 ++-
 drivers/gpu/drm/i915/selftests/i915_request.c | 20 +--
 drivers/gpu/drm/i915/selftests/igt_spinner.c  |  8 ++---
 34 files changed, 169 insertions(+), 127 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c 
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 963ca7155b06..1bb99ef4ce2d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -64,7 +64,7 @@ static void dpt_insert_entries(struct i915_address_space *vm,
 * not to allow the user to override access to a read only page.
 */
 
-   i = vma->node.start / I915_GTT_PAGE_SIZE;
+   i = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, sgt_iter, vma->pages)
gen8_set_pte([i++], pte_encode | addr);
 }
@@ -104,7 +104,7 @@ static void dpt_bind_vma(struct i915_address_space *vm,
 
 static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
 {
-   vm->clear_range(vm, vma->node.start, vma->size);
+   vm->clear_range(vm, i915_vma_offset(vma), vma->size);
 }
 
 static void dpt_cleanup(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c 
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..0583dcd538ae 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -261,8 +261,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
 
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
-   (unsigned long)(ggtt->gmadr.start + vma->node.start);
-   info->fix.smem_len = vma->node.size;
+   (unsigned long)(ggtt->gmadr.start + 
i915_ggtt_offset(vma));
+   info->fix.smem_len = vma->size;
}
 
vaddr = i915_vma_pin_iomap(vma);
@@ -273,7 +273,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out_unpin;
}
info->screen_base = vaddr;
-   info->screen_size = vma->node.size;
+   info->screen_size = vma->size;
 
drm_fb_helper_fill_info(info, >helper, sizes);
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 6a0ed537c199..d024b88da608 100644

[Intel-gfx] [PATCH V2 2/3] drm/i915: Introduce guard pages to i915_vma

[Tejas Upadhyay]

From: Chris Wilson 

Introduce the concept of padding the i915_vma with guard pages before
and aft. The major consequence is that all ordinary uses of i915_vma
must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
directly, as the drm_mm_node will include the guard pages that surround
our object.

The biggest connundrum is how exactly to mix requesting a fixed address
with guard pages, particularly through the existing uABI. The user does
not know about guard pages, so such must be transparent to the user, and
so the execobj.offset must be that of the object itself excluding the
guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
The caveat is that some placements will be impossible with guard pages,
as wrap arounds need to be avoided, and the vma itself will require a
larger node. We must we not report EINVAL but ENOSPC as these are
unavailable locations within the GTT rather than conflicting user
requirements.

In the next patch, we start using guard pages for scanout objects. While
these are limited to GGTT vma, on a few platforms these vma (or at least
an alias of the vma) is shared with userspace, so we may leak the
existence of such guards if we are not careful to ensure that the
execobj.offset is transparent and excludes the guards. (On such platforms
like ivb, without full-ppgtt, userspace has to use relocations so the
presence of more untouchable regions within its GTT such be of no further
issue.)

v2: Include the guard range in the overflow checks and placement
restrictions.

v3: Fix the check on the placement upper bound. The request user offset
is relative to the guard offset (not the node.start) and so we should
not include the initial guard offset again when computing the upper
bound of the node.

Signed-off-by: Chris Wilson 
Cc: Matthew Auld 
Reviewed-by: Matthew Auld 
Signed-off-by: Tejas Upadhyay 
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c  | 12 ++--
 drivers/gpu/drm/i915/i915_vma.c   | 26 +-
 drivers/gpu/drm/i915/i915_vma.h   |  5 +++--
 drivers/gpu/drm/i915/i915_vma_types.h |  3 ++-
 4 files changed, 36 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 07133f0c529e..282ed6dd3ca2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -256,8 +256,12 @@ static void gen8_ggtt_insert_entries(struct 
i915_address_space *vm,
 
gte = (gen8_pte_t __iomem *)ggtt->gsm;
gte += vma->node.start / I915_GTT_PAGE_SIZE;
-   end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
 
+   end = gte + vma->guard / I915_GTT_PAGE_SIZE;
+   while (gte < end)
+   gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+   end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, iter, vma->pages)
gen8_set_pte(gte++, pte_encode | addr);
GEM_BUG_ON(gte > end);
@@ -307,8 +311,12 @@ static void gen6_ggtt_insert_entries(struct 
i915_address_space *vm,
 
gte = (gen6_pte_t __iomem *)ggtt->gsm;
gte += vma->node.start / I915_GTT_PAGE_SIZE;
-   end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
 
+   end = gte + vma->guard / I915_GTT_PAGE_SIZE;
+   while (gte < end)
+   gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+   end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, iter, vma->pages)
iowrite32(vm->pte_encode(addr, level, flags), gte++);
GEM_BUG_ON(gte > end);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 10473ce8a047..080ffa583edf 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -658,7 +658,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, 
unsigned long color)
 static int
 i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
 {
-   unsigned long color;
+   unsigned long color, guard;
u64 start, end;
int ret;
 
@@ -666,7 +666,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 
alignment, u64 flags)
GEM_BUG_ON(drm_mm_node_allocated(>node));
 
size = max(size, vma->size);
-   alignment = max(alignment, vma->display_alignment);
+   alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
if (flags & PIN_MAPPABLE) {
size = max_t(typeof(size), size, vma->fence_size);
alignment = max_t(typeof(alignment),
@@ -677,6 +677,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 
alignment, u64 flags)
GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
GEM_BUG_ON(!is_power_of_2(alignment));
 
+   guard = vma->guard; /* retain guard across rebinds */
+   guard = ALIGN(guard, alignment);
+
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
GEM_BUG_ON(!IS_ALIGNED(start, 

[Intel-gfx] [PATCH V2 3/3] drm/i915: Refine VT-d scanout workaround

[Tejas Upadhyay]

From: Chris Wilson 

VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 168 PTE,
warning that the accesses will wrap around the ends of the GGTT.
Currently, we fill the entire GGTT with scratch pages when using VT-d to
always ensure there are valid entries around every vma, including
scanout. However, writing every PTE is slow as on recent devices we
perform 8MiB of uncached writes, incurring an extra 100ms during resume.

If instead we focus on only putting guard pages around scanout, we can
avoid touching the whole GGTT. To avoid having to introduce extra nodes
around each scanout vma, we adjust the scanout drm_mm_node to be smaller
than the allocated space, and fixup the extra PTE during dma binding.

v2: Move the guard from modifying drm_mm_node.start which is still used
by the drm_mm itself, into an adjustment of node.start at the point of
use.

v3: Pass the requested guard padding from the caller, so we can drop the
VT-d w/a knowledge from the i915_vma allocator.

v4: Bump minimum padding to 168 PTE and cautiously ensure that a full
tile row around the vma is included with the guard.

Signed-off-by: Chris Wilson 
Cc: Ville Syrjälä 
Cc: Matthew Auld 
Cc: Imre Deak 
Reviewed-by: Matthew Auld 
Signed-off-by: Tejas Upadhyay 
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++
 drivers/gpu/drm/i915/gt/intel_ggtt.c   | 25 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h|  1 +
 drivers/gpu/drm/i915/i915_vma.c|  8 +++
 4 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c 
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 26532c07d467..03876af45c8b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -16,6 +16,8 @@
 #include "i915_gem_lmem.h"
 #include "i915_gem_mman.h"
 
+#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
+
 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
 {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
@@ -423,6 +425,17 @@ i915_gem_object_pin_to_display_plane(struct 
drm_i915_gem_object *obj,
if (ret)
return ERR_PTR(ret);
 
+   /* VT-d may overfetch before/after the vma, so pad with scratch */
+   if (intel_scanout_needs_vtd_wa(i915)) {
+   unsigned int guard = VTD_GUARD;
+
+   if (i915_gem_object_is_tiled(obj))
+   guard = max(guard,
+   i915_gem_object_get_tile_row_size(obj));
+
+   flags |= PIN_OFFSET_GUARD | guard;
+   }
+
/*
 * As the user may map the buffer once pinned in the display plane
 * (e.g. libkms for the bootup splash), we have to ensure that we
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 282ed6dd3ca2..4a0f916ab03f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -337,27 +337,6 @@ static void nop_clear_range(struct i915_address_space *vm,
 {
 }
 
-static void gen8_ggtt_clear_range(struct i915_address_space *vm,
- u64 start, u64 length)
-{
-   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-   unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
-   unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
-   const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
-   gen8_pte_t __iomem *gtt_base =
-   (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
-   const int max_entries = ggtt_total_entries(ggtt) - first_entry;
-   int i;
-
-   if (WARN(num_entries > max_entries,
-"First entry = %d; Num entries = %d (max=%d)\n",
-first_entry, num_entries, max_entries))
-   num_entries = max_entries;
-
-   for (i = 0; i < num_entries; i++)
-   gen8_set_pte(_base[i], scratch_pte);
-}
-
 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
 {
/*
@@ -956,8 +935,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.cleanup = gen6_gmch_remove;
ggtt->vm.insert_page = gen8_ggtt_insert_page;
ggtt->vm.clear_range = nop_clear_range;
-   if (intel_scanout_needs_vtd_wa(i915))
-   ggtt->vm.clear_range = gen8_ggtt_clear_range;
 
ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
 
@@ -1105,7 +1082,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
 
ggtt->vm.clear_range = nop_clear_range;
-   if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
+   if (!HAS_FULL_PPGTT(i915))
ggtt->vm.clear_range = gen6_ggtt_clear_range;
ggtt->vm.insert_page = gen6_ggtt_insert_page;

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Replace VT-d workaround with guard pages (rev2)

[Patchwork]

== Series Details ==

Series: Replace VT-d workaround with guard pages (rev2)
URL   : https://patchwork.freedesktop.org/series/97492/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Replace VT-d workaround with guard pages

[Patchwork]

== Series Details ==

Series: Replace VT-d workaround with guard pages
URL   : https://patchwork.freedesktop.org/series/97492/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9f65b4ead78d drm/i915: Wrap all access to i915_vma.node.start|size
aab382a940c6 drm/i915: Introduce guard pages to i915_vma
3ab5c1e98b07 drm/i915: Refine VT-d scanout workaround
-:63: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#63: FILE: drivers/gpu/drm/i915/gem/i915_gem_domain.c:434:
+   guard = max(guard,
+   i915_gem_object_get_tile_row_size(obj));

total: 0 errors, 0 warnings, 1 checks, 101 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for Replace VT-d workaround with guard pages (rev2)

[Patchwork]

== Series Details ==

Series: Replace VT-d workaround with guard pages (rev2)
URL   : https://patchwork.freedesktop.org/series/97492/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10953 -> Patchwork_21727


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/index.html

Participating hosts (38 -> 32)
--

  Additional (1): fi-bdw-gvtdvm 
  Missing(7): fi-tgl-dsi bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 
bat-jsl-2 bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_21727 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@write:
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][1] ([fdo#109271]) +5 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-bdw-gvtdvm/igt@fb...@write.html

  * igt@gem_exec_suspend@basic-s0:
- fi-bdw-gvtdvm:  NOTRUN -> [INCOMPLETE][2] ([i915#146] / [i915#2539])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s0.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live:
- fi-skl-6600u:   NOTRUN -> [INCOMPLETE][5] ([i915#198])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@i915_selft...@live.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u:   NOTRUN -> [SKIP][7] ([fdo#109271]) +3 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1:
- fi-blb-e6850:   [PASS][8] -> [FAIL][9] ([i915#2122])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-blb-e6850/igt@kms_flip@basic-flip-vs-wf_vbl...@a-vga1.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-blb-e6850/igt@kms_flip@basic-flip-vs-wf_vbl...@a-vga1.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u:   NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#533])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4:  [FAIL][11] ([i915#1888]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html

  * igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u:   [INCOMPLETE][13] ([i915#4547]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [DMESG-WARN][15] ([i915#4269]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-

  * Linux: CI_DRM_10953 -> Patchwork_21727

  CI-20190529: 20190529
  

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix error pointer dereference in i915_gem_do_execbuffer() (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix error pointer dereference in i915_gem_do_execbuffer() 
(rev4)
URL   : https://patchwork.freedesktop.org/series/96969/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10953_full -> Patchwork_21725_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_21725_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([PASS][26], [FAIL][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50]) ([i915#4386])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl1/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl1/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl1/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl2/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl2/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl8/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl8/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl8/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl6/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl6/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl1/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl1/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl2/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl2/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl2/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl3/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl3/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl3/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl4/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl4/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl4/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl6/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl6/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl6/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl6/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/shard-apl7/boot.html
   [44]: 

Re: [Intel-gfx] [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width

[Srinivas, Vidya]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Thursday, December 2, 2021 4:26 PM
> To: Srinivas, Vidya 
> Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> 
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
> 
> On Thu, Dec 02, 2021 at 03:25:34AM +, Srinivas, Vidya wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä 
> > > Sent: Wednesday, December 1, 2021 8:33 PM
> > > To: Srinivas, Vidya 
> > > Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> > > 
> > > Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in
> > > max_width
> > >
> > > On Wed, Dec 01, 2021 at 09:17:27AM +0530, Vidya Srinivas wrote:
> > > > PLANE_CUS_CTL has a restriction of 4096 width even though
> > > > PLANE_SIZE and scaler size registers supports max 5120.
> > > > Take care of this restriction in max_width.
> > > >
> > > > Without this patch, when 5k content is sent on HDR plane with NV12
> > > > content, FIFO underrun is seen and screen blanks out.
> > > >
> > > > v2: Addressed review comments from Ville. Added separate functions
> > > > for max_width - for HDR and SDR
> > > >
> > > > v3: Addressed review comments from Ville. Changed names of HDR and
> > > SDR
> > > > max_width functions to icl_hdr_plane_max_width and
> > > > icl_sdr_plane_max_width
> > > >
> > > > v4: Fixed paranthesis alignment. No code change
> > > >
> > > > Reviewed-by: Ville Syrjälä 
> > > > Signed-off-by: Vidya Srinivas 
> > > > Signed-off-by: Yashashvi Shantam 
> > >
> > > Hmm. What's this extra sob doing here?
> >
> > Hello Ville, sincere apologies. When I run checkpatch.pl I see no warnings
> on my host.
> > However patchwork keeps reporting paranthesis alignment warning.
> > I tried to push it multiple times after running checkpatch.pl on my host.
> Really sorry about that.
> 
> I was asking about the extra "signed-off-by" (sob).

Hello Ville, I am really sorry about that. Should I keep single signed-off-by 
and push the patch
again? Kindly let me know. Thank you.

Regards
Vidya

> 
> --
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width

[Srinivas, Vidya]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Thursday, December 2, 2021 4:43 PM
> To: Srinivas, Vidya 
> Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> 
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
> 
> On Thu, Dec 02, 2021 at 11:10:37AM +, Srinivas, Vidya wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä 
> > > Sent: Thursday, December 2, 2021 4:26 PM
> > > To: Srinivas, Vidya 
> > > Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> > > 
> > > Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in
> > > max_width
> > >
> > > On Thu, Dec 02, 2021 at 03:25:34AM +, Srinivas, Vidya wrote:
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Ville Syrjälä 
> > > > > Sent: Wednesday, December 1, 2021 8:33 PM
> > > > > To: Srinivas, Vidya 
> > > > > Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> > > > > 
> > > > > Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in
> > > > > max_width
> > > > >
> > > > > On Wed, Dec 01, 2021 at 09:17:27AM +0530, Vidya Srinivas wrote:
> > > > > > PLANE_CUS_CTL has a restriction of 4096 width even though
> > > > > > PLANE_SIZE and scaler size registers supports max 5120.
> > > > > > Take care of this restriction in max_width.
> > > > > >
> > > > > > Without this patch, when 5k content is sent on HDR plane with
> > > > > > NV12 content, FIFO underrun is seen and screen blanks out.
> > > > > >
> > > > > > v2: Addressed review comments from Ville. Added separate
> > > > > > functions for max_width - for HDR and SDR
> > > > > >
> > > > > > v3: Addressed review comments from Ville. Changed names of HDR
> > > > > > and
> > > > > SDR
> > > > > > max_width functions to icl_hdr_plane_max_width and
> > > > > > icl_sdr_plane_max_width
> > > > > >
> > > > > > v4: Fixed paranthesis alignment. No code change
> > > > > >
> > > > > > Reviewed-by: Ville Syrjälä 
> > > > > > Signed-off-by: Vidya Srinivas 
> > > > > > Signed-off-by: Yashashvi Shantam 
> > > > >
> > > > > Hmm. What's this extra sob doing here?
> > > >
> > > > Hello Ville, sincere apologies. When I run checkpatch.pl I see no
> > > > warnings
> > > on my host.
> > > > However patchwork keeps reporting paranthesis alignment warning.
> > > > I tried to push it multiple times after running checkpatch.pl on my 
> > > > host.
> > > Really sorry about that.
> > >
> > > I was asking about the extra "signed-off-by" (sob).
> >
> > Hello Ville, I am really sorry about that. Should I keep single
> > signed-off-by and push the patch again? Kindly let me know. Thank you.
> 
> Yeah, please resend with proper signed-off-by.

Hello Ville, I have kept a single signed-off-by and pushed
https://patchwork.freedesktop.org/patch/465010/?series=97053=9
Apologies for bothering you. Thank you very much. Kindly have a check.

Regards
Vidya


> 
> --
> Ville Syrjälä
> Intel

[Intel-gfx] ✓ Fi.CI.IGT: success for Replace VT-d workaround with guard pages (rev2)

[Patchwork]

== Series Details ==

Series: Replace VT-d workaround with guard pages (rev2)
URL   : https://patchwork.freedesktop.org/series/97492/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10953_full -> Patchwork_21727_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_21727_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [FAIL][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50]) ([i915#4386])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl1/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl1/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl1/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl2/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl2/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl8/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl8/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl8/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl6/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl6/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl7/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl7/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl7/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl6/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl6/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl6/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl3/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl3/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl3/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl3/boot.html
   [44]: 

Re: [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits

[Ville Syrjälä]

On Wed, Dec 01, 2021 at 05:14:39PM +, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Rename the YUV byte order bits to be a bit more consistent.
> 
> Why rename bits not used? Would be better already nuke it.
> Anyways up to you.

We'll need the masks for the REG_FIELD_PREP() stuff later.

> 
> Reviewed-by: José Roberto de Souza 
> 
> > 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/display/skl_universal_plane.c |  8 
> >  drivers/gpu/drm/i915/i915_reg.h| 14 +++---
> >  2 files changed, 11 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 845b99844ec6..9ff24a0e79b4 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -672,13 +672,13 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> > case DRM_FORMAT_XYUV:
> > return PLANE_CTL_FORMAT_XYUV;
> > case DRM_FORMAT_YUYV:
> > -   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> > +   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
> > case DRM_FORMAT_YVYU:
> > -   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
> > +   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
> > case DRM_FORMAT_UYVY:
> > -   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
> > +   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
> > case DRM_FORMAT_VYUY:
> > -   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> > +   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
> > case DRM_FORMAT_NV12:
> > return PLANE_CTL_FORMAT_NV12;
> > case DRM_FORMAT_P010:
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 3c0471f20e53..02d8db03c0bf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6966,7 +6966,7 @@ enum {
> >  #define   DVS_SOURCE_KEY   (1 << 22)
> >  #define   DVS_RGB_ORDER_XBGR   (1 << 20)
> >  #define   DVS_YUV_FORMAT_BT709 (1 << 18)
> > -#define   DVS_YUV_BYTE_ORDER_MASK (3 << 16)
> > +#define   DVS_YUV_ORDER_MASK   (3 << 16)
> >  #define   DVS_YUV_ORDER_YUYV   (0 << 16)
> >  #define   DVS_YUV_ORDER_UYVY   (1 << 16)
> >  #define   DVS_YUV_ORDER_YVYU   (2 << 16)
> > @@ -7045,7 +7045,7 @@ enum {
> >  #define   SPRITE_RGB_ORDER_RGBX(1 << 20) /* only for 888 and 
> > 161616 */
> >  #define   SPRITE_YUV_TO_RGB_CSC_DISABLE(1 << 19)
> >  #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709   (1 << 18) /* 0 is BT601 
> > */
> > -#define   SPRITE_YUV_BYTE_ORDER_MASK   (3 << 16)
> > +#define   SPRITE_YUV_ORDER_MASK(3 << 16)
> >  #define   SPRITE_YUV_ORDER_YUYV(0 << 16)
> >  #define   SPRITE_YUV_ORDER_UYVY(1 << 16)
> >  #define   SPRITE_YUV_ORDER_YVYU(2 << 16)
> > @@ -7130,7 +7130,7 @@ enum {
> >  #define   SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
> >  #define   SP_SOURCE_KEY(1 << 22)
> >  #define   SP_YUV_FORMAT_BT709  (1 << 18)
> > -#define   SP_YUV_BYTE_ORDER_MASK   (3 << 16)
> > +#define   SP_YUV_ORDER_MASK(3 << 16)
> >  #define   SP_YUV_ORDER_YUYV(0 << 16)
> >  #define   SP_YUV_ORDER_UYVY(1 << 16)
> >  #define   SP_YUV_ORDER_YVYU(2 << 16)
> > @@ -7271,10 +7271,10 @@ enum {
> >  #define   PLANE_CTL_YUV420_Y_PLANE (1 << 19)
> >  #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709(1 << 18)
> >  #define   PLANE_CTL_YUV422_ORDER_MASK  (0x3 << 16)
> > -#define   PLANE_CTL_YUV422_YUYV(0 << 16)
> > -#define   PLANE_CTL_YUV422_UYVY(1 << 16)
> > -#define   PLANE_CTL_YUV422_YVYU(2 << 16)
> > -#define   PLANE_CTL_YUV422_VYUY(3 << 16)
> > +#define   PLANE_CTL_YUV422_ORDER_YUYV  (0 << 16)
> > +#define   PLANE_CTL_YUV422_ORDER_UYVY  (1 << 16)
> > +#define   PLANE_CTL_YUV422_ORDER_YVYU  (2 << 16)
> > +#define   PLANE_CTL_YUV422_ORDER_VYUY  (3 << 16)
> >  #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15)
> >  #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
> >  #define   PLANE_CTL_CLEAR_COLOR_DISABLE(1 << 13) /* TGL+ */
> 

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width

[Ville Syrjälä]

On Thu, Dec 02, 2021 at 11:10:37AM +, Srinivas, Vidya wrote:
> 
> 
> > -Original Message-
> > From: Ville Syrjälä 
> > Sent: Thursday, December 2, 2021 4:26 PM
> > To: Srinivas, Vidya 
> > Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> > 
> > Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
> > 
> > On Thu, Dec 02, 2021 at 03:25:34AM +, Srinivas, Vidya wrote:
> > >
> > >
> > > > -Original Message-
> > > > From: Ville Syrjälä 
> > > > Sent: Wednesday, December 1, 2021 8:33 PM
> > > > To: Srinivas, Vidya 
> > > > Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> > > > 
> > > > Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in
> > > > max_width
> > > >
> > > > On Wed, Dec 01, 2021 at 09:17:27AM +0530, Vidya Srinivas wrote:
> > > > > PLANE_CUS_CTL has a restriction of 4096 width even though
> > > > > PLANE_SIZE and scaler size registers supports max 5120.
> > > > > Take care of this restriction in max_width.
> > > > >
> > > > > Without this patch, when 5k content is sent on HDR plane with NV12
> > > > > content, FIFO underrun is seen and screen blanks out.
> > > > >
> > > > > v2: Addressed review comments from Ville. Added separate functions
> > > > > for max_width - for HDR and SDR
> > > > >
> > > > > v3: Addressed review comments from Ville. Changed names of HDR and
> > > > SDR
> > > > > max_width functions to icl_hdr_plane_max_width and
> > > > > icl_sdr_plane_max_width
> > > > >
> > > > > v4: Fixed paranthesis alignment. No code change
> > > > >
> > > > > Reviewed-by: Ville Syrjälä 
> > > > > Signed-off-by: Vidya Srinivas 
> > > > > Signed-off-by: Yashashvi Shantam 
> > > >
> > > > Hmm. What's this extra sob doing here?
> > >
> > > Hello Ville, sincere apologies. When I run checkpatch.pl I see no warnings
> > on my host.
> > > However patchwork keeps reporting paranthesis alignment warning.
> > > I tried to push it multiple times after running checkpatch.pl on my host.
> > Really sorry about that.
> > 
> > I was asking about the extra "signed-off-by" (sob).
> 
> Hello Ville, I am really sorry about that. Should I keep single signed-off-by 
> and push the patch
> again? Kindly let me know. Thank you.

Yeah, please resend with proper signed-off-by.

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH] drm/i915: Fix possible null ptr dereferences

[Pallavi Mishra]

add null ptr checks to prevent crash/exceptions.

Signed-off-by: Pallavi Mishra 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c  | 3 +++
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 3 ++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 218a9b3037c7..997fe73c205b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -906,6 +906,8 @@ vm_access_ttm(struct vm_area_struct *area, unsigned long 
addr,
struct drm_i915_gem_object *obj =
i915_ttm_to_gem(area->vm_private_data);
 
+   GEM_BUG_ON(!obj);
+
if (i915_gem_object_is_readonly(obj) && write)
return -EACCES;
 
@@ -966,6 +968,7 @@ static const struct drm_i915_gem_object_ops 
i915_gem_ttm_obj_ops = {
 void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
 {
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+   GEM_BUG_ON(!obj);
 
i915_gem_object_release_memory_region(obj);
mutex_destroy(>ttm.get_io_page.lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 80df9f592407..2b684903a9f5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -371,6 +371,7 @@ int i915_ttm_move_notify(struct ttm_buffer_object *bo)
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
int ret;
 
+   GEM_BUG_ON(!obj);
ret = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
if (ret)
return ret;
@@ -506,7 +507,7 @@ static void i915_ttm_memcpy_init(struct i915_ttm_memcpy_arg 
*arg,
 
dst_reg = i915_ttm_region(bo->bdev, dst_mem->mem_type);
src_reg = i915_ttm_region(bo->bdev, bo->resource->mem_type);
-   GEM_BUG_ON(!dst_reg || !src_reg);
+   GEM_BUG_ON(!dst_reg || !src_reg || !obj);
 
arg->dst_iter = !i915_ttm_cpu_maps_iomem(dst_mem) ?
ttm_kmap_iter_tt_init(>_dst_iter.tt, dst_ttm) :
-- 
2.25.1

Re: [Intel-gfx] [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width

[Ville Syrjälä]

On Thu, Dec 02, 2021 at 03:25:34AM +, Srinivas, Vidya wrote:
> 
> 
> > -Original Message-
> > From: Ville Syrjälä 
> > Sent: Wednesday, December 1, 2021 8:33 PM
> > To: Srinivas, Vidya 
> > Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> > 
> > Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
> > 
> > On Wed, Dec 01, 2021 at 09:17:27AM +0530, Vidya Srinivas wrote:
> > > PLANE_CUS_CTL has a restriction of 4096 width even though PLANE_SIZE
> > > and scaler size registers supports max 5120.
> > > Take care of this restriction in max_width.
> > >
> > > Without this patch, when 5k content is sent on HDR plane with NV12
> > > content, FIFO underrun is seen and screen blanks out.
> > >
> > > v2: Addressed review comments from Ville. Added separate functions for
> > > max_width - for HDR and SDR
> > >
> > > v3: Addressed review comments from Ville. Changed names of HDR and
> > SDR
> > > max_width functions to icl_hdr_plane_max_width and
> > > icl_sdr_plane_max_width
> > >
> > > v4: Fixed paranthesis alignment. No code change
> > >
> > > Reviewed-by: Ville Syrjälä 
> > > Signed-off-by: Vidya Srinivas 
> > > Signed-off-by: Yashashvi Shantam 
> > 
> > Hmm. What's this extra sob doing here?
> 
> Hello Ville, sincere apologies. When I run checkpatch.pl I see no warnings on 
> my host.
> However patchwork keeps reporting paranthesis alignment warning.
> I tried to push it multiple times after running checkpatch.pl on my host. 
> Really sorry about that.

I was asking about the extra "signed-off-by" (sob).

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width

[Vidya Srinivas]

PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.

Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.

v2: Addressed review comments from Ville. Added separate
functions for max_width - for HDR and SDR

v3: Addressed review comments from Ville. Changed names of
HDR and SDR max_width functions to icl_hdr_plane_max_width
and icl_sdr_plane_max_width

v4: Fixed paranthesis alignment. No code change

Reviewed-by: Ville Syrjälä 
Signed-off-by: Vidya Srinivas 
---
 .../drm/i915/display/skl_universal_plane.c| 21 +++
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 28890876bdeb..e717eb58b105 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -420,9 +420,19 @@ static int icl_plane_min_width(const struct 
drm_framebuffer *fb,
}
 }
 
-static int icl_plane_max_width(const struct drm_framebuffer *fb,
-  int color_plane,
-  unsigned int rotation)
+static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
+   int color_plane,
+   unsigned int rotation)
+{
+   if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
+   return 4096;
+   else
+   return 5120;
+}
+
+static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
+   int color_plane,
+   unsigned int rotation)
 {
return 5120;
 }
@@ -2108,7 +2118,10 @@ skl_universal_plane_create(struct drm_i915_private 
*dev_priv,
 
if (DISPLAY_VER(dev_priv) >= 11) {
plane->min_width = icl_plane_min_width;
-   plane->max_width = icl_plane_max_width;
+   if (icl_is_hdr_plane(dev_priv, plane_id))
+   plane->max_width = icl_hdr_plane_max_width;
+   else
+   plane->max_width = icl_sdr_plane_max_width;
plane->max_height = icl_plane_max_height;
plane->min_cdclk = icl_plane_min_cdclk;
} else if (DISPLAY_VER(dev_priv) >= 10) {
-- 
2.33.0

Re: [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff

[Ville Syrjälä]

On Wed, Dec 01, 2021 at 05:18:54PM +, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Replace the "sizes are 0 based" stuff with just straight
> > up -1 where needed. Less confusing all around.
> > 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/display/intel_sprite.c   | 26 ---
> >  .../drm/i915/display/skl_universal_plane.c|  6 +
> >  2 files changed, 6 insertions(+), 26 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 1b99a9501a45..2067a7bca4a8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -431,10 +431,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> > u32 crtc_h = drm_rect_height(_state->uapi.dst);
> > unsigned long irqflags;
> >  
> > -   /* Sizes are 0 based */
> 
> In my opinion at least this comment should stay, helps understand why the -1. 

It's just normal practice for almost all such registers.
We don't have similar comments elsewhere either. Also if 
the code already says "foo-1" then I don't see what extra
the comment gets you.

> 
> > -   crtc_w--;
> > -   crtc_h--;
> > -
> > spin_lock_irqsave(_priv->uncore.lock, irqflags);
> >  
> > intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
> > @@ -442,7 +438,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
> >   (crtc_y << 16) | crtc_x);
> > intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
> > - (crtc_h << 16) | crtc_w);
> > + ((crtc_h - 1) << 16) | (crtc_w - 1));
> >  
> > spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> >  }
> > @@ -866,21 +862,15 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
> > u32 sprscale = 0;
> > unsigned long irqflags;
> >  
> > -   /* Sizes are 0 based */
> > -   src_w--;
> > -   src_h--;
> > -   crtc_w--;
> > -   crtc_h--;
> > -
> > if (crtc_w != src_w || crtc_h != src_h)
> > -   sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
> > +   sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 
> > 1);
> >  
> > spin_lock_irqsave(_priv->uncore.lock, irqflags);
> >  
> > intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
> >   plane_state->view.color_plane[0].mapping_stride);
> > intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> > -   intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> > +   intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) | 
> > (crtc_w - 1));
> > if (IS_IVYBRIDGE(dev_priv))
> > intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
> >  
> > @@ -1208,21 +1198,15 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
> > u32 dvsscale = 0;
> > unsigned long irqflags;
> >  
> > -   /* Sizes are 0 based */
> > -   src_w--;
> > -   src_h--;
> > -   crtc_w--;
> > -   crtc_h--;
> > -
> > if (crtc_w != src_w || crtc_h != src_h)
> > -   dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
> > +   dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
> >  
> > spin_lock_irqsave(_priv->uncore.lock, irqflags);
> >  
> > intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
> >   plane_state->view.color_plane[0].mapping_stride);
> > intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
> > -   intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
> > +   intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) | 
> > (crtc_w - 1));
> > intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
> >  
> > spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 9ff24a0e79b4..09948922016b 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -1022,10 +1022,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > u32 src_h = drm_rect_height(_state->uapi.src) >> 16;
> > unsigned long irqflags;
> >  
> > -   /* Sizes are 0 based */
> > -   src_w--;
> > -   src_h--;
> > -
> > /* The scaler will handle the output position */
> > if (plane_state->scaler_id >= 0) {
> > crtc_x = 0;
> > @@ -1045,7 +1041,7 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> >   (crtc_y << 16) | crtc_x);
> > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> > - (src_h << 16) | src_w);
> > + ((src_h - 1) << 16) | (src_w - 1));
> >  
> > if 

Re: [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal plane bits

[Ville Syrjälä]

On Wed, Dec 01, 2021 at 05:26:50PM +, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Polish the skl+ universal plane register defines by
> > using REG_BIT() & co.
> > 
> > The defines are also currently spread around in some
> > semi-random fashion. Collect them up into one place.
> > 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  .../drm/i915/display/skl_universal_plane.c|  36 ++--
> >  drivers/gpu/drm/i915/gvt/reg.h|   1 -
> >  drivers/gpu/drm/i915/i915_reg.h   | 197 ++
> >  drivers/gpu/drm/i915/intel_pm.c   |  12 +-
> >  4 files changed, 135 insertions(+), 111 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 984bb35ecf06..79998eb67280 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -1037,11 +1037,12 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > if (plane_state->force_black)
> > icl_plane_csc_load_black(plane);
> >  
> > -   intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
> > +   intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
> > + PLANE_STRIDE_(stride));
> > intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> > - (crtc_y << 16) | crtc_x);
> > + PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
> > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> > - ((src_h - 1) << 16) | (src_w - 1));
> > + PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
> >  
> > if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> > intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
> > @@ -1100,7 +1101,7 @@ skl_program_plane_arm(struct intel_plane *plane,
> > skl_surf_address(plane_state, color_plane);
> >  
> > if (DISPLAY_VER(dev_priv) < 12)
> > -   aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > +   aux_dist |= 
> > PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
> > }
> >  
> > spin_lock_irqsave(_priv->uncore.lock, irqflags);
> > @@ -,14 +1112,14 @@ skl_program_plane_arm(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
> >  
> > intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> > - (y << 16) | x);
> > + PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
> >  
> > intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> >  
> > if (DISPLAY_VER(dev_priv) < 11)
> > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
> > - (plane_state->view.color_plane[1].y << 16) |
> > -  plane_state->view.color_plane[1].x);
> > + 
> > PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
> > + 
> > PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
> >  
> > if (DISPLAY_VER(dev_priv) >= 10)
> > intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), 
> > plane_color_ctl);
> > @@ -2262,16 +2263,17 @@ skl_get_initial_plane_config(struct intel_crtc 
> > *crtc,
> > val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
> >  
> > if (DISPLAY_VER(dev_priv) >= 11)
> > -   pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
> > +   pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
> 
> Most of our platform bits definition follows  ver>_.

s/most/some/

I want it exactly the other way around so that the namespace for
each register is consistent.

> 
> Other than that the idea looks good to me.
> 
> > else
> > -   pixel_format = val & PLANE_CTL_FORMAT_MASK;
> > +   pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
> >  
> > if (DISPLAY_VER(dev_priv) >= 10) {
> > -   alpha = intel_de_read(dev_priv,
> > - PLANE_COLOR_CTL(pipe, plane_id));
> > -   alpha &= PLANE_COLOR_ALPHA_MASK;
> > +   u32 color_ctl;
> > +
> > +   color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, 
> > plane_id));
> > +   alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
> > } else {
> > -   alpha = val & PLANE_CTL_ALPHA_MASK;
> > +   alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
> > }
> >  
> > fourcc = skl_format_to_fourcc(pixel_format,
> > @@ -2335,19 +2337,19 @@ skl_get_initial_plane_config(struct intel_crtc 
> > *crtc,
> > if (drm_rotation_90_or_270(plane_config->rotation))
> > goto error;
> >  
> > -   base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xf000;
> > +   base = intel_de_read(dev_priv, 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reject 5k on HDR planes for planar fb formats (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev9)
URL   : https://patchwork.freedesktop.org/series/97053/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10954 -> Patchwork_21728


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/index.html

Participating hosts (33 -> 32)
--

  Additional (1): fi-kbl-soraka 
  Missing(2): fi-bsw-cyan fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_21728 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271]) +2 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s0:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][2] ([i915#4221])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_pm_rpm@basic-rte:
- fi-hsw-4770:[PASS][3] -> [SKIP][4] ([fdo#109271]) +2 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/fi-hsw-4770/igt@i915_pm_...@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
- fi-skl-6600u:   [PASS][5] -> [FAIL][6] ([i915#579])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/fi-skl-6600u/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/fi-skl-6600u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][7] -> [INCOMPLETE][8] ([i915#2940])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1436] / 
[i915#2722] / [i915#3428] / [i915#4312])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/fi-bsw-nick/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4:  [FAIL][10] ([i915#1888]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10954/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#4221]: https://gitlab.freedesktop.org/drm/intel/issues/4221
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579


Build changes
-

  * Linux: CI_DRM_10954 -> Patchwork_21728

  CI-20190529: 20190529
  CI_DRM_10954: 8ea5e088c7d1b759052d0c04e51d31bd2c72f98d @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6299: 0933b7ccdb2bb054b6a8154171e35315d84299b7 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21728: 30dac13d1d1cc585c3ccd8cc0705e477c90b70a1 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

30dac13d1d1c drm/i915: Add PLANE_CUS_CTL restriction in max_width

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21728/index.html

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Reject 5k on HDR planes for planar fb formats (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev9)
URL   : https://patchwork.freedesktop.org/series/97053/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
30dac13d1d1c drm/i915: Add PLANE_CUS_CTL restriction in max_width
-:41: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#41: FILE: drivers/gpu/drm/i915/display/skl_universal_plane.c:424:
+static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
+   int color_plane,

-:51: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#51: FILE: drivers/gpu/drm/i915/display/skl_universal_plane.c:434:
+static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
+   int color_plane,

total: 0 errors, 0 warnings, 2 checks, 33 lines checked

Re: [Intel-gfx] [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width

[Ville Syrjälä]

On Thu, Dec 02, 2021 at 04:38:36PM +0530, Vidya Srinivas wrote:
> PLANE_CUS_CTL has a restriction of 4096 width even though
> PLANE_SIZE and scaler size registers supports max 5120.
> Take care of this restriction in max_width.
> 
> Without this patch, when 5k content is sent on HDR plane
> with NV12 content, FIFO underrun is seen and screen blanks
> out.
> 
> v2: Addressed review comments from Ville. Added separate
> functions for max_width - for HDR and SDR
> 
> v3: Addressed review comments from Ville. Changed names of
> HDR and SDR max_width functions to icl_hdr_plane_max_width
> and icl_sdr_plane_max_width
> 
> v4: Fixed paranthesis alignment. No code change
> 
> Reviewed-by: Ville Syrjälä 
> Signed-off-by: Vidya Srinivas 

Pushed to drm-intel-next. Thanks.

> ---
>  .../drm/i915/display/skl_universal_plane.c| 21 +++
>  1 file changed, 17 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 28890876bdeb..e717eb58b105 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -420,9 +420,19 @@ static int icl_plane_min_width(const struct 
> drm_framebuffer *fb,
>   }
>  }
>  
> -static int icl_plane_max_width(const struct drm_framebuffer *fb,
> -int color_plane,
> -unsigned int rotation)
> +static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
> + int color_plane,
> + unsigned int rotation)
> +{
> + if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> + return 4096;
> + else
> + return 5120;
> +}
> +
> +static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
> + int color_plane,
> + unsigned int rotation)
>  {
>   return 5120;
>  }
> @@ -2108,7 +2118,10 @@ skl_universal_plane_create(struct drm_i915_private 
> *dev_priv,
>  
>   if (DISPLAY_VER(dev_priv) >= 11) {
>   plane->min_width = icl_plane_min_width;
> - plane->max_width = icl_plane_max_width;
> + if (icl_is_hdr_plane(dev_priv, plane_id))
> + plane->max_width = icl_hdr_plane_max_width;
> + else
> + plane->max_width = icl_sdr_plane_max_width;
>   plane->max_height = icl_plane_max_height;
>   plane->min_cdclk = icl_plane_min_cdclk;
>   } else if (DISPLAY_VER(dev_priv) >= 10) {
> -- 
> 2.33.0

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v4 1/6] drm: move the buddy allocator from i915 into common drm

[Christian König]

Am 01.12.21 um 17:39 schrieb Arunpravin:

Move the base i915 buddy allocator code into drm
- Move i915_buddy.h to include/drm
- Move i915_buddy.c to drm root folder
- Rename "i915" string with "drm" string wherever applicable
- Rename "I915" string with "DRM" string wherever applicable
- Fix header file dependencies
- Fix alignment issues
- add Makefile support for drm buddy
- export functions and write kerneldoc description
- Remove i915 selftest config check condition as buddy selftest
   will be moved to drm selftest folder

cleanup i915 buddy references in i915 driver module
and replace with drm buddy

v2:
   - include header file in alphabetical order(Thomas)
   - merged changes listed in the body section into a single patch
 to keep the build intact(Christian, Jani)

v3:
   - make drm buddy a separate module(Thomas, Christian)


I only skimmed over this, but this looks really good now.

Only remaining problem is that you need to fix the build error reported 
by the kernel robot in drivers/gpu/drm/i915/selftests/intel_memory_region.c.


I strongly suggest that you use a build test config with all DRM drivers 
and selftests enabled to narrow down things like that before sending it 
out. I can help with that if necessary.


Regards,
Christian.



Signed-off-by: Arunpravin 
---
  drivers/gpu/drm/Kconfig   |   6 +
  drivers/gpu/drm/Makefile  |   2 +
  drivers/gpu/drm/drm_buddy.c   | 516 ++
  drivers/gpu/drm/i915/Kconfig  |   1 +
  drivers/gpu/drm/i915/Makefile |   1 -
  drivers/gpu/drm/i915/i915_buddy.c | 466 
  drivers/gpu/drm/i915/i915_buddy.h | 143 -
  drivers/gpu/drm/i915/i915_module.c|   3 -
  drivers/gpu/drm/i915/i915_scatterlist.c   |  11 +-
  drivers/gpu/drm/i915/i915_ttm_buddy_manager.c |  33 +-
  drivers/gpu/drm/i915/i915_ttm_buddy_manager.h |   4 +-
  include/drm/drm_buddy.h   | 154 ++
  12 files changed, 703 insertions(+), 637 deletions(-)
  create mode 100644 drivers/gpu/drm/drm_buddy.c
  delete mode 100644 drivers/gpu/drm/i915/i915_buddy.c
  delete mode 100644 drivers/gpu/drm/i915/i915_buddy.h
  create mode 100644 include/drm/drm_buddy.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 0039df26854b..7a4a66d54782 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -197,6 +197,12 @@ config DRM_TTM
  GPU memory types. Will be enabled automatically if a device driver
  uses it.
  
+config DRM_BUDDY

+   tristate
+   depends on DRM
+   help
+ A page based buddy allocator
+
  config DRM_VRAM_HELPER
tristate
depends on DRM
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 0dff40bb863c..e62e432bf1e5 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -35,6 +35,8 @@ drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
  
  obj-$(CONFIG_DRM_DP_AUX_BUS) += drm_dp_aux_bus.o
  
+obj-$(CONFIG_DRM_BUDDY) += drm_buddy.o

+
  drm_vram_helper-y := drm_gem_vram_helper.o
  obj-$(CONFIG_DRM_VRAM_HELPER) += drm_vram_helper.o
  
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c

new file mode 100644
index ..9340a4b61c5a
--- /dev/null
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -0,0 +1,516 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+static struct drm_buddy_block *drm_block_alloc(struct drm_buddy_mm *mm,
+  struct drm_buddy_block *parent,
+  unsigned int order,
+  u64 offset)
+{
+   struct drm_buddy_block *block;
+
+   BUG_ON(order > DRM_BUDDY_MAX_ORDER);
+
+   block = kmem_cache_zalloc(mm->slab_blocks, GFP_KERNEL);
+   if (!block)
+   return NULL;
+
+   block->header = offset;
+   block->header |= order;
+   block->parent = parent;
+
+   BUG_ON(block->header & DRM_BUDDY_HEADER_UNUSED);
+   return block;
+}
+
+static void drm_block_free(struct drm_buddy_mm *mm,
+  struct drm_buddy_block *block)
+{
+   kmem_cache_free(mm->slab_blocks, block);
+}
+
+static void mark_allocated(struct drm_buddy_block *block)
+{
+   block->header &= ~DRM_BUDDY_HEADER_STATE;
+   block->header |= DRM_BUDDY_ALLOCATED;
+
+   list_del(>link);
+}
+
+static void mark_free(struct drm_buddy_mm *mm,
+ struct drm_buddy_block *block)
+{
+   block->header &= ~DRM_BUDDY_HEADER_STATE;
+   block->header |= DRM_BUDDY_FREE;
+
+   list_add(>link,
+>free_list[drm_buddy_block_order(block)]);
+}
+
+static void mark_split(struct drm_buddy_block *block)
+{
+   block->header &= ~DRM_BUDDY_HEADER_STATE;
+   block->header |= DRM_BUDDY_SPLIT;
+
+   

[Intel-gfx] [PATCH] drm: get rid of DRM_DEBUG_* log calls in drm core, files drm_a*.c

[Mastan Katragadda]

From: Claudio Suarez 

igt_check_plane_state test crashes in drm_atomic_helper_check_plane_state
when trying to de-reference drm_plane_state->plane->dev
due to the lack of a struct drm_plane in the mock struct drm_plane_state.
Since drm_plane_state always should contain a plane, the mock also
needs a plane to be the test more robust and realistic. Add it.

fails when the drm_device
cannot be found in the parameter plane_state->crtc.
Fix it using plane_state->plane.

[788.441343] [IGT] kms_selftest: starting dynamic subtest check_plane_state
[788.450045] BUG: kernel NULL pointer dereference, address: 0010
[788.450068] #PF: supervisor read access in kernel mode
[788.450077] #PF: error_code(0x) - not-present page
[788.450085] PGD 0 P4D 0
[788.450094] Oops:  [#1] PREEMPT SMP NOPTI
[788.450103] CPU: 2 PID: 1529 Comm: kms_selftest Not tainted 
5.16.0-rc2-CI-CI_DRM_10934+ #1
[788.450116] Hardware name:  /NUC6CAYB, BIOS AYAPLCEL.86A.0049.2018.0508.1356 
05/08/2018
[788.450128] RIP: 0010:drm_atomic_helper_check_plane_state+0x1a3/0x2e0 
[drm_kms_helper]
[788.450178] Code: 80 00 00 00 01 75 6b 80 7c 24 08 00 75 64 8b 44 24 18 41 39 
46 70 75 0e
8b 44 24 20 41 39 46 78 0f 84 c8 00 00 00 49 8b 46 08 <48> 8b 38 48 85 ff 74 04 
48 8b 7f 08 48
c7 c2 08 cf 12 a0 be 04 00
[788.450202] RSP: 0018:c9cd3970 EFLAGS: 00010287
[788.450213] RAX: 0010 RBX: c9cd3a38 RCX: 0001
[788.450223] RDX: 0800 RSI: 0800 RDI: c9cd3a38
[788.450234] RBP: c9cd3a48 R08: c9cd3a48 R09: c9cd3a38
[788.450244] R10: c9cd3988 R11: 0418 R12: 0001
[788.450254] R13: 0001 R14: c9cd39d8 R15: c9cd3a70
[788.450267] FS:  7f46e1479c00() GS:88827790() 
knlGS:
[788.450280] CS:  0010 DS:  ES:  CR0: 80050033
[788.450289] CR2: 0010 CR3: 0001086ba000 CR4: 003506e0
[788.450299] Call Trace:
[788.450306]  
[788.450314]  ? 0xa0612000
[788.450323]  igt_check_plane_state+0x236/0x730 [test_drm_modeset]
[788.450357]  test_drm_modeset_init+0x7c/0x1000 [test_drm_modeset]

Link : https://gitlab.freedesktop.org/drm/intel/-/issues/4663

Signed-off-by: Claudio Suarez 
Signed-off-by: Mastan Katragadda 
---
 drivers/gpu/drm/drm_atomic_helper.c   | 12 ++--
 drivers/gpu/drm/selftests/test-drm_plane_helper.c |  6 ++
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index aef2fbd676e5..a7a05e1e26bb 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -828,8 +828,8 @@ int drm_atomic_helper_check_plane_state(struct 
drm_plane_state *plane_state,
}
 
if (!crtc_state->enable && !can_update_disabled) {
-   drm_dbg_kms(plane_state->crtc->dev,
-  "Cannot update plane of a disabled CRTC.\n");
+   drm_dbg_kms(plane_state->plane->dev,
+   "Cannot update plane of a disabled CRTC.\n");
return -EINVAL;
}
 
@@ -839,8 +839,8 @@ int drm_atomic_helper_check_plane_state(struct 
drm_plane_state *plane_state,
hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
if (hscale < 0 || vscale < 0) {
-   drm_dbg_kms(plane_state->crtc->dev,
-  "Invalid scaling of plane\n");
+   drm_dbg_kms(plane_state->plane->dev,
+   "Invalid scaling of plane\n");
drm_rect_debug_print("src: ", _state->src, true);
drm_rect_debug_print("dst: ", _state->dst, false);
return -ERANGE;
@@ -864,8 +864,8 @@ int drm_atomic_helper_check_plane_state(struct 
drm_plane_state *plane_state,
return 0;
 
if (!can_position && !drm_rect_equals(dst, )) {
-   drm_dbg_kms(plane_state->crtc->dev,
-  "Plane must cover entire CRTC\n");
+   drm_dbg_kms(plane_state->plane->dev,
+   "Plane must cover entire CRTC\n");
drm_rect_debug_print("dst: ", dst, false);
drm_rect_debug_print("clip: ", , false);
return -EINVAL;
diff --git a/drivers/gpu/drm/selftests/test-drm_plane_helper.c 
b/drivers/gpu/drm/selftests/test-drm_plane_helper.c
index 0a9553f51796..e865563be7d0 100644
--- a/drivers/gpu/drm/selftests/test-drm_plane_helper.c
+++ b/drivers/gpu/drm/selftests/test-drm_plane_helper.c
@@ -87,11 +87,17 @@ int igt_check_plane_state(void *ignored)
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
},
};
+
+   struct drm_plane plane = {
+   .dev = NULL
+   };
+
struct drm_framebuffer fb = {
.width = 

Re: [Intel-gfx] [v3 3/3] drm/i915/rpl-s: Enable guc submission by default

[Souza, Jose]

On Wed, 2021-12-01 at 02:33 -0800, Anusha Srivatsa wrote:
> Though, RPL-S is defined as subplatform of ADL-S, unlike
> ADL-S, it has GuC submission by default.
> 
> v2: Remove extra parenthesis (Jani)
> v3: s/IS_RAPTORLAKE/IS_ADLS_RPLS (Jani)
> 

Reviewed-by: José Roberto de Souza 

> Cc: Jani Nikula 
> Cc: Swathi Dhanavanthri 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 2fef3b0bbe95..8f17005ce85f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -35,7 +35,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
>   }
>  
>   /* Intermediate platforms are HuC authentication only */
> - if (IS_ALDERLAKE_S(i915)) {
> + if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
>   i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
>   return;
>   }

Re: [Intel-gfx] [v3 1/3] drm/i915/rpl-s: Add PCI IDS for Raptor Lake S

[Souza, Jose]

On Wed, 2021-12-01 at 02:33 -0800, Anusha Srivatsa wrote:
> Raptor Lake S(RPL-S) is a version 12
> Display, Media and Render. For all i915
> purposes it is the same as Alder Lake S (ADL-S).
> 
> Introduce RPL-S as a subplatform
> of ADL-S. This patch adds PCI ids for RPL-S.
> 
> v2: Update PCI IDs.
> - Add more description to commit message (Jani)
> 
> v3: s/IS_RAPTORLAKE/IS_ADLS_RPLS (Jani)
> - Fix comment (Tvrtko)
> 
> BSpec: 53655

In my opinion there is more ids add but those can be added in another patch.

Reviewed-by: José Roberto de Souza 

> 
> Cc: Matt Roper 
> Cc: Tvrtko Ursulin 
> Cc: Swathi Dhanavanthri 
> Cc: Jani Nikula 
> Signed-off-by: Anusha Srivatsa 
> ---
>  arch/x86/kernel/early-quirks.c   | 1 +
>  drivers/gpu/drm/i915/i915_drv.h  | 2 ++
>  drivers/gpu/drm/i915/i915_pci.c  | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c | 7 +++
>  drivers/gpu/drm/i915/intel_device_info.h | 3 +++
>  include/drm/i915_pciids.h| 9 +
>  6 files changed, 23 insertions(+)
> 
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 391a4e2b8604..fd2d3ab38ebb 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -554,6 +554,7 @@ static const struct pci_device_id intel_early_ids[] 
> __initconst = {
>   INTEL_RKL_IDS(_early_ops),
>   INTEL_ADLS_IDS(_early_ops),
>   INTEL_ADLP_IDS(_early_ops),
> + INTEL_RPLS_IDS(_early_ops),
>  };
>  
>  struct resource intel_graphics_stolen_res __ro_after_init = 
> DEFINE_RES_MEM(0, 0);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1bfadd9127fc..88c4fd80dcbe 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1469,6 +1469,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
>  #define IS_DG2_G11(dev_priv) \
>   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
> +#define IS_ADLS_RPLS(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>   (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>  #define IS_BDW_ULT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f01cba4ec283..061b2e076373 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1131,6 +1131,7 @@ static const struct pci_device_id pciidlist[] = {
>   INTEL_ADLS_IDS(_s_info),
>   INTEL_ADLP_IDS(_p_info),
>   INTEL_DG1_IDS(_info),
> + INTEL_RPLS_IDS(_s_info),
>   {0, 0, 0}
>  };
>  MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 6e6b317bc33c..cae51d9dd7ea 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -182,6 +182,10 @@ static const u16 subplatform_portf_ids[] = {
>   INTEL_ICL_PORT_F_IDS(0),
>  };
>  
> +static const u16 subplatform_rpls_ids[] = {
> + INTEL_RPLS_IDS(0),
> +};
> +
>  static bool find_devid(u16 id, const u16 *p, unsigned int num)
>  {
>   for (; num; num--, p++) {
> @@ -218,6 +222,9 @@ void intel_device_info_subplatform_init(struct 
> drm_i915_private *i915)
>   } else if (find_devid(devid, subplatform_portf_ids,
> ARRAY_SIZE(subplatform_portf_ids))) {
>   mask = BIT(INTEL_SUBPLATFORM_PORTF);
> + } else if (find_devid(devid, subplatform_rpls_ids,
> +   ARRAY_SIZE(subplatform_rpls_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_RPL_S);
>   }
>  
>   if (IS_TIGERLAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 669f0d26c3c3..2bedf73e0a7d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -110,6 +110,9 @@ enum intel_platform {
>  #define INTEL_SUBPLATFORM_G100
>  #define INTEL_SUBPLATFORM_G111
>  
> +/* ADL-S */
> +#define INTEL_SUBPLATFORM_RPL_S  0
> +
>  enum intel_ppgtt_type {
>   INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
>   INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index c00ac54692d7..baf3d1d3d566 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -666,4 +666,13 @@
>   INTEL_VGA_DEVICE(0x46C2, info), \
>   INTEL_VGA_DEVICE(0x46C3, info)
>  
> +/* RPL-S */
> +#define INTEL_RPLS_IDS(info) \
> + INTEL_VGA_DEVICE(0xA780, info), \
> + INTEL_VGA_DEVICE(0xA781, info), \
> + INTEL_VGA_DEVICE(0xA782, info), \
> + INTEL_VGA_DEVICE(0xA783, info), \
> + INTEL_VGA_DEVICE(0xA788, info), \
> + INTEL_VGA_DEVICE(0xA789, info)
> +
>  #endif /* 

Re: [Intel-gfx] [v3 2/3] drm/i915/rpl-s: Add PCH Support for Raptor Lake S

[Souza, Jose]

On Wed, 2021-12-01 at 02:33 -0800, Anusha Srivatsa wrote:
> Add the PCH ID for RPL-S.
> 
> v2: Self contained commit message (Jani)

Reviewed-by: José Roberto de Souza 

> 
> Cc: Jani Nikula 
> Cc: Swathi Dhanavanthri 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/intel_pch.c | 1 +
>  drivers/gpu/drm/i915/intel_pch.h | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pch.c 
> b/drivers/gpu/drm/i915/intel_pch.c
> index d1d4b97b86f5..da8f82c2342f 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -129,6 +129,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, 
> unsigned short id)
>   return PCH_JSP;
>   case INTEL_PCH_ADP_DEVICE_ID_TYPE:
>   case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
> + case INTEL_PCH_ADP3_DEVICE_ID_TYPE:
>   drm_dbg_kms(_priv->drm, "Found Alder Lake PCH\n");
>   drm_WARN_ON(_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
>   !IS_ALDERLAKE_P(dev_priv));
> diff --git a/drivers/gpu/drm/i915/intel_pch.h 
> b/drivers/gpu/drm/i915/intel_pch.h
> index 7c0d83d292dc..6bff77521094 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -57,6 +57,7 @@ enum intel_pch {
>  #define INTEL_PCH_JSP2_DEVICE_ID_TYPE0x3880
>  #define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
>  #define INTEL_PCH_ADP2_DEVICE_ID_TYPE0x5180
> +#define INTEL_PCH_ADP3_DEVICE_ID_TYPE0x7A00
>  #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
>  #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
>  #define INTEL_PCH_QEMU_DEVICE_ID_TYPE0x2900 /* qemu q35 has 
> 2918 */

Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Do not return '0' if there is nothing to return

[Maciej Patelczyk]

Andi Shyti  writes:

> Change functions that always return '0' to be void type.
>
> Signed-off-by: Andi Shyti 
> Cc: Maciej Patelczyk 
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_debugfs.c|  7 ---
>  drivers/gpu/drm/i915/gt/intel_gt_debugfs.h|  2 +-
>  drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 16 
>  drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h |  4 ++--
>  drivers/gpu/drm/i915/i915_debugfs.c   | 12 +---
>  5 files changed, 24 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c 
> b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> index f103664b71d4..53b90b4f73d7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> @@ -29,7 +29,7 @@ int intel_gt_debugfs_reset_show(struct intel_gt *gt, u64 
> *val)
>   }
>  }
>  
> -int intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val)
> +void intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val)
>  {
>   /* Flush any previous reset before applying for a new one */
>   wait_event(gt->reset.queue,
> @@ -37,7 +37,6 @@ int intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 
> val)
>  
>   intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
> "Manually reset engine mask to %llx", val);
> - return 0;
>  }
>  
>  /*
> @@ -51,7 +50,9 @@ static int __intel_gt_debugfs_reset_show(void *data, u64 
> *val)
>  
>  static int __intel_gt_debugfs_reset_store(void *data, u64 val)
>  {
> - return intel_gt_debugfs_reset_store(data, val);
> + intel_gt_debugfs_reset_store(data, val);
> +
> + return 0;
>  }
>  
>  DEFINE_SIMPLE_ATTRIBUTE(reset_fops, __intel_gt_debugfs_reset_show,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
> index e307ceb99031..a4baf8e7f068 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
> @@ -37,6 +37,6 @@ void intel_gt_debugfs_register_files(struct dentry *root,
>  
>  /* functions that need to be accessed by the upper level non-gt interfaces */
>  int intel_gt_debugfs_reset_show(struct intel_gt *gt, u64 *val);
> -int intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val);
> +void intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val);
>  
>  #endif /* INTEL_GT_DEBUGFS_H */
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
> b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 404dfa7673c6..7a30157aa9d3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -20,38 +20,38 @@
>  #include "intel_uncore.h"
>  #include "vlv_sideband.h"
>  
> -int intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt)
> +void intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt)
>  {
>   atomic_inc(>user_wakeref);
>   intel_gt_pm_get(gt);
>   if (GRAPHICS_VER(gt->i915) >= 6)
>   intel_uncore_forcewake_user_get(gt->uncore);
> -
> - return 0;
>  }
>  
> -int intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt)
> +void intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt)
>  {
>   if (GRAPHICS_VER(gt->i915) >= 6)
>   intel_uncore_forcewake_user_put(gt->uncore);
>   intel_gt_pm_put(gt);
>   atomic_dec(>user_wakeref);
> -
> - return 0;
>  }
>  
>  static int forcewake_user_open(struct inode *inode, struct file *file)
>  {
>   struct intel_gt *gt = inode->i_private;
>  
> - return intel_gt_pm_debugfs_forcewake_user_open(gt);
> + intel_gt_pm_debugfs_forcewake_user_open(gt);
> +
> + return 0;
>  }
>  
>  static int forcewake_user_release(struct inode *inode, struct file *file)
>  {
>   struct intel_gt *gt = inode->i_private;
>  
> - return intel_gt_pm_debugfs_forcewake_user_release(gt);
> + intel_gt_pm_debugfs_forcewake_user_release(gt);
> +
> + return 0;
>  }
>  
>  static const struct file_operations forcewake_user_fops = {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
> index a8457887ec65..0ace8c2da0ac 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
> @@ -14,7 +14,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, 
> struct dentry *root);
>  void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *m);
>  
>  /* functions that need to be accessed by the upper level non-gt interfaces */
> -int intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt);
> -int intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt);
> +void intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt);
> +void intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt);
>  
>  #endif /* INTEL_GT_PM_DEBUGFS_H */
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 

[Intel-gfx] [PATCH] drm/i915/snps: use div32 version of MPLLB word clock for UHBR

[Jani Nikula]

The mode set sequence for 128b/132b requires setting the div32 version
of MPLLB clock.

Bspec: 53880, 54128
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 ++
 drivers/gpu/drm/i915/i915_reg.h   | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c 
b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index c2251218a39e..09f405e4d363 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -186,6 +186,7 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_100 = {
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
+   REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
.mpllb_div2 =
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
@@ -369,6 +370,7 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
+   REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
.mpllb_div2 =
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3450818802c2..1fad1d593e13 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2265,6 +2265,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   SNPS_PHY_MPLLB_DP2_MODE  REG_BIT(9)
 #define   SNPS_PHY_MPLLB_WORD_DIV2_EN  REG_BIT(8)
 #define   SNPS_PHY_MPLLB_TX_CLK_DIVREG_GENMASK(7, 5)
+#define   SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SELREG_BIT(0)
 
 #define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
 #define   SNPS_PHY_MPLLB_FRACN_EN  REG_BIT(31)
-- 
2.30.2