date:20110804

This is a mostly mindless conversion of all QEMU PCI devices to the memory API.
After this patchset is applied, it is no longer possible to create a PCI device
using the old API.

An immediate benefit is that PCI BARs that overlap each other are now handled
correctly: currently, the sequence

  map BAR 0
  map BAR 1 at an overlapping address
  unmap either BAR 0 or BAR 1

will leave a hole where the overlap exists.  With the patchset, the memory map
is restored correctly.

Note that overlaps of PCI BARs with memory or non-PCI resources are still not
resolved correctly; this will be fixed later on.

The vga patches have ugly intermediate states; however the result is fairly 
clean.

This patchset should be merged after

  memory: synchronize dirty bitmap before unmapping a range
  memory: use signed arithmetic

though there's no hard dependency.

Changes from v2:
 - added patch from Michael simplifying virtio-pci config setup

Changes from v1:
 - cmd646 type fix
 - folded a fixlet into its parent

Avi Kivity (38):
  pci: add API to get a BAR's mapped address
  vmsvga: don't remember pci BAR address in callback any more
  vga: convert vga and its derivatives to the memory API
  cirrus: simplify mmio BAR access functions
  cirrus: simplify bitblt BAR access functions
  cirrus: simplify vga window mmio access functions
  vga: simplify vga window mmio access functions
  cirrus: simplify linear framebuffer access functions
  Integrate I/O memory regions into qemu
  pci: pass I/O address space to new PCI bus
  pci: allow I/O BARs to be registered with pci_register_bar_region()
  rtl8139: convert to memory API
  ac97: convert to memory API
  e1000: convert to memory API
  eepro100: convert to memory API
  es1370: convert to memory API
  ide: convert to memory API
  ivshmem: convert to memory API
  virtio-pci: convert to memory API
  ahci: convert to memory API
  intel-hda: convert to memory API
  lsi53c895a: convert to memory API
  ppc: convert to memory API
  ne2000: convert to memory API
  pcnet: convert to memory API
  i6300esb: convert to memory API
  isa-mmio: concert to memory API
  sun4u: convert to memory API
  ehci: convert to memory API
  uhci: convert to memory API
  xen-platform: convert to memory API
  msix: convert to memory API
  pci: remove pci_register_bar_simple()
  pci: convert pci rom to memory API
  pci: remove pci_register_bar()
  pci: fold BAR mapping function into its caller
  pci: rename pci_register_bar_region() to pci_register_bar()
  pci: remove support for pre memory API BARs

Michael S. Tsirkin (1):
  virtio-pci: get config on init

 exec-memory.h  |2 +
 exec.c |   10 ++
 hw/ac97.c  |   88 ++-
 hw/apb_pci.c   |1 +
 hw/bonito.c|1 +
 hw/cirrus_vga.c|  458 ---
 hw/cuda.c  |6 +-
 hw/e1000.c |  113 ++
 hw/eepro100.c  |  181 -
 hw/es1370.c|   43 +++--
 hw/escc.c  |   42 +++---
 hw/escc.h  |2 +-
 hw/grackle_pci.c   |8 +-
 hw/gt64xxx.c   |4 +-
 hw/heathrow_pic.c  |   29 ++--
 hw/ide.h   |2 +-
 hw/ide/ahci.c  |   31 ++--
 hw/ide/ahci.h  |2 +-
 hw/ide/cmd646.c|  204 +++-
 hw/ide/ich.c   |3 +-
 hw/ide/macio.c |   36 +++--
 hw/ide/pci.c   |   25 ++--
 hw/ide/pci.h   |   19 ++-
 hw/ide/piix.c  |   63 ++--
 hw/ide/via.c   |   64 ++--
 hw/intel-hda.c |   35 +++--
 hw/isa.h   |2 +
 hw/isa_mmio.c  |   30 ++--
 hw/ivshmem.c   |  158 +++
 hw/lance.c |   31 ++--
 hw/lsi53c895a.c|  257 +++---
 hw/mac_dbdma.c |   32 ++--
 hw/mac_dbdma.h |4 +-
 hw/mac_nvram.c |   39 ++---
 hw/macio.c |   73 -
 hw/msix.c  |   64 +++-
 hw/msix.h  |6 +-
 hw/ne2000-isa.c|   14 +--
 hw/ne2000.c|   77 ++---
 hw/ne2000.h|8 +-
 hw/openpic.c   |   81 +-
 hw/openpic.h   |2 +-
 hw/pc.h|4 +-
 hw/pc_piix.c   |6 +-
 hw/pci.c   |  133 +---
 hw/pci.h   |   26 ++--
 hw/pci_internals.h |3 +-
 hw/pcnet-pci.c |   74 +
 hw/pcnet.h |4 +-
 hw/piix_pci.c  |   14 +-
 hw/ppc4xx_pci.c|1 +
 hw/ppc_mac.h   |   27 ++--
 hw/ppc_newworld.c  |   34 ++--
 hw/ppc_oldworld.c  |   27 ++--
 hw/ppc_prep.c  |2 +-
 hw/ppce500_pci.c   |7 +-
 hw/prep_pci.c  |8 +-
 hw/prep_pci.h  |4 +-
 hw/qxl-render.c|2 +-
 hw/qxl.c   |  129 ++--
 hw/qxl.h   |6 +-
 hw/rtl8139.c   |   70 
 hw/sh_pci.c|4 +-
 hw/sun4u.c |   53 +++
 hw/unin_pci.c  |   16 ++-
 hw/usb-ehci.c  |   36 +---
 hw/usb-ohci.c  |2 +-
 hw/usb-uhci.c  |   41 +++--
 hw/versatile_pci.c |2 +-
 hw/vga-isa-mm.c|   45 --

[PATCH v3 02/39] pci: add API to get a BAR's mapped address

This is a hack, for devices that have a back-channel to read this
address back outside the normal configuration mechanisms, such
as VMware svga.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/pci.c |5 +
 hw/pci.h |1 +
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index 36db58b..912f849 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -952,6 +952,11 @@ void pci_register_bar_region(PCIDevice *pci_dev, int 
region_num,
 pci_dev-io_regions[region_num].memory = memory;
 }
 
+pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
+{
+return pci_dev-io_regions[region_num].addr;
+}
+
 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
   uint8_t type)
 {
diff --git a/hw/pci.h b/hw/pci.h
index c51156d..64282ad 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -207,6 +207,7 @@ void pci_register_bar_simple(PCIDevice *pci_dev, int 
region_num,
  pcibus_t size, uint8_t attr, ram_addr_t ram_addr);
 void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
  uint8_t attr, MemoryRegion *memory);
+pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 
 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
uint8_t offset, uint8_t size);
-- 
1.7.5.3

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[PATCH v3 01/39] virtio-pci: get config on init

From: Michael S. Tsirkin m...@redhat.com

We originally did get config on map, so that
following write accesses are done on an updated config.
New memory API doesn't give us a callback
on map, and arguably, devices don't know when
cpu really can access there. So updating on
init seems cleaner.

Signed-off-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/virtio-pci.c |7 ---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c
index d685243..ca1f12f 100644
--- a/hw/virtio-pci.c
+++ b/hw/virtio-pci.c
@@ -506,9 +506,6 @@ static void virtio_map(PCIDevice *pci_dev, int region_num,
 register_ioport_read(addr, config_len, 1, virtio_pci_config_readb, proxy);
 register_ioport_read(addr, config_len, 2, virtio_pci_config_readw, proxy);
 register_ioport_read(addr, config_len, 4, virtio_pci_config_readl, proxy);
-
-if (vdev-config_len)
-vdev-get_config(vdev, vdev-config);
 }
 
 static void virtio_write_config(PCIDevice *pci_dev, uint32_t address,
@@ -689,6 +686,10 @@ void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice 
*vdev)
 proxy-host_features |= 0x1  VIRTIO_F_NOTIFY_ON_EMPTY;
 proxy-host_features |= 0x1  VIRTIO_F_BAD_FEATURE;
 proxy-host_features = vdev-get_features(vdev, proxy-host_features);
+
+if (vdev-config_len) {
+vdev-get_config(vdev, vdev-config);
+}
 }
 
 static int virtio_blk_init_pci(PCIDevice *pci_dev)
-- 
1.7.5.3

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[PATCH v3 03/39] vmsvga: don't remember pci BAR address in callback any more

We're going to remove the callback, so we can't use it to save the
address.  Use the pci API instead.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/vmware_vga.c |   12 ++--
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index 354c221..190b005 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -52,8 +52,6 @@ struct vmsvga_state_s {
 int on;
 } cursor;
 
-target_phys_addr_t vram_base;
-
 int index;
 int scratch_size;
 uint32_t *scratch;
@@ -761,8 +759,11 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t 
address)
 case SVGA_REG_BYTES_PER_LINE:
 return ((s-depth + 7)  3) * s-new_width;
 
-case SVGA_REG_FB_START:
-return s-vram_base;
+case SVGA_REG_FB_START: {
+struct pci_vmsvga_state_s *pci_vmsvga
+= container_of(s, struct pci_vmsvga_state_s, chip);
+return pci_get_bar_addr(pci_vmsvga-card, 1);
+}
 
 case SVGA_REG_FB_OFFSET:
 return 0x0;
@@ -1247,14 +1248,13 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int 
region_num,
 struct vmsvga_state_s *s = d-chip;
 ram_addr_t iomemtype;
 
-s-vram_base = addr;
 #ifdef DIRECT_VRAM
 iomemtype = cpu_register_io_memory(vmsvga_vram_read,
 vmsvga_vram_write, s, DEVICE_NATIVE_ENDIAN);
 #else
 iomemtype = s-vga.vram_offset | IO_MEM_RAM;
 #endif
-cpu_register_physical_memory(s-vram_base, s-vga.vram_size,
+cpu_register_physical_memory(addr, s-vga.vram_size,
 iomemtype);
 
 s-vga.map_addr = addr;
-- 
1.7.5.3

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[PATCH v3 04/39] vga: convert vga and its derivatives to the memory API

Convert all vga memory to the memory API.  Note we need to fall back to
get_system_memory(), since the various buses don't pass the vga window
as a memory region.

We no longer need to sync the dirty bitmap of the cirrus mapped memory
banks, since the memory API takes care of that for us.

[jan: fix vga-pci logging]

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/cirrus_vga.c |  343 --
 hw/qxl-render.c |2 +-
 hw/qxl.c|  135 --
 hw/qxl.h|6 +-
 hw/vga-isa-mm.c |   45 +---
 hw/vga-isa.c|   11 +-
 hw/vga-pci.c|   28 +
 hw/vga.c|  147 +++-
 hw/vga_int.h|   14 +--
 hw/vmware_vga.c |  143 ---
 10 files changed, 440 insertions(+), 434 deletions(-)

diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index f39d1f8..d1475dd 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -200,9 +200,14 @@ typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
 typedef struct CirrusVGAState {
 VGACommonState vga;
 
-int cirrus_linear_io_addr;
-int cirrus_linear_bitblt_io_addr;
-int cirrus_mmio_io_addr;
+MemoryRegion cirrus_linear_io;
+MemoryRegion cirrus_linear_bitblt_io;
+MemoryRegion cirrus_mmio_io;
+MemoryRegion pci_bar;
+bool linear_vram;  /* vga.vram mapped over cirrus_linear_io */
+MemoryRegion low_mem_container; /* container for 0xa-0xc */
+MemoryRegion low_mem;   /* always mapped, overridden by: */
+MemoryRegion *cirrus_bank[2];   /*   aliases at 0xa-0xb  */
 uint32_t cirrus_addr_mask;
 uint32_t linear_mmio_mask;
 uint8_t cirrus_shadow_gr0;
@@ -612,7 +617,7 @@ static void cirrus_invalidate_region(CirrusVGAState * s, 
int off_begin,
off_cur_end = (off_cur + bytesperline)  s-cirrus_addr_mask;
off_cur = TARGET_PAGE_MASK;
while (off_cur  off_cur_end) {
-   cpu_physical_memory_set_dirty(s-vga.vram_offset + off_cur);
+   memory_region_set_dirty(s-vga.vram, off_cur);
off_cur += TARGET_PAGE_SIZE;
}
off_begin += off_pitch;
@@ -1177,12 +1182,6 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, 
unsigned bank_index)
 }
 
 if (limit  0) {
-/* Thinking about changing bank base? First, drop the dirty bitmap 
information
- * on the current location, otherwise we lose this pointer forever */
-if (s-vga.lfb_vram_mapped) {
-target_phys_addr_t base_addr = isa_mem_base + 0xa + bank_index 
* 0x8000;
-cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
-}
s-cirrus_bank_base[bank_index] = offset;
s-cirrus_bank_limit[bank_index] = limit;
 } else {
@@ -1921,8 +1920,8 @@ static void 
cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
val = 1;
dst++;
 }
-cpu_physical_memory_set_dirty(s-vga.vram_offset + offset);
-cpu_physical_memory_set_dirty(s-vga.vram_offset + offset + 7);
+memory_region_set_dirty(s-vga.vram, offset);
+memory_region_set_dirty(s-vga.vram, offset + 7);
 }
 
 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
@@ -1946,8 +1945,8 @@ static void 
cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
val = 1;
dst += 2;
 }
-cpu_physical_memory_set_dirty(s-vga.vram_offset + offset);
-cpu_physical_memory_set_dirty(s-vga.vram_offset + offset + 15);
+memory_region_set_dirty(s-vga.vram, offset);
+memory_region_set_dirty(s-vga.vram, offset + 15);
 }
 
 /***
@@ -2057,8 +2056,7 @@ static void cirrus_vga_mem_writeb(void *opaque, 
target_phys_addr_t addr,
mode = s-vga.gr[0x05]  0x7;
if (mode  4 || mode  5 || ((s-vga.gr[0x0B]  0x4) == 0)) {
*(s-vga.vram_ptr + bank_offset) = mem_value;
-   cpu_physical_memory_set_dirty(s-vga.vram_offset +
- bank_offset);
+   memory_region_set_dirty(s-vga.vram, bank_offset);
} else {
if ((s-vga.gr[0x0B]  0x14) != 0x14) {
cirrus_mem_writeb_mode4and5_8bpp(s, mode,
@@ -2099,16 +2097,37 @@ static void cirrus_vga_mem_writel(void *opaque, 
target_phys_addr_t addr, uint32_
 cirrus_vga_mem_writeb(opaque, addr + 3, (val  24)  0xff);
 }
 
-static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
-cirrus_vga_mem_readb,
-cirrus_vga_mem_readw,
-cirrus_vga_mem_readl,
+static uint64_t cirrus_vga_mem_read(void *opaque,
+target_phys_addr_t addr,
+uint32_t size)
+{
+CirrusVGAState *s = opaque;
+
+switch (size) {
+case 1: return cirrus_vga_mem_readb(s, addr);
+case 2: return cirrus_vga_mem_readw(s, addr);
+case 4: return cirrus_vga_mem_readl(s, addr);
+

[PATCH v3 06/39] cirrus: simplify bitblt BAR access functions

Make use of the memory API's ability to satisfy multi-byte accesses via
multiple single-byte accesses.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/cirrus_vga.c |   81 +--
 1 files changed, 13 insertions(+), 68 deletions(-)

diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 6e1aa75..b8a51b4 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2445,37 +2445,23 @@ static void cirrus_linear_write(void *opaque, 
target_phys_addr_t addr,
  ***/
 
 
-static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t 
addr)
+static uint64_t cirrus_linear_bitblt_read(void *opaque,
+  target_phys_addr_t addr,
+  unsigned size)
 {
+CirrusVGAState *s = opaque;
 uint32_t ret;
 
 /* XXX handle bitblt */
+(void)s;
 ret = 0xff;
 return ret;
 }
 
-static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t 
addr)
-{
-uint32_t v;
-
-v = cirrus_linear_bitblt_readb(opaque, addr);
-v |= cirrus_linear_bitblt_readb(opaque, addr + 1)  8;
-return v;
-}
-
-static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t 
addr)
-{
-uint32_t v;
-
-v = cirrus_linear_bitblt_readb(opaque, addr);
-v |= cirrus_linear_bitblt_readb(opaque, addr + 1)  8;
-v |= cirrus_linear_bitblt_readb(opaque, addr + 2)  16;
-v |= cirrus_linear_bitblt_readb(opaque, addr + 3)  24;
-return v;
-}
-
-static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
-uint32_t val)
+static void cirrus_linear_bitblt_write(void *opaque,
+   target_phys_addr_t addr,
+   uint64_t val,
+   unsigned size)
 {
 CirrusVGAState *s = opaque;
 
@@ -2488,55 +2474,14 @@ static void cirrus_linear_bitblt_writeb(void *opaque, 
target_phys_addr_t addr,
 }
 }
 
-static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-cirrus_linear_bitblt_writeb(opaque, addr, val  0xff);
-cirrus_linear_bitblt_writeb(opaque, addr + 1, (val  8)  0xff);
-}
-
-static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-cirrus_linear_bitblt_writeb(opaque, addr, val  0xff);
-cirrus_linear_bitblt_writeb(opaque, addr + 1, (val  8)  0xff);
-cirrus_linear_bitblt_writeb(opaque, addr + 2, (val  16)  0xff);
-cirrus_linear_bitblt_writeb(opaque, addr + 3, (val  24)  0xff);
-}
-
-static uint64_t cirrus_linear_bitblt_read(void *opaque,
-  target_phys_addr_t addr,
-  unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_linear_bitblt_readb(s, addr);
-case 2: return cirrus_linear_bitblt_readw(s, addr);
-case 4: return cirrus_linear_bitblt_readl(s, addr);
-default: abort();
-}
-};
-
-static void cirrus_linear_bitblt_write(void *opaque,
-   target_phys_addr_t addr,
-   uint64_t data,
-   unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_linear_bitblt_writeb(s, addr, data);
-case 2: return cirrus_linear_bitblt_writew(s, addr, data);
-case 4: return cirrus_linear_bitblt_writel(s, addr, data);
-default: abort();
-}
-};
-
 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
 .read = cirrus_linear_bitblt_read,
 .write = cirrus_linear_bitblt_write,
 .endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
 };
 
 #include exec-memory.h
-- 
1.7.5.3

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[PATCH v3 08/39] vga: simplify vga window mmio access functions

Make use of the memory API's ability to satisfy multi-byte accesses via
multiple single-byte accesses.

We have to keep vga_mem_{read,write}b() since they're used by cirrus.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/cirrus_vga.c |4 +-
 hw/vga.c|   56 +++---
 hw/vga_int.h|4 +-
 3 files changed, 12 insertions(+), 52 deletions(-)

diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 92696d9..3db15bf 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -1965,7 +1965,7 @@ static uint64_t cirrus_vga_mem_read(void *opaque,
 uint32_t val;
 
 if ((s-vga.sr[0x07]  0x01) == 0) {
-   return vga_mem_readb(s, addr);
+return vga_mem_readb(s-vga, addr);
 }
 
 if (addr  0x1) {
@@ -2010,7 +2010,7 @@ static void cirrus_vga_mem_write(void *opaque,
 unsigned mode;
 
 if ((s-vga.sr[0x07]  0x01) == 0) {
-   vga_mem_writeb(s, addr, mem_value);
+vga_mem_writeb(s-vga, addr, mem_value);
 return;
 }
 
diff --git a/hw/vga.c b/hw/vga.c
index cdd8255..f5dd519 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -707,9 +707,8 @@ static void vbe_ioport_write_data(void *opaque, uint32_t 
addr, uint32_t val)
 #endif
 
 /* called for accesses between 0xa and 0xc */
-uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
+uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)
 {
-VGACommonState *s = opaque;
 int memory_map_mode, plane;
 uint32_t ret;
 
@@ -763,28 +762,9 @@ uint32_t vga_mem_readb(void *opaque, target_phys_addr_t 
addr)
 return ret;
 }
 
-static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-v = vga_mem_readb(opaque, addr);
-v |= vga_mem_readb(opaque, addr + 1)  8;
-return v;
-}
-
-static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-v = vga_mem_readb(opaque, addr);
-v |= vga_mem_readb(opaque, addr + 1)  8;
-v |= vga_mem_readb(opaque, addr + 2)  16;
-v |= vga_mem_readb(opaque, addr + 3)  24;
-return v;
-}
-
 /* called for accesses between 0xa and 0xc */
-void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)
 {
-VGACommonState *s = opaque;
 int memory_map_mode, plane, write_mode, b, func_select, mask;
 uint32_t write_mask, bit_mask, set_mask;
 
@@ -916,20 +896,6 @@ void vga_mem_writeb(void *opaque, target_phys_addr_t addr, 
uint32_t val)
 }
 }
 
-static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-vga_mem_writeb(opaque, addr, val  0xff);
-vga_mem_writeb(opaque, addr + 1, (val  8)  0xff);
-}
-
-static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-vga_mem_writeb(opaque, addr, val  0xff);
-vga_mem_writeb(opaque, addr + 1, (val  8)  0xff);
-vga_mem_writeb(opaque, addr + 2, (val  16)  0xff);
-vga_mem_writeb(opaque, addr + 3, (val  24)  0xff);
-}
-
 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
  const uint8_t *font_ptr, int h,
  uint32_t fgcol, uint32_t bgcol);
@@ -2104,12 +2070,7 @@ static uint64_t vga_mem_read(void *opaque, 
target_phys_addr_t addr,
 {
 VGACommonState *s = opaque;
 
-switch (size) {
-case 1: return vga_mem_readb(s, addr);
-case 2: return vga_mem_readw(s, addr);
-case 4: return vga_mem_readl(s, addr);
-default: abort();
-}
+return vga_mem_readb(s, addr);
 }
 
 static void vga_mem_write(void *opaque, target_phys_addr_t addr,
@@ -2117,18 +2078,17 @@ static void vga_mem_write(void *opaque, 
target_phys_addr_t addr,
 {
 VGACommonState *s = opaque;
 
-switch (size) {
-case 1: return vga_mem_writeb(s, addr, data);
-case 2: return vga_mem_writew(s, addr, data);
-case 4: return vga_mem_writel(s, addr, data);
-default: abort();
-}
+return vga_mem_writeb(s, addr, data);
 }
 
 const MemoryRegionOps vga_mem_ops = {
 .read = vga_mem_read,
 .write = vga_mem_write,
 .endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
 };
 
 static int vga_common_post_load(void *opaque, int version_id)
diff --git a/hw/vga_int.h b/hw/vga_int.h
index 4592d2c..100d98c 100644
--- a/hw/vga_int.h
+++ b/hw/vga_int.h
@@ -198,8 +198,8 @@ void vga_dirty_log_restart(VGACommonState *s);
 extern const VMStateDescription vmstate_vga_common;
 uint32_t vga_ioport_read(void *opaque, uint32_t addr);
 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
-uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
-void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
+uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr);
+void vga_mem_writeb(VGACommonState *s, target_phys_addr_t

[PATCH v3 10/39] Integrate I/O memory regions into qemu

get_system_io() returns the root I/O memory region.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 exec-memory.h |2 ++
 exec.c|   10 ++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/exec-memory.h b/exec-memory.h
index c439aba..999fd69 100644
--- a/exec-memory.h
+++ b/exec-memory.h
@@ -28,6 +28,8 @@
  */
 MemoryRegion *get_system_memory(void);
 
+MemoryRegion *get_system_io(void);
+
 /* Set the root memory region.  This region is the system memory map. */
 void set_system_memory_map(MemoryRegion *mr);
 
diff --git a/exec.c b/exec.c
index 751fd89..c93c980 100644
--- a/exec.c
+++ b/exec.c
@@ -113,6 +113,7 @@ static int in_migration;
 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) };
 
 static MemoryRegion *system_memory;
+static MemoryRegion *system_io;
 
 #endif
 
@@ -3820,6 +3821,10 @@ static void memory_map_init(void)
 system_memory = qemu_malloc(sizeof(*system_memory));
 memory_region_init(system_memory, system, INT64_MAX);
 set_system_memory_map(system_memory);
+
+system_io = qemu_malloc(sizeof(*system_io));
+memory_region_init(system_io, io, 65536);
+set_system_io_map(system_io);
 }
 
 MemoryRegion *get_system_memory(void)
@@ -3827,6 +3832,11 @@ MemoryRegion *get_system_memory(void)
 return system_memory;
 }
 
+MemoryRegion *get_system_io(void)
+{
+return system_io;
+}
+
 #endif /* !defined(CONFIG_USER_ONLY) */
 
 /* physical memory access (slow version, mainly for debug) */
-- 
1.7.5.3

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[PATCH v3 12/39] pci: allow I/O BARs to be registered with pci_register_bar_region()

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/pci.c   |   43 +++
 hw/pci.h   |1 +
 hw/pci_internals.h |3 ++-
 3 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index 2659d96..980840f 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -271,7 +271,8 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 qbus_create_inplace(bus-qbus, pci_bus_info, parent, name);
 assert(PCI_FUNC(devfn_min) == 0);
 bus-devfn_min = devfn_min;
-bus-address_space = address_space_mem;
+bus-address_space_mem = address_space_mem;
+bus-address_space_io = address_space_io;
 
 /* host bridge */
 QLIST_INIT(bus-child);
@@ -847,12 +848,11 @@ static void pci_unregister_io_regions(PCIDevice *pci_dev)
 r = pci_dev-io_regions[i];
 if (!r-size || r-addr == PCI_BAR_UNMAPPED)
 continue;
-if (r-type == PCI_BASE_ADDRESS_SPACE_IO) {
-isa_unassign_ioport(r-addr, r-filtered_size);
+if (r-memory) {
+memory_region_del_subregion(r-address_space, r-memory);
 } else {
-if (r-memory) {
-memory_region_del_subregion(pci_dev-bus-address_space,
-r-memory);
+if (r-type == PCI_BASE_ADDRESS_SPACE_IO) {
+isa_unassign_ioport(r-addr, r-filtered_size);
 } else {
 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev-bus,
  r-addr),
@@ -934,9 +934,11 @@ static void pci_simple_bar_mapfunc_region(PCIDevice 
*pci_dev, int region_num,
   pcibus_t addr, pcibus_t size,
   int type)
 {
-memory_region_add_subregion_overlap(pci_dev-bus-address_space,
+PCIIORegion *r = pci_dev-io_regions[region_num];
+
+memory_region_add_subregion_overlap(r-address_space,
 addr,
-pci_dev-io_regions[region_num].memory,
+r-memory,
 1);
 }
 
@@ -953,9 +955,13 @@ void pci_register_bar_region(PCIDevice *pci_dev, int 
region_num,
  uint8_t attr, MemoryRegion *memory)
 {
 pci_register_bar(pci_dev, region_num, memory_region_size(memory),
- PCI_BASE_ADDRESS_SPACE_MEMORY | attr,
+ attr,
  pci_simple_bar_mapfunc_region);
 pci_dev-io_regions[region_num].memory = memory;
+pci_dev-io_regions[region_num].address_space
+= attr  PCI_BASE_ADDRESS_SPACE_IO
+? pci_dev-bus-address_space_io
+: pci_dev-bus-address_space_mem;
 }
 
 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
@@ -1090,7 +1096,9 @@ static void pci_update_mappings(PCIDevice *d)
 
 /* now do the real mapping */
 if (r-addr != PCI_BAR_UNMAPPED) {
-if (r-type  PCI_BASE_ADDRESS_SPACE_IO) {
+if (r-memory) {
+memory_region_del_subregion(r-address_space, r-memory);
+} else if (r-type  PCI_BASE_ADDRESS_SPACE_IO) {
 int class;
 /* NOTE: specific hack for IDE in PC case:
only one byte must be mapped. */
@@ -1101,16 +1109,11 @@ static void pci_update_mappings(PCIDevice *d)
 isa_unassign_ioport(r-addr, r-filtered_size);
 }
 } else {
-if (r-memory) {
-memory_region_del_subregion(d-bus-address_space,
-r-memory);
-} else {
-cpu_register_physical_memory(pci_to_cpu_addr(d-bus,
- r-addr),
- r-filtered_size,
- IO_MEM_UNASSIGNED);
-qemu_unregister_coalesced_mmio(r-addr, r-filtered_size);
-}
+cpu_register_physical_memory(pci_to_cpu_addr(d-bus,
+ r-addr),
+ r-filtered_size,
+ IO_MEM_UNASSIGNED);
+qemu_unregister_coalesced_mmio(r-addr, r-filtered_size);
 }
 }
 r-addr = new_addr;
diff --git a/hw/pci.h b/hw/pci.h
index 45b30fa..928e96c 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -95,6 +95,7 @@ typedef struct PCIIORegion {
 PCIMapIORegionFunc *map_func;
 ram_addr_t ram_addr;
 MemoryRegion *memory;
+MemoryRegion *address_space;
 } PCIIORegion;
 
 #define PCI_ROM_SLOT 6
diff --git a/hw/pci_internals.h b/hw/pci_internals.h
index c3a463a..c7fd23d 100644
---

[PATCH v3 05/39] cirrus: simplify mmio BAR access functions

Make use of the memory API's ability to satisfy multi-byte accesses via
multiple single-byte accesses.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/cirrus_vga.c |   78 +-
 1 files changed, 8 insertions(+), 70 deletions(-)

diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index d1475dd..6e1aa75 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2828,12 +2828,11 @@ static void cirrus_vga_ioport_write(void *opaque, 
uint32_t addr, uint32_t val)
  *
  ***/
 
-static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
 {
 CirrusVGAState *s = opaque;
 
-addr = CIRRUS_PNPMMIO_SIZE - 1;
-
 if (addr = 0x100) {
 return cirrus_mmio_blt_read(s, addr - 0x100);
 } else {
@@ -2841,33 +2840,11 @@ static uint32_t cirrus_mmio_readb(void *opaque, 
target_phys_addr_t addr)
 }
 }
 
-static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_mmio_readb(opaque, addr);
-v |= cirrus_mmio_readb(opaque, addr + 1)  8;
-return v;
-}
-
-static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_mmio_readb(opaque, addr);
-v |= cirrus_mmio_readb(opaque, addr + 1)  8;
-v |= cirrus_mmio_readb(opaque, addr + 2)  16;
-v |= cirrus_mmio_readb(opaque, addr + 3)  24;
-return v;
-}
-
-static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
-  uint32_t val)
+static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
+  uint64_t val, unsigned size)
 {
 CirrusVGAState *s = opaque;
 
-addr = CIRRUS_PNPMMIO_SIZE - 1;
-
 if (addr = 0x100) {
cirrus_mmio_blt_write(s, addr - 0x100, val);
 } else {
@@ -2875,53 +2852,14 @@ static void cirrus_mmio_writeb(void *opaque, 
target_phys_addr_t addr,
 }
 }
 
-static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
-  uint32_t val)
-{
-cirrus_mmio_writeb(opaque, addr, val  0xff);
-cirrus_mmio_writeb(opaque, addr + 1, (val  8)  0xff);
-}
-
-static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
-  uint32_t val)
-{
-cirrus_mmio_writeb(opaque, addr, val  0xff);
-cirrus_mmio_writeb(opaque, addr + 1, (val  8)  0xff);
-cirrus_mmio_writeb(opaque, addr + 2, (val  16)  0xff);
-cirrus_mmio_writeb(opaque, addr + 3, (val  24)  0xff);
-}
-
-
-static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
- unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_mmio_readb(s, addr);
-case 2: return cirrus_mmio_readw(s, addr);
-case 4: return cirrus_mmio_readl(s, addr);
-default: abort();
-}
-};
-
-static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
-  uint64_t data, unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_mmio_writeb(s, addr, data);
-case 2: return cirrus_mmio_writew(s, addr, data);
-case 4: return cirrus_mmio_writel(s, addr, data);
-default: abort();
-}
-};
-
 static const MemoryRegionOps cirrus_mmio_io_ops = {
 .read = cirrus_mmio_read,
 .write = cirrus_mmio_write,
 .endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
 };
 
 /* load/save state */
-- 
1.7.5.3

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[PATCH v3 07/39] cirrus: simplify vga window mmio access functions

Make use of the memory API's ability to satisfy multi-byte accesses via
multiple single-byte accesses.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/cirrus_vga.c |   79 +++---
 1 files changed, 11 insertions(+), 68 deletions(-)

diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index b8a51b4..92696d9 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -1955,7 +1955,9 @@ static void 
cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
  *
  ***/
 
-static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t cirrus_vga_mem_read(void *opaque,
+target_phys_addr_t addr,
+uint32_t size)
 {
 CirrusVGAState *s = opaque;
 unsigned bank_index;
@@ -1966,8 +1968,6 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, 
target_phys_addr_t addr)
return vga_mem_readb(s, addr);
 }
 
-addr = 0x1;
-
 if (addr  0x1) {
/* XXX handle bitblt */
/* video memory */
@@ -1999,28 +1999,10 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, 
target_phys_addr_t addr)
 return val;
 }
 
-static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_vga_mem_readb(opaque, addr);
-v |= cirrus_vga_mem_readb(opaque, addr + 1)  8;
-return v;
-}
-
-static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_vga_mem_readb(opaque, addr);
-v |= cirrus_vga_mem_readb(opaque, addr + 1)  8;
-v |= cirrus_vga_mem_readb(opaque, addr + 2)  16;
-v |= cirrus_vga_mem_readb(opaque, addr + 3)  24;
-return v;
-}
-
-static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
-  uint32_t mem_value)
+static void cirrus_vga_mem_write(void *opaque,
+ target_phys_addr_t addr,
+ uint64_t mem_value,
+ uint32_t size)
 {
 CirrusVGAState *s = opaque;
 unsigned bank_index;
@@ -2032,8 +2014,6 @@ static void cirrus_vga_mem_writeb(void *opaque, 
target_phys_addr_t addr,
 return;
 }
 
-addr = 0x1;
-
 if (addr  0x1) {
if (s-cirrus_srcptr != s-cirrus_srcptr_end) {
/* bitblt */
@@ -2083,51 +2063,14 @@ static void cirrus_vga_mem_writeb(void *opaque, 
target_phys_addr_t addr,
 }
 }
 
-static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, 
uint32_t val)
-{
-cirrus_vga_mem_writeb(opaque, addr, val  0xff);
-cirrus_vga_mem_writeb(opaque, addr + 1, (val  8)  0xff);
-}
-
-static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, 
uint32_t val)
-{
-cirrus_vga_mem_writeb(opaque, addr, val  0xff);
-cirrus_vga_mem_writeb(opaque, addr + 1, (val  8)  0xff);
-cirrus_vga_mem_writeb(opaque, addr + 2, (val  16)  0xff);
-cirrus_vga_mem_writeb(opaque, addr + 3, (val  24)  0xff);
-}
-
-static uint64_t cirrus_vga_mem_read(void *opaque,
-target_phys_addr_t addr,
-uint32_t size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_vga_mem_readb(s, addr);
-case 2: return cirrus_vga_mem_readw(s, addr);
-case 4: return cirrus_vga_mem_readl(s, addr);
-default: abort();
-}
-}
-
-static void cirrus_vga_mem_write(void *opaque, target_phys_addr_t addr,
- uint64_t data, unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_vga_mem_writeb(s, addr, data);
-case 2: return cirrus_vga_mem_writew(s, addr, data);
-case 4: return cirrus_vga_mem_writel(s, addr, data);
-default: abort();
-}
-};
-
 static const MemoryRegionOps cirrus_vga_mem_ops = {
 .read = cirrus_vga_mem_read,
 .write = cirrus_vga_mem_write,
 .endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
 };
 
 /***
-- 
1.7.5.3

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[PATCH v3 22/39] intel-hda: convert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/intel-hda.c |   35 +++
 1 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index 5a2bc3a..1e4c71e 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -177,7 +177,7 @@ struct IntelHDAState {
 IntelHDAStream st[8];
 
 /* state */
-int mmio_addr;
+MemoryRegion mmio;
 uint32_t rirb_count;
 int64_t wall_base_ns;
 
@@ -1084,16 +1084,20 @@ static uint32_t intel_hda_mmio_readl(void *opaque, 
target_phys_addr_t addr)
 return intel_hda_reg_read(d, reg, 0x);
 }
 
-static CPUReadMemoryFunc * const intel_hda_mmio_read[3] = {
-intel_hda_mmio_readb,
-intel_hda_mmio_readw,
-intel_hda_mmio_readl,
-};
-
-static CPUWriteMemoryFunc * const intel_hda_mmio_write[3] = {
-intel_hda_mmio_writeb,
-intel_hda_mmio_writew,
-intel_hda_mmio_writel,
+static const MemoryRegionOps intel_hda_mmio_ops = {
+.old_mmio = {
+.read = {
+intel_hda_mmio_readb,
+intel_hda_mmio_readw,
+intel_hda_mmio_readl,
+},
+.write = {
+intel_hda_mmio_writeb,
+intel_hda_mmio_writew,
+intel_hda_mmio_writel,
+},
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
 };
 
 /* - */
@@ -1130,10 +1134,9 @@ static int intel_hda_init(PCIDevice *pci)
 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
 conf[0x40] = 0x01;
 
-d-mmio_addr = cpu_register_io_memory(intel_hda_mmio_read,
-  intel_hda_mmio_write, d,
-  DEVICE_NATIVE_ENDIAN);
-pci_register_bar_simple(d-pci, 0, 0x4000, 0, d-mmio_addr);
+memory_region_init_io(d-mmio, intel_hda_mmio_ops, d,
+  intel-hda, 0x4000);
+pci_register_bar_region(d-pci, 0, 0, d-mmio);
 if (d-msi) {
 msi_init(d-pci, 0x50, 1, true, false);
 }
@@ -1149,7 +1152,7 @@ static int intel_hda_exit(PCIDevice *pci)
 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
 
 msi_uninit(d-pci);
-cpu_unregister_io_memory(d-mmio_addr);
+memory_region_destroy(d-mmio);
 return 0;
 }
 
-- 
1.7.5.3

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[PATCH v3 15/39] e1000: convert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/e1000.c |  114 +--
 1 files changed, 48 insertions(+), 66 deletions(-)

diff --git a/hw/e1000.c b/hw/e1000.c
index 96d84f9..dfc082b 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -82,7 +82,8 @@ typedef struct E1000State_st {
 PCIDevice dev;
 NICState *nic;
 NICConf conf;
-int mmio_index;
+MemoryRegion mmio;
+MemoryRegion io;
 
 uint32_t mac_reg[0x8000];
 uint16_t phy_reg[0x20];
@@ -151,14 +152,6 @@ static const char phy_regcap[0x20] = {
 };
 
 static void
-ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
-   pcibus_t size, int type)
-{
-DBGOUT(IO, e1000_ioport_map addr=0x%04FMT_PCIBUS
-size=0x%08FMT_PCIBUS\n, addr, size);
-}
-
-static void
 set_interrupt_cause(E1000State *s, int index, uint32_t val)
 {
 if (val)
@@ -905,7 +898,8 @@ static void (*macreg_writeops[])(E1000State *, int, 
uint32_t) = {
 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
 
 static void
-e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+ unsigned size)
 {
 E1000State *s = opaque;
 unsigned int index = (addr  0x1)  2;
@@ -913,31 +907,15 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr, 
uint32_t val)
 if (index  NWRITEOPS  macreg_writeops[index]) {
 macreg_writeops[index](s, index, val);
 } else if (index  NREADOPS  macreg_readops[index]) {
-DBGOUT(MMIO, e1000_mmio_writel RO %x: 0x%04x\n, index2, val);
+DBGOUT(MMIO, e1000_mmio_writel RO %x: 0x%04PRIx64\n, index2, 
val);
 } else {
-DBGOUT(UNKNOWN, MMIO unknown write addr=0x%08x,val=0x%08x\n,
+DBGOUT(UNKNOWN, MMIO unknown write addr=0x%08x,val=0x%08PRIx64\n,
index2, val);
 }
 }
 
-static void
-e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-// emulate hw without byte enables: no RMW
-e1000_mmio_writel(opaque, addr  ~3,
-  (val  0x)  (8*(addr  3)));
-}
-
-static void
-e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-// emulate hw without byte enables: no RMW
-e1000_mmio_writel(opaque, addr  ~3,
-  (val  0xff)  (8*(addr  3)));
-}
-
-static uint32_t
-e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t
+e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
 {
 E1000State *s = opaque;
 unsigned int index = (addr  0x1)  2;
@@ -950,20 +928,39 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
 return 0;
 }
 
-static uint32_t
-e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
+static const MemoryRegionOps e1000_mmio_ops = {
+.read = e1000_mmio_read,
+.write = e1000_mmio_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
+
+static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
+  unsigned size)
 {
-return ((e1000_mmio_readl(opaque, addr  ~3)) 
-(8 * (addr  3)))  0xff;
+E1000State *s = opaque;
+
+(void)s;
+return 0;
 }
 
-static uint32_t
-e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
+static void e1000_io_write(void *opaque, target_phys_addr_t addr,
+   uint64_t val, unsigned size)
 {
-return ((e1000_mmio_readl(opaque, addr  ~3)) 
-(8 * (addr  3)))  0x;
+E1000State *s = opaque;
+
+(void)s;
 }
 
+static const MemoryRegionOps e1000_io_ops = {
+.read = e1000_io_read,
+.write = e1000_io_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
 static bool is_version_1(void *opaque, int version_id)
 {
 return version_id == 1;
@@ -1083,36 +1080,22 @@ static const uint32_t mac_reg_init[] = {
 
 /* PCI interface */
 
-static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
-e1000_mmio_writeb, e1000_mmio_writew,  e1000_mmio_writel
-};
-
-static CPUReadMemoryFunc * const e1000_mmio_read[] = {
-e1000_mmio_readb,  e1000_mmio_readw,   e1000_mmio_readl
-};
-
 static void
-e1000_mmio_map(PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
+e1000_mmio_setup(E1000State *d)
 {
-E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
 int i;
 const uint32_t excluded_regs[] = {
 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
 };
 
-
-DBGOUT(MMIO, e1000_mmio_map addr=0x%08FMT_PCIBUS 0x%08FMT_PCIBUS\n,
-   addr, size);
-
-cpu_register_physical_memory(addr, PNPMMIO_SIZE, d-mmio_index);
-qemu_register_coalesced_mmio(addr, excluded_regs[0]);
-
+memory_region_init_io(d-mmio, e1000_mmio_ops, d, e1000-mmio,
+

[PATCH v3 11/39] pci: pass I/O address space to new PCI bus

This lets us register BARs in the I/O address space.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/apb_pci.c   |1 +
 hw/bonito.c|1 +
 hw/grackle_pci.c   |8 ++--
 hw/gt64xxx.c   |4 +++-
 hw/pc.h|4 +++-
 hw/pc_piix.c   |6 +-
 hw/pci.c   |   18 --
 hw/pci.h   |   10 +++---
 hw/piix_pci.c  |   14 +-
 hw/ppc4xx_pci.c|1 +
 hw/ppc_mac.h   |   11 ---
 hw/ppc_newworld.c  |4 ++--
 hw/ppc_oldworld.c  |4 +++-
 hw/ppc_prep.c  |2 +-
 hw/ppce500_pci.c   |7 ---
 hw/prep_pci.c  |8 ++--
 hw/prep_pci.h  |4 +++-
 hw/sh_pci.c|4 +++-
 hw/unin_pci.c  |   16 
 hw/versatile_pci.c |2 +-
 20 files changed, 91 insertions(+), 38 deletions(-)

diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 8b9939c..1638226 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -348,6 +348,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
 d-bus = pci_register_bus(d-busdev.qdev, pci,
  pci_apb_set_irq, pci_pbm_map_irq, d,
  get_system_memory(),
+ get_system_io(),
  0, 32);
 pci_bus_set_mem_base(d-bus, mem_base);
 
diff --git a/hw/bonito.c b/hw/bonito.c
index 5f62dda..8708e95 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -775,6 +775,7 @@ PCIBus *bonito_init(qemu_irq *pic)
 pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev));
 b = pci_register_bus(pcihost-busdev.qdev, pci, pci_bonito_set_irq,
  pci_bonito_map_irq, pic, get_system_memory(),
+ get_system_io(),
  0x28, 32);
 pcihost-bus = b;
 qdev_init_nofail(dev);
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index da67cf9..9a823e1 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -62,7 +62,8 @@ static void pci_grackle_reset(void *opaque)
 }
 
 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
- MemoryRegion *address_space)
+ MemoryRegion *address_space_mem,
+ MemoryRegion *address_space_io)
 {
 DeviceState *dev;
 SysBusDevice *s;
@@ -75,7 +76,10 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
 d-host_state.bus = pci_register_bus(d-busdev.qdev, pci,
  pci_grackle_set_irq,
  pci_grackle_map_irq,
- pic, address_space, 0, 4);
+ pic,
+ address_space_mem,
+ address_space_io,
+ 0, 4);
 
 pci_create_simple(d-host_state.bus, 0, grackle);
 
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 65e63dd..d541558 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -1093,7 +1093,9 @@ PCIBus *gt64120_register(qemu_irq *pic)
 d = FROM_SYSBUS(GT64120State, s);
 d-pci.bus = pci_register_bus(d-busdev.qdev, pci,
   gt64120_pci_set_irq, gt64120_pci_map_irq,
-  pic, get_system_memory(),
+  pic,
+  get_system_memory(),
+  get_system_io(),
   PCI_DEVFN(18, 0), 4);
 d-ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d,
DEVICE_NATIVE_ENDIAN);
diff --git a/hw/pc.h b/hw/pc.h
index a2de0fe..ec34db7 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -179,7 +179,9 @@ struct PCII440FXState;
 typedef struct PCII440FXState PCII440FXState;
 
 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
-qemu_irq *pic, MemoryRegion *address_space,
+qemu_irq *pic,
+MemoryRegion *address_space_mem,
+MemoryRegion *address_space_io,
 ram_addr_t ram_size);
 void i440fx_init_memory_mappings(PCII440FXState *d);
 
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index c0a2abe..7dd5008 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -69,6 +69,7 @@ static void ioapic_init(IsaIrqState *isa_irq_state)
 
 /* PC hardware initialisation */
 static void pc_init1(MemoryRegion *system_memory,
+ MemoryRegion *system_io,
  ram_addr_t ram_size,
  const char *boot_device,
  const char *kernel_filename,
@@ -129,7 +130,7 @@ static void pc_init1(MemoryRegion *system_memory,
 
 if (pci_enabled) {
 pci_bus = i440fx_init(i440fx_state, piix3_devfn, isa_irq,
-  system_memory, ram_size);
+

[PATCH v3 09/39] cirrus: simplify linear framebuffer access functions

Make use of the memory API's ability to satisfy multi-byte accesses via
multiple single-byte accesses.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/cirrus_vga.c |   74 ++-
 1 files changed, 8 insertions(+), 66 deletions(-)

diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 3db15bf..15ccf4a 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2249,7 +2249,8 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, 
uint8_t *d1, int scr_y)
  *
  ***/
 
-static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
+   unsigned size)
 {
 CirrusVGAState *s = opaque;
 uint32_t ret;
@@ -2277,28 +2278,8 @@ static uint32_t cirrus_linear_readb(void *opaque, 
target_phys_addr_t addr)
 return ret;
 }
 
-static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_linear_readb(opaque, addr);
-v |= cirrus_linear_readb(opaque, addr + 1)  8;
-return v;
-}
-
-static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
-{
-uint32_t v;
-
-v = cirrus_linear_readb(opaque, addr);
-v |= cirrus_linear_readb(opaque, addr + 1)  8;
-v |= cirrus_linear_readb(opaque, addr + 2)  16;
-v |= cirrus_linear_readb(opaque, addr + 3)  24;
-return v;
-}
-
-static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
-uint32_t val)
+static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
+uint64_t val, unsigned size)
 {
 CirrusVGAState *s = opaque;
 unsigned mode;
@@ -2338,49 +2319,6 @@ static void cirrus_linear_writeb(void *opaque, 
target_phys_addr_t addr,
 }
 }
 
-static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-cirrus_linear_writeb(opaque, addr, val  0xff);
-cirrus_linear_writeb(opaque, addr + 1, (val  8)  0xff);
-}
-
-static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-cirrus_linear_writeb(opaque, addr, val  0xff);
-cirrus_linear_writeb(opaque, addr + 1, (val  8)  0xff);
-cirrus_linear_writeb(opaque, addr + 2, (val  16)  0xff);
-cirrus_linear_writeb(opaque, addr + 3, (val  24)  0xff);
-}
-
-
-static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
-   unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_linear_readb(s, addr);
-case 2: return cirrus_linear_readw(s, addr);
-case 4: return cirrus_linear_readl(s, addr);
-default: abort();
-}
-}
-
-static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
-uint64_t data, unsigned size)
-{
-CirrusVGAState *s = opaque;
-
-switch (size) {
-case 1: return cirrus_linear_writeb(s, addr, data);
-case 2: return cirrus_linear_writew(s, addr, data);
-case 4: return cirrus_linear_writel(s, addr, data);
-default: abort();
-}
-}
-
 /***
  *
  *  system to screen memory access
@@ -2860,6 +2798,10 @@ static const MemoryRegionOps cirrus_linear_io_ops = {
 .read = cirrus_linear_read,
 .write = cirrus_linear_write,
 .endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
 };
 
 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
-- 
1.7.5.3

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[PATCH v3 21/39] ahci: convert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/ide/ahci.c |   31 +--
 hw/ide/ahci.h |2 +-
 hw/ide/ich.c  |3 +--
 3 files changed, 15 insertions(+), 21 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 1f008a3..e207ca0 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -276,12 +276,12 @@ static void  ahci_port_write(AHCIState *s, int port, int 
offset, uint32_t val)
 }
 }
 
-static uint32_t ahci_mem_readl(void *ptr, target_phys_addr_t addr)
+static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr,
+  unsigned size)
 {
-AHCIState *s = ptr;
+AHCIState *s = opaque;
 uint32_t val = 0;
 
-addr = addr  0xfff;
 if (addr  AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
 switch (addr) {
 case HOST_CAP:
@@ -314,10 +314,10 @@ static uint32_t ahci_mem_readl(void *ptr, 
target_phys_addr_t addr)
 
 
 
-static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
+static void ahci_mem_write(void *opaque, target_phys_addr_t addr,
+   uint64_t val, unsigned size)
 {
-AHCIState *s = ptr;
-addr = addr  0xfff;
+AHCIState *s = opaque;
 
 /* Only aligned reads are allowed on AHCI */
 if (addr  3) {
@@ -364,16 +364,10 @@ static void ahci_mem_writel(void *ptr, target_phys_addr_t 
addr, uint32_t val)
 
 }
 
-static CPUReadMemoryFunc * const ahci_readfn[3]={
-ahci_mem_readl,
-ahci_mem_readl,
-ahci_mem_readl
-};
-
-static CPUWriteMemoryFunc * const ahci_writefn[3]={
-ahci_mem_writel,
-ahci_mem_writel,
-ahci_mem_writel
+static MemoryRegionOps ahci_mem_ops = {
+.read = ahci_mem_read,
+.write = ahci_mem_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static void ahci_reg_init(AHCIState *s)
@@ -1131,8 +1125,8 @@ void ahci_init(AHCIState *s, DeviceState *qdev, int ports)
 s-ports = ports;
 s-dev = qemu_mallocz(sizeof(AHCIDevice) * ports);
 ahci_reg_init(s);
-s-mem = cpu_register_io_memory(ahci_readfn, ahci_writefn, s,
-DEVICE_LITTLE_ENDIAN);
+/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
+memory_region_init_io(s-mem, ahci_mem_ops, s, ahci, 0x1000);
 irqs = qemu_allocate_irqs(ahci_irq_set, s, s-ports);
 
 for (i = 0; i  s-ports; i++) {
@@ -1151,6 +1145,7 @@ void ahci_init(AHCIState *s, DeviceState *qdev, int ports)
 
 void ahci_uninit(AHCIState *s)
 {
+memory_region_destroy(s-mem);
 qemu_free(s-dev);
 }
 
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index dc86951..e456193 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -289,7 +289,7 @@ struct AHCIDevice {
 typedef struct AHCIState {
 AHCIDevice *dev;
 AHCIControlRegs control_regs;
-int mem;
+MemoryRegion mem;
 int ports;
 qemu_irq irq;
 } AHCIState;
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index d241ea8..698b5f6 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -98,8 +98,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
 msi_init(dev, 0x50, 1, true, false);
 d-ahci.irq = d-card.irq[0];
 
-/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
-pci_register_bar_simple(d-card, 5, 0x1000, 0, d-ahci.mem);
+pci_register_bar_region(d-card, 5, 0, d-ahci.mem);
 
 return 0;
 }
-- 
1.7.5.3

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[PATCH v3 27/39] i6300esb: convert to memory API

Also add missing destructor.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/wdt_i6300esb.c |   43 +--
 1 files changed, 29 insertions(+), 14 deletions(-)

diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c
index 53786ce..abc2e17 100644
--- a/hw/wdt_i6300esb.c
+++ b/hw/wdt_i6300esb.c
@@ -66,6 +66,7 @@
 /* Device state. */
 struct I6300State {
 PCIDevice dev;
+MemoryRegion io_mem;
 
 int reboot_enabled; /* Reboot on timer expiry.  The real action
  * performed depends on the -watchdog-action
@@ -355,6 +356,22 @@ static void i6300esb_mem_writel(void *vp, 
target_phys_addr_t addr, uint32_t val)
 }
 }
 
+static const MemoryRegionOps i6300esb_ops = {
+.old_mmio = {
+.read = {
+i6300esb_mem_readb,
+i6300esb_mem_readw,
+i6300esb_mem_readl,
+},
+.write = {
+i6300esb_mem_writeb,
+i6300esb_mem_writew,
+i6300esb_mem_writel,
+},
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
 static const VMStateDescription vmstate_i6300esb = {
 .name = i6300esb_wdt,
 .version_id = sizeof(I6300State),
@@ -381,31 +398,28 @@ static const VMStateDescription vmstate_i6300esb = {
 static int i6300esb_init(PCIDevice *dev)
 {
 I6300State *d = DO_UPCAST(I6300State, dev, dev);
-int io_mem;
-static CPUReadMemoryFunc * const mem_read[3] = {
-i6300esb_mem_readb,
-i6300esb_mem_readw,
-i6300esb_mem_readl,
-};
-static CPUWriteMemoryFunc * const mem_write[3] = {
-i6300esb_mem_writeb,
-i6300esb_mem_writew,
-i6300esb_mem_writel,
-};
 
 i6300esb_debug(I6300State = %p\n, d);
 
 d-timer = qemu_new_timer_ns(vm_clock, i6300esb_timer_expired, d);
 d-previous_reboot_flag = 0;
 
-io_mem = cpu_register_io_memory(mem_read, mem_write, d,
-DEVICE_NATIVE_ENDIAN);
-pci_register_bar_simple(d-dev, 0, 0x10, 0, io_mem);
+memory_region_init_io(d-io_mem, i6300esb_ops, d, i6300esb, 0x10);
+pci_register_bar_region(d-dev, 0, 0, d-io_mem);
 /* qemu_register_coalesced_mmio (addr, 0x10); ? */
 
 return 0;
 }
 
+static int i6300esb_exit(PCIDevice *dev)
+{
+I6300State *d = DO_UPCAST(I6300State, dev, dev);
+
+memory_region_destroy(d-io_mem);
+
+return 0;
+}
+
 static WatchdogTimerModel model = {
 .wdt_name = i6300esb,
 .wdt_description = Intel 6300ESB,
@@ -419,6 +433,7 @@ static PCIDeviceInfo i6300esb_info = {
 .config_read  = i6300esb_config_read,
 .config_write = i6300esb_config_write,
 .init = i6300esb_init,
+.exit = i6300esb_exit,
 .vendor_id= PCI_VENDOR_ID_INTEL,
 .device_id= PCI_DEVICE_ID_INTEL_ESB_9,
 .class_id = PCI_CLASS_SYSTEM_OTHER,
-- 
1.7.5.3

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[PATCH v3 19/39] ivshmem: convert to memory API

excluding msix.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/ivshmem.c |  148 --
 1 files changed, 50 insertions(+), 98 deletions(-)

diff --git a/hw/ivshmem.c b/hw/ivshmem.c
index 3055dd2..f80e7b6 100644
--- a/hw/ivshmem.c
+++ b/hw/ivshmem.c
@@ -56,11 +56,15 @@ typedef struct IVShmemState {
 
 CharDriverState **eventfd_chr;
 CharDriverState *server_chr;
-int ivshmem_mmio_io_addr;
+MemoryRegion ivshmem_mmio;
 
 pcibus_t mmio_addr;
-pcibus_t shm_pci_addr;
-uint64_t ivshmem_offset;
+/* We might need to register the BAR before we actually have the memory.
+ * So prepare a container MemoryRegion for the BAR immediately and
+ * add a subregion when we have the memory.
+ */
+MemoryRegion bar;
+MemoryRegion ivshmem;
 uint64_t ivshmem_size; /* size of shared memory region */
 int shm_fd; /* shared memory file descriptor */
 
@@ -96,23 +100,6 @@ static inline bool is_power_of_two(uint64_t x) {
 return (x  (x - 1)) == 0;
 }
 
-static void ivshmem_map(PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
-{
-IVShmemState *s = DO_UPCAST(IVShmemState, dev, pci_dev);
-
-s-shm_pci_addr = addr;
-
-if (s-ivshmem_offset  0) {
-cpu_register_physical_memory(s-shm_pci_addr, s-ivshmem_size,
-s-ivshmem_offset);
-}
-
-IVSHMEM_DPRINTF(guest pci addr = % FMT_PCIBUS , guest h/w addr = %
-PRIu64 , size = % FMT_PCIBUS \n, addr, s-ivshmem_offset, size);
-
-}
-
 /* accessing registers - based on rtl8139 */
 static void ivshmem_update_irq(IVShmemState *s, int val)
 {
@@ -168,15 +155,8 @@ static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)
 return ret;
 }
 
-static void ivshmem_io_writew(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-
-IVSHMEM_DPRINTF(We shouldn't be writing words\n);
-}
-
-static void ivshmem_io_writel(void *opaque, target_phys_addr_t addr,
-uint32_t val)
+static void ivshmem_io_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
 {
 IVShmemState *s = opaque;
 
@@ -219,20 +199,8 @@ static void ivshmem_io_writel(void *opaque, 
target_phys_addr_t addr,
 }
 }
 
-static void ivshmem_io_writeb(void *opaque, target_phys_addr_t addr,
-uint32_t val)
-{
-IVSHMEM_DPRINTF(We shouldn't be writing bytes\n);
-}
-
-static uint32_t ivshmem_io_readw(void *opaque, target_phys_addr_t addr)
-{
-
-IVSHMEM_DPRINTF(We shouldn't be reading words\n);
-return 0;
-}
-
-static uint32_t ivshmem_io_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t ivshmem_io_read(void *opaque, target_phys_addr_t addr,
+unsigned size)
 {
 
 IVShmemState *s = opaque;
@@ -265,23 +233,14 @@ static uint32_t ivshmem_io_readl(void *opaque, 
target_phys_addr_t addr)
 return ret;
 }
 
-static uint32_t ivshmem_io_readb(void *opaque, target_phys_addr_t addr)
-{
-IVSHMEM_DPRINTF(We shouldn't be reading bytes\n);
-
-return 0;
-}
-
-static CPUReadMemoryFunc * const ivshmem_mmio_read[3] = {
-ivshmem_io_readb,
-ivshmem_io_readw,
-ivshmem_io_readl,
-};
-
-static CPUWriteMemoryFunc * const ivshmem_mmio_write[3] = {
-ivshmem_io_writeb,
-ivshmem_io_writew,
-ivshmem_io_writel,
+static const MemoryRegionOps ivshmem_mmio_ops = {
+.read = ivshmem_io_read,
+.write = ivshmem_io_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
 };
 
 static void ivshmem_receive(void *opaque, const uint8_t *buf, int size)
@@ -371,12 +330,12 @@ static void create_shared_memory_BAR(IVShmemState *s, int 
fd) {
 
 ptr = mmap(0, s-ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
 
-s-ivshmem_offset = qemu_ram_alloc_from_ptr(s-dev.qdev, ivshmem.bar2,
-s-ivshmem_size, ptr);
+memory_region_init_ram_ptr(s-ivshmem, s-dev.qdev, ivshmem.bar2,
+   s-ivshmem_size, ptr);
+memory_region_add_subregion(s-bar, 0, s-ivshmem);
 
 /* region for shared memory */
-pci_register_bar(s-dev, 2, s-ivshmem_size,
-PCI_BASE_ADDRESS_SPACE_MEMORY, ivshmem_map);
+pci_register_bar_region(s-dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, 
s-bar);
 }
 
 static void close_guest_eventfds(IVShmemState *s, int posn)
@@ -401,8 +360,12 @@ static void setup_ioeventfds(IVShmemState *s) {
 
 for (i = 0; i = s-max_peer; i++) {
 for (j = 0; j  s-peers[i].nb_eventfds; j++) {
-kvm_set_ioeventfd_mmio_long(s-peers[i].eventfds[j],
-

[PATCH v3 29/39] sun4u: convert to memory API

fixes memory leak on repeated BAR map/unmap

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/sun4u.c |   55 +--
 1 files changed, 25 insertions(+), 30 deletions(-)

diff --git a/hw/sun4u.c b/hw/sun4u.c
index d7dcaf0..74a06a8 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -91,6 +91,12 @@ struct hwdef {
 uint64_t console_serial_base;
 };
 
+typedef struct EbusState {
+PCIDevice pci_dev;
+MemoryRegion bar0;
+MemoryRegion bar1;
+} EbusState;
+
 int DMA_get_channel_mode (int nchan)
 {
 return 0;
@@ -518,21 +524,6 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 }
 }
 
-static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
-  pcibus_t addr, pcibus_t size, int type)
-{
-EBUS_DPRINTF(Mapping region %d registers at % FMT_PCIBUS \n,
- region_num, addr);
-switch (region_num) {
-case 0:
-isa_mmio_init(addr, 0x100);
-break;
-case 1:
-isa_mmio_init(addr, 0x80);
-break;
-}
-}
-
 static void dummy_isa_irq_handler(void *opaque, int n, int level)
 {
 }
@@ -549,27 +540,31 @@ pci_ebus_init(PCIBus *bus, int devfn)
 }
 
 static int
-pci_ebus_init1(PCIDevice *s)
+pci_ebus_init1(PCIDevice *pci_dev)
 {
-isa_bus_new(s-qdev);
+EbusState *s = container_of(pci_dev, EbusState, pci_dev);
+
+isa_bus_new(pci_dev-qdev);
 
-s-config[0x04] = 0x06; // command = bus master, pci mem
-s-config[0x05] = 0x00;
-s-config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
-s-config[0x07] = 0x03; // status = medium devsel
-s-config[0x09] = 0x00; // programming i/f
-s-config[0x0D] = 0x0a; // latency_timer
+pci_dev-config[0x04] = 0x06; // command = bus master, pci mem
+pci_dev-config[0x05] = 0x00;
+pci_dev-config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no 
error
+pci_dev-config[0x07] = 0x03; // status = medium devsel
+pci_dev-config[0x09] = 0x00; // programming i/f
+pci_dev-config[0x0D] = 0x0a; // latency_timer
 
-pci_register_bar(s, 0, 0x100, PCI_BASE_ADDRESS_SPACE_MEMORY,
-   ebus_mmio_mapfunc);
-pci_register_bar(s, 1, 0x80,  PCI_BASE_ADDRESS_SPACE_MEMORY,
-   ebus_mmio_mapfunc);
+isa_mmio_setup(s-bar0, 0x100);
+pci_register_bar_region(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
+s-bar0);
+isa_mmio_setup(s-bar1, 0x80);
+pci_register_bar_region(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
+s-bar1);
 return 0;
 }
 
 static PCIDeviceInfo ebus_info = {
 .qdev.name = ebus,
-.qdev.size = sizeof(PCIDevice),
+.qdev.size = sizeof(EbusState),
 .init = pci_ebus_init1,
 .vendor_id = PCI_VENDOR_ID_SUN,
 .device_id = PCI_DEVICE_ID_SUN_EBUS,
-- 
1.7.5.3

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[PATCH v3 25/39] ne2000: convert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/ne2000-isa.c |   14 +++---
 hw/ne2000.c |   77 +-
 hw/ne2000.h |8 +
 3 files changed, 59 insertions(+), 40 deletions(-)

diff --git a/hw/ne2000-isa.c b/hw/ne2000-isa.c
index e41dbba..ce7b365 100644
--- a/hw/ne2000-isa.c
+++ b/hw/ne2000-isa.c
@@ -61,24 +61,18 @@ static const VMStateDescription vmstate_isa_ne2000 = {
 }
 };
 
+#include exec-memory.h
+
 static int isa_ne2000_initfn(ISADevice *dev)
 {
 ISANE2000State *isa = DO_UPCAST(ISANE2000State, dev, dev);
 NE2000State *s = isa-ne2000;
 
-register_ioport_write(isa-iobase, 16, 1, ne2000_ioport_write, s);
-register_ioport_read(isa-iobase, 16, 1, ne2000_ioport_read, s);
+ne2000_setup_io(s, 0x20);
 isa_init_ioport_range(dev, isa-iobase, 16);
-
-register_ioport_write(isa-iobase + 0x10, 1, 1, ne2000_asic_ioport_write, 
s);
-register_ioport_read(isa-iobase + 0x10, 1, 1, ne2000_asic_ioport_read, s);
-register_ioport_write(isa-iobase + 0x10, 2, 2, ne2000_asic_ioport_write, 
s);
-register_ioport_read(isa-iobase + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 isa_init_ioport_range(dev, isa-iobase + 0x10, 2);
-
-register_ioport_write(isa-iobase + 0x1f, 1, 1, ne2000_reset_ioport_write, 
s);
-register_ioport_read(isa-iobase + 0x1f, 1, 1, ne2000_reset_ioport_read, 
s);
 isa_init_ioport(dev, isa-iobase + 0x1f);
+memory_region_add_subregion(get_system_io(), isa-iobase, s-io);
 
 isa_init_irq(dev, s-irq, isa-isairq);
 
diff --git a/hw/ne2000.c b/hw/ne2000.c
index f8acaae..5b76acf 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -297,7 +297,7 @@ ssize_t ne2000_receive(VLANClientState *nc, const uint8_t 
*buf, size_t size_)
 return size_;
 }
 
-void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 {
 NE2000State *s = opaque;
 int offset, page, index;
@@ -394,7 +394,7 @@ void ne2000_ioport_write(void *opaque, uint32_t addr, 
uint32_t val)
 }
 }
 
-uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
+static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 {
 NE2000State *s = opaque;
 int offset, page, ret;
@@ -544,7 +544,7 @@ static inline void ne2000_dma_update(NE2000State *s, int 
len)
 }
 }
 
-void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 {
 NE2000State *s = opaque;
 
@@ -564,7 +564,7 @@ void ne2000_asic_ioport_write(void *opaque, uint32_t addr, 
uint32_t val)
 }
 }
 
-uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
+static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 {
 NE2000State *s = opaque;
 int ret;
@@ -612,12 +612,12 @@ static uint32_t ne2000_asic_ioport_readl(void *opaque, 
uint32_t addr)
 return ret;
 }
 
-void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t 
val)
 {
 /* nothing to do (end of reset pulse) */
 }
 
-uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
+static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 {
 NE2000State *s = opaque;
 ne2000_reset(s);
@@ -676,27 +676,55 @@ static const VMStateDescription vmstate_pci_ne2000 = {
 }
 };
 
-/***/
-/* PCI NE2000 definitions */
+static uint64_t ne2000_read(void *opaque, target_phys_addr_t addr,
+unsigned size)
+{
+NE2000State *s = opaque;
 
-static void ne2000_map(PCIDevice *pci_dev, int region_num,
-   pcibus_t addr, pcibus_t size, int type)
+if (addr  0x10  size == 1) {
+return ne2000_ioport_read(s, addr);
+} else if (addr == 0x10) {
+if (size = 2) {
+return ne2000_asic_ioport_read(s, addr);
+} else {
+return ne2000_asic_ioport_readl(s, addr);
+}
+} else if (addr == 0x1f  size == 1) {
+return ne2000_reset_ioport_read(s, addr);
+}
+return ((uint64_t)1  (size * 8)) - 1;
+}
+
+static void ne2000_write(void *opaque, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
 {
-PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
-NE2000State *s = d-ne2000;
+NE2000State *s = opaque;
+
+if (addr  0x10  size == 1) {
+return ne2000_ioport_write(s, addr, data);
+} else if (addr == 0x10) {
+if (size = 2) {
+return ne2000_asic_ioport_write(s, addr, data);
+} else {
+return ne2000_asic_ioport_writel(s, addr, data);
+}
+} else if (addr == 0x1f  size == 1) {
+return ne2000_reset_ioport_write(s, addr, data);
+}
+}
 
-register_ioport_write(addr, 16, 1,

[PATCH v3 13/39] rtl8139: convert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/rtl8139.c |   72 ++---
 1 files changed, 38 insertions(+), 34 deletions(-)

diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index 5214b8c..dfbab90 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -474,7 +474,6 @@ typedef struct RTL8139State {
 
 NICState *nic;
 NICConf conf;
-int rtl8139_mmio_io_addr;
 
 /* C ring mode */
 uint32_t   currTxDesc;
@@ -506,6 +505,9 @@ typedef struct RTL8139State {
 QEMUTimer *timer;
 int64_t TimerExpire;
 
+MemoryRegion bar_io;
+MemoryRegion bar_mem;
+
 /* Support migration to/from old versions */
 int rtl8139_mmio_io_addr_dummy;
 } RTL8139State;
@@ -3283,7 +3285,7 @@ static void rtl8139_pre_save(void *opaque)
 rtl8139_set_next_tctr_time(s, current_time);
 s-TCTR = muldiv64(current_time - s-TCTR_base, PCI_FREQUENCY,
get_ticks_per_sec());
-s-rtl8139_mmio_io_addr_dummy = s-rtl8139_mmio_io_addr;
+s-rtl8139_mmio_io_addr_dummy = 0;
 }
 
 static const VMStateDescription vmstate_rtl8139 = {
@@ -3379,31 +3381,35 @@ static const VMStateDescription vmstate_rtl8139 = {
 /***/
 /* PCI RTL8139 definitions */
 
-static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
-   pcibus_t addr, pcibus_t size, int type)
-{
-RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
-
-register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
-register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb,  s);
-
-register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
-register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw,  s);
-
-register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
-register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl,  s);
-}
+static const MemoryRegionPortio rtl8139_portio[] = {
+{ 0, 0x100, 1, .read = rtl8139_ioport_readb, },
+{ 0, 0x100, 1, .write = rtl8139_ioport_writeb, },
+{ 0, 0x100, 2, .read = rtl8139_ioport_readw, },
+{ 0, 0x100, 2, .write = rtl8139_ioport_writew, },
+{ 0, 0x100, 4, .read = rtl8139_ioport_readl, },
+{ 0, 0x100, 4, .write = rtl8139_ioport_writel, },
+PORTIO_END
+};
 
-static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
-rtl8139_mmio_readb,
-rtl8139_mmio_readw,
-rtl8139_mmio_readl,
+static const MemoryRegionOps rtl8139_io_ops = {
+.old_portio = rtl8139_portio,
+.endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
-rtl8139_mmio_writeb,
-rtl8139_mmio_writew,
-rtl8139_mmio_writel,
+static const MemoryRegionOps rtl8139_mmio_ops = {
+.old_mmio = {
+.read = {
+rtl8139_mmio_readb,
+rtl8139_mmio_readw,
+rtl8139_mmio_readl,
+},
+.write = {
+rtl8139_mmio_writeb,
+rtl8139_mmio_writew,
+rtl8139_mmio_writel,
+},
+},
+.endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static void rtl8139_timer(void *opaque)
@@ -3432,7 +3438,8 @@ static int pci_rtl8139_uninit(PCIDevice *dev)
 {
 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
 
-cpu_unregister_io_memory(s-rtl8139_mmio_io_addr);
+memory_region_destroy(s-bar_io);
+memory_region_destroy(s-bar_mem);
 if (s-cplus_txbuffer) {
 qemu_free(s-cplus_txbuffer);
 s-cplus_txbuffer = NULL;
@@ -3462,15 +3469,12 @@ static int pci_rtl8139_init(PCIDevice *dev)
  * list bit in status register, and offset 0xdc seems unused. */
 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
 
-/* I/O handler for memory-mapped I/O */
-s-rtl8139_mmio_io_addr =
-cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
-   DEVICE_LITTLE_ENDIAN);
-
-pci_register_bar(s-dev, 0, 0x100,
-   PCI_BASE_ADDRESS_SPACE_IO,  rtl8139_ioport_map);
-
-pci_register_bar_simple(s-dev, 1, 0x100, 0, s-rtl8139_mmio_io_addr);
+memory_region_init_io(s-bar_io, rtl8139_io_ops, s, rtl8139, 0x100);
+memory_region_init_io(s-bar_mem, rtl8139_mmio_ops, s, rtl8139, 0x100);
+pci_register_bar_region(s-dev, 0, PCI_BASE_ADDRESS_SPACE_IO,
+s-bar_io);
+pci_register_bar_region(s-dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
+s-bar_mem);
 
 qemu_macaddr_default_if_unset(s-conf.macaddr);
 
-- 
1.7.5.3

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[PATCH v3 20/39] virtio-pci: convert to memory API

except msix.

[jan: fix build]

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/virtio-pci.c |   71 +++---
 hw/virtio-pci.h |2 +-
 2 files changed, 31 insertions(+), 42 deletions(-)

diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c
index ca1f12f..5d4c1be 100644
--- a/hw/virtio-pci.c
+++ b/hw/virtio-pci.c
@@ -161,7 +161,8 @@ static int 
virtio_pci_set_host_notifier_internal(VirtIOPCIProxy *proxy,
 {
 VirtQueue *vq = virtio_get_queue(proxy-vdev, n);
 EventNotifier *notifier = virtio_queue_get_host_notifier(vq);
-int r;
+int r = 0;
+
 if (assign) {
 r = event_notifier_init(notifier, 1);
 if (r  0) {
@@ -169,24 +170,11 @@ static int 
virtio_pci_set_host_notifier_internal(VirtIOPCIProxy *proxy,
  __func__, r);
 return r;
 }
-r = kvm_set_ioeventfd_pio_word(event_notifier_get_fd(notifier),
-   proxy-addr + VIRTIO_PCI_QUEUE_NOTIFY,
-   n, assign);
-if (r  0) {
-error_report(%s: unable to map ioeventfd: %d,
- __func__, r);
-event_notifier_cleanup(notifier);
-}
+memory_region_add_eventfd(proxy-bar, VIRTIO_PCI_QUEUE_NOTIFY, 2,
+  true, n, event_notifier_get_fd(notifier));
 } else {
-r = kvm_set_ioeventfd_pio_word(event_notifier_get_fd(notifier),
-   proxy-addr + VIRTIO_PCI_QUEUE_NOTIFY,
-   n, assign);
-if (r  0) {
-error_report(%s: unable to unmap ioeventfd: %d,
- __func__, r);
-return r;
-}
-
+memory_region_del_eventfd(proxy-bar, VIRTIO_PCI_QUEUE_NOTIFY, 2,
+  true, n, event_notifier_get_fd(notifier));
 /* Handle the race condition where the guest kicked and we deassigned
  * before we got around to handling the kick.
  */
@@ -423,7 +411,6 @@ static uint32_t virtio_pci_config_readb(void *opaque, 
uint32_t addr)
 {
 VirtIOPCIProxy *proxy = opaque;
 uint32_t config = VIRTIO_PCI_CONFIG(proxy-pci_dev);
-addr -= proxy-addr;
 if (addr  config)
 return virtio_ioport_read(proxy, addr);
 addr -= config;
@@ -434,7 +421,6 @@ static uint32_t virtio_pci_config_readw(void *opaque, 
uint32_t addr)
 {
 VirtIOPCIProxy *proxy = opaque;
 uint32_t config = VIRTIO_PCI_CONFIG(proxy-pci_dev);
-addr -= proxy-addr;
 if (addr  config)
 return virtio_ioport_read(proxy, addr);
 addr -= config;
@@ -445,7 +431,6 @@ static uint32_t virtio_pci_config_readl(void *opaque, 
uint32_t addr)
 {
 VirtIOPCIProxy *proxy = opaque;
 uint32_t config = VIRTIO_PCI_CONFIG(proxy-pci_dev);
-addr -= proxy-addr;
 if (addr  config)
 return virtio_ioport_read(proxy, addr);
 addr -= config;
@@ -456,7 +441,6 @@ static void virtio_pci_config_writeb(void *opaque, uint32_t 
addr, uint32_t val)
 {
 VirtIOPCIProxy *proxy = opaque;
 uint32_t config = VIRTIO_PCI_CONFIG(proxy-pci_dev);
-addr -= proxy-addr;
 if (addr  config) {
 virtio_ioport_write(proxy, addr, val);
 return;
@@ -469,7 +453,6 @@ static void virtio_pci_config_writew(void *opaque, uint32_t 
addr, uint32_t val)
 {
 VirtIOPCIProxy *proxy = opaque;
 uint32_t config = VIRTIO_PCI_CONFIG(proxy-pci_dev);
-addr -= proxy-addr;
 if (addr  config) {
 virtio_ioport_write(proxy, addr, val);
 return;
@@ -482,7 +465,6 @@ static void virtio_pci_config_writel(void *opaque, uint32_t 
addr, uint32_t val)
 {
 VirtIOPCIProxy *proxy = opaque;
 uint32_t config = VIRTIO_PCI_CONFIG(proxy-pci_dev);
-addr -= proxy-addr;
 if (addr  config) {
 virtio_ioport_write(proxy, addr, val);
 return;
@@ -491,27 +473,26 @@ static void virtio_pci_config_writel(void *opaque, 
uint32_t addr, uint32_t val)
 virtio_config_writel(proxy-vdev, addr, val);
 }
 
-static void virtio_map(PCIDevice *pci_dev, int region_num,
-   pcibus_t addr, pcibus_t size, int type)
-{
-VirtIOPCIProxy *proxy = container_of(pci_dev, VirtIOPCIProxy, pci_dev);
-VirtIODevice *vdev = proxy-vdev;
-unsigned config_len = VIRTIO_PCI_REGION_SIZE(pci_dev) + vdev-config_len;
-
-proxy-addr = addr;
+const MemoryRegionPortio virtio_portio[] = {
+{ 0, 0x1, 1, .write = virtio_pci_config_writeb, },
+{ 0, 0x1, 2, .write = virtio_pci_config_writew, },
+{ 0, 0x1, 4, .write = virtio_pci_config_writel, },
+{ 0, 0x1, 1, .read = virtio_pci_config_readb, },
+{ 0, 0x1, 2, .read = virtio_pci_config_readw, },
+{ 0, 0x1, 4, .read = virtio_pci_config_readl, },
+PORTIO_END
+};
 
-register_ioport_write(addr, config_len, 1, virtio_pci_config_writeb, 
proxy);
-

[PATCH v3 16/39] eepro100: convert to memory API

Note: the existing code aliases the flash BAR into the MMIO bar.  This is
probably a bug.  This patch does not correct the problem.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/eepro100.c |  182 -
 1 files changed, 37 insertions(+), 145 deletions(-)

diff --git a/hw/eepro100.c b/hw/eepro100.c
index 9b6f4a5..04723f3 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -228,13 +228,14 @@ typedef struct {
 PCIDevice dev;
 /* Hash register (multicast mask array, multiple individual addresses). */
 uint8_t mult[8];
-int mmio_index;
+MemoryRegion mmio_bar;
+MemoryRegion io_bar;
+MemoryRegion flash_bar;
 NICState *nic;
 NICConf conf;
 uint8_t scb_stat;   /* SCB stat/ack byte */
 uint8_t int_stat;   /* PCI interrupt status */
 /* region must not be saved by nic_save. */
-uint32_t region1;   /* PCI region 1 address */
 uint16_t mdimem[32];
 eeprom_t *eeprom;
 uint32_t device;/* device variant */
@@ -1584,147 +1585,36 @@ static void eepro100_write4(EEPRO100State * s, 
uint32_t addr, uint32_t val)
 }
 }
 
-/*
- *
- * Port mapped I/O.
- *
- /
-
-static uint32_t ioport_read1(void *opaque, uint32_t addr)
-{
-EEPRO100State *s = opaque;
-#if 0
-logout(addr=%s\n, regname(addr));
-#endif
-return eepro100_read1(s, addr - s-region1);
-}
-
-static uint32_t ioport_read2(void *opaque, uint32_t addr)
-{
-EEPRO100State *s = opaque;
-return eepro100_read2(s, addr - s-region1);
-}
-
-static uint32_t ioport_read4(void *opaque, uint32_t addr)
-{
-EEPRO100State *s = opaque;
-return eepro100_read4(s, addr - s-region1);
-}
-
-static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
-{
-EEPRO100State *s = opaque;
-#if 0
-logout(addr=%s val=0x%02x\n, regname(addr), val);
-#endif
-eepro100_write1(s, addr - s-region1, val);
-}
-
-static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
-{
-EEPRO100State *s = opaque;
-eepro100_write2(s, addr - s-region1, val);
-}
-
-static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
-{
-EEPRO100State *s = opaque;
-eepro100_write4(s, addr - s-region1, val);
-}
-
-/***/
-/* PCI EEPRO100 definitions */
-
-static void pci_map(PCIDevice * pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
-{
-EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
-
-TRACE(OTHER, logout(region %d, addr=0x%08FMT_PCIBUS, 
-  size=0x%08FMT_PCIBUS, type=%d\n,
-  region_num, addr, size, type));
-
-assert(region_num == 1);
-register_ioport_write(addr, size, 1, ioport_write1, s);
-register_ioport_read(addr, size, 1, ioport_read1, s);
-register_ioport_write(addr, size, 2, ioport_write2, s);
-register_ioport_read(addr, size, 2, ioport_read2, s);
-register_ioport_write(addr, size, 4, ioport_write4, s);
-register_ioport_read(addr, size, 4, ioport_read4, s);
-
-s-region1 = addr;
-}
-
-/*
- *
- * Memory mapped I/O.
- *
- /
-
-static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t 
val)
-{
-EEPRO100State *s = opaque;
-#if 0
-logout(addr=%s val=0x%02x\n, regname(addr), val);
-#endif
-eepro100_write1(s, addr, val);
-}
-
-static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t 
val)
+static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
+  unsigned size)
 {
 EEPRO100State *s = opaque;
-#if 0
-logout(addr=%s val=0x%02x\n, regname(addr), val);
-#endif
-eepro100_write2(s, addr, val);
-}
 
-static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t 
val)
-{
-EEPRO100State *s = opaque;
-#if 0
-logout(addr=%s val=0x%02x\n, regname(addr), val);
-#endif
-eepro100_write4(s, addr, val);
-}
-
-static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
-{
-EEPRO100State *s = opaque;
-#if 0
-logout(addr=%s\n, regname(addr));
-#endif
-return eepro100_read1(s, addr);
+switch (size) {
+case 1: return eepro100_read1(s, addr);
+case 2: return eepro100_read2(s, addr);
+case 4: return eepro100_read4(s, addr);
+default: abort();
+}
 }
 
-static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
+static void eepro100_write(void *opaque, target_phys_addr_t addr,
+   uint64_t data, unsigned size)
 {
 EEPRO100State *s = opaque;
-#if 0
-logout(addr=%s\n, regname(addr));
-#endif
-return

[PATCH v3 34/39] pci: remove pci_register_bar_simple()

Reviewed-by: Richard Henderson r...@twiddle.net
Superceded by pci_register_bar_region().
---
 hw/pci.c |   17 -
 hw/pci.h |3 ---
 2 files changed, 0 insertions(+), 20 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index 980840f..6aca1af 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -903,7 +903,6 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
 r-filtered_size = size;
 r-type = type;
 r-map_func = map_func;
-r-ram_addr = IO_MEM_UNASSIGNED;
 r-memory = NULL;
 
 wmask = ~(size - 1);
@@ -923,13 +922,6 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
 }
 }
 
-static void pci_simple_bar_mapfunc(PCIDevice *pci_dev, int region_num,
-   pcibus_t addr, pcibus_t size, int type)
-{
-cpu_register_physical_memory(addr, size,
- pci_dev-io_regions[region_num].ram_addr);
-}
-
 static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num,
   pcibus_t addr, pcibus_t size,
   int type)
@@ -942,15 +934,6 @@ static void pci_simple_bar_mapfunc_region(PCIDevice 
*pci_dev, int region_num,
 1);
 }
 
-void pci_register_bar_simple(PCIDevice *pci_dev, int region_num,
- pcibus_t size,  uint8_t attr, ram_addr_t ram_addr)
-{
-pci_register_bar(pci_dev, region_num, size,
- PCI_BASE_ADDRESS_SPACE_MEMORY | attr,
- pci_simple_bar_mapfunc);
-pci_dev-io_regions[region_num].ram_addr = ram_addr;
-}
-
 void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
  uint8_t attr, MemoryRegion *memory)
 {
diff --git a/hw/pci.h b/hw/pci.h
index a95e2ad..25e28b1 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -93,7 +93,6 @@ typedef struct PCIIORegion {
 pcibus_t filtered_size;
 uint8_t type;
 PCIMapIORegionFunc *map_func;
-ram_addr_t ram_addr;
 MemoryRegion *memory;
 MemoryRegion *address_space;
 } PCIIORegion;
@@ -204,8 +203,6 @@ PCIDevice *pci_register_device(PCIBus *bus, const char 
*name,
 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 pcibus_t size, uint8_t type,
 PCIMapIORegionFunc *map_func);
-void pci_register_bar_simple(PCIDevice *pci_dev, int region_num,
- pcibus_t size, uint8_t attr, ram_addr_t ram_addr);
 void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
  uint8_t attr, MemoryRegion *memory);
 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
-- 
1.7.5.3

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[PATCH v3 30/39] ehci: convert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/usb-ehci.c |   36 +---
 1 files changed, 9 insertions(+), 27 deletions(-)

diff --git a/hw/usb-ehci.c b/hw/usb-ehci.c
index 8b0dcc3..025ed1f 100644
--- a/hw/usb-ehci.c
+++ b/hw/usb-ehci.c
@@ -368,8 +368,7 @@ struct EHCIState {
 PCIDevice dev;
 USBBus bus;
 qemu_irq irq;
-target_phys_addr_t mem_base;
-int mem;
+MemoryRegion mem;
 int companion_count;
 
 /* properties */
@@ -2207,29 +2206,15 @@ static void ehci_frame_timer(void *opaque)
 qemu_mod_timer(ehci-frame_timer, expire_time);
 }
 
-static CPUReadMemoryFunc *ehci_readfn[3]={
-ehci_mem_readb,
-ehci_mem_readw,
-ehci_mem_readl
-};
 
-static CPUWriteMemoryFunc *ehci_writefn[3]={
-ehci_mem_writeb,
-ehci_mem_writew,
-ehci_mem_writel
+static const MemoryRegionOps ehci_mem_ops = {
+.old_mmio = {
+.read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
+.write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
+},
+.endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void ehci_map(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
-EHCIState *s =(EHCIState *)pci_dev;
-
-DPRINTF(ehci_map: region %d, addr %08 PRIx64 , size % PRId64 , s-mem 
%08X\n,
-region_num, addr, size, s-mem);
-s-mem_base = addr;
-cpu_register_physical_memory(addr, size, s-mem);
-}
-
 static int usb_ehci_initfn(PCIDevice *dev);
 
 static USBPortOps ehci_port_ops = {
@@ -2344,11 +2329,8 @@ static int usb_ehci_initfn(PCIDevice *dev)
 
 qemu_register_reset(ehci_reset, s);
 
-s-mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
-DEVICE_LITTLE_ENDIAN);
-
-pci_register_bar(s-dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
-ehci_map);
+memory_region_init_io(s-mem, ehci_mem_ops, s, ehci, MMIO_SIZE);
+pci_register_bar_region(s-dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, 
s-mem);
 
 fprintf(stderr, *** EHCI support is under development ***\n);
 
-- 
1.7.5.3

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[PATCH v3 37/39] pci: fold BAR mapping function into its caller

There is only one function, so no need for a function pointer.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/pci.c |   25 +
 hw/pci.h |1 -
 2 files changed, 9 insertions(+), 17 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index e9e4874..e6a759a 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -881,18 +881,6 @@ static int pci_unregister_device(DeviceState *dev)
 return 0;
 }
 
-static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num,
-  pcibus_t addr, pcibus_t size,
-  int type)
-{
-PCIIORegion *r = pci_dev-io_regions[region_num];
-
-memory_region_add_subregion_overlap(r-address_space,
-addr,
-r-memory,
-1);
-}
-
 void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
  uint8_t type, MemoryRegion *memory)
 {
@@ -914,7 +902,6 @@ void pci_register_bar_region(PCIDevice *pci_dev, int 
region_num,
 r-size = size;
 r-filtered_size = size;
 r-type = type;
-r-map_func = pci_simple_bar_mapfunc_region;
 r-memory = NULL;
 
 wmask = ~(size - 1);
@@ -1102,10 +1089,16 @@ static void pci_update_mappings(PCIDevice *d)
  * addr  (size - 1) != 0.
  */
 if (r-type  PCI_BASE_ADDRESS_SPACE_IO) {
-r-map_func(d, i, r-addr, r-filtered_size, r-type);
+memory_region_add_subregion_overlap(r-address_space,
+r-addr,
+r-memory,
+1);
 } else {
-r-map_func(d, i, pci_to_cpu_addr(d-bus, r-addr),
-r-filtered_size, r-type);
+memory_region_add_subregion_overlap(r-address_space,
+pci_to_cpu_addr(d-bus,
+r-addr),
+r-memory,
+1);
 }
 }
 }
diff --git a/hw/pci.h b/hw/pci.h
index 8028176..8d1662a 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -92,7 +92,6 @@ typedef struct PCIIORegion {
 pcibus_t size;
 pcibus_t filtered_size;
 uint8_t type;
-PCIMapIORegionFunc *map_func;
 MemoryRegion *memory;
 MemoryRegion *address_space;
 } PCIIORegion;
-- 
1.7.5.3

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[PATCH v3 23/39] lsi53c895a: convert to memory API

An optimization that fast-pathed DMA reads from the SCRIPTS memory
was removed int the process.  Likely it breaks with iommus anyway.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/lsi53c895a.c |  258 ---
 1 files changed, 56 insertions(+), 202 deletions(-)

diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index e9904c4..0ab8c78 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -185,9 +185,9 @@ typedef struct lsi_request {
 
 typedef struct {
 PCIDevice dev;
-int mmio_io_addr;
-int ram_io_addr;
-uint32_t script_ram_base;
+MemoryRegion mmio_io;
+MemoryRegion ram_io;
+MemoryRegion io_io;
 
 int carry; /* ??? Should this be an a visible register somewhere?  */
 int status;
@@ -391,10 +391,9 @@ static inline uint32_t read_dword(LSIState *s, uint32_t 
addr)
 {
 uint32_t buf;
 
-/* Optimize reading from SCRIPTS RAM.  */
-if ((addr  0xe000) == s-script_ram_base) {
-return s-script_ram[(addr  0x1fff)  2];
-}
+/* XXX: an optimization here used to fast-path the read from scripts
+ * memory.  But that bypasses any iommu.
+ */
 cpu_physical_memory_read(addr, (uint8_t *)buf, 4);
 return cpu_to_le32(buf);
 }
@@ -1899,232 +1898,90 @@ static void lsi_reg_writeb(LSIState *s, int offset, 
uint8_t val)
 #undef CASE_SET_REG32
 }
 
-static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t 
val)
+static void lsi_mmio_write(void *opaque, target_phys_addr_t addr,
+   uint64_t val, unsigned size)
 {
 LSIState *s = opaque;
 
 lsi_reg_writeb(s, addr  0xff, val);
 }
 
-static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t 
val)
-{
-LSIState *s = opaque;
-
-addr = 0xff;
-lsi_reg_writeb(s, addr, val  0xff);
-lsi_reg_writeb(s, addr + 1, (val  8)  0xff);
-}
-
-static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t 
val)
-{
-LSIState *s = opaque;
-
-addr = 0xff;
-lsi_reg_writeb(s, addr, val  0xff);
-lsi_reg_writeb(s, addr + 1, (val  8)  0xff);
-lsi_reg_writeb(s, addr + 2, (val  16)  0xff);
-lsi_reg_writeb(s, addr + 3, (val  24)  0xff);
-}
-
-static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t lsi_mmio_read(void *opaque, target_phys_addr_t addr,
+  unsigned size)
 {
 LSIState *s = opaque;
 
 return lsi_reg_readb(s, addr  0xff);
 }
 
-static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
-{
-LSIState *s = opaque;
-uint32_t val;
-
-addr = 0xff;
-val = lsi_reg_readb(s, addr);
-val |= lsi_reg_readb(s, addr + 1)  8;
-return val;
-}
-
-static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
-{
-LSIState *s = opaque;
-uint32_t val;
-addr = 0xff;
-val = lsi_reg_readb(s, addr);
-val |= lsi_reg_readb(s, addr + 1)  8;
-val |= lsi_reg_readb(s, addr + 2)  16;
-val |= lsi_reg_readb(s, addr + 3)  24;
-return val;
-}
-
-static CPUReadMemoryFunc * const lsi_mmio_readfn[3] = {
-lsi_mmio_readb,
-lsi_mmio_readw,
-lsi_mmio_readl,
-};
-
-static CPUWriteMemoryFunc * const lsi_mmio_writefn[3] = {
-lsi_mmio_writeb,
-lsi_mmio_writew,
-lsi_mmio_writel,
+static const MemoryRegionOps lsi_mmio_ops = {
+.read = lsi_mmio_read,
+.write = lsi_mmio_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.impl = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
 };
 
-static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void lsi_ram_write(void *opaque, target_phys_addr_t addr,
+  uint64_t val, unsigned size)
 {
 LSIState *s = opaque;
 uint32_t newval;
+uint32_t mask;
 int shift;
 
-addr = 0x1fff;
 newval = s-script_ram[addr  2];
 shift = (addr  3) * 8;
-newval = ~(0xff  shift);
+mask = ((uint64_t)1  (size * 8)) - 1;
+newval = ~(mask  shift);
 newval |= val  shift;
 s-script_ram[addr  2] = newval;
 }
 
-static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-LSIState *s = opaque;
-uint32_t newval;
-
-addr = 0x1fff;
-newval = s-script_ram[addr  2];
-if (addr  2) {
-newval = (newval  0x) | (val  16);
-} else {
-newval = (newval  0x) | val;
-}
-s-script_ram[addr  2] = newval;
-}
-
-
-static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-LSIState *s = opaque;
-
-addr = 0x1fff;
-s-script_ram[addr  2] = val;
-}
-
-static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t lsi_ram_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
 {
 LSIState *s = opaque;
 uint32_t val;
+uint32_t mask;
 
-addr = 0x1fff;
 val = s-script_ram[addr  2];
+mask

[PATCH v3 31/39] uhci: convert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/usb-uhci.c |   42 --
 1 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c
index da74c57..96a17bd 100644
--- a/hw/usb-uhci.c
+++ b/hw/usb-uhci.c
@@ -132,6 +132,7 @@ typedef struct UHCIPort {
 
 struct UHCIState {
 PCIDevice dev;
+MemoryRegion io_bar;
 USBBus bus; /* Note unused when we're a companion controller */
 uint16_t cmd; /* cmd register */
 uint16_t status;
@@ -1101,18 +1102,19 @@ static void uhci_frame_timer(void *opaque)
 qemu_mod_timer(s-frame_timer, s-expire_time);
 }
 
-static void uhci_map(PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
-{
-UHCIState *s = (UHCIState *)pci_dev;
-
-register_ioport_write(addr, 32, 2, uhci_ioport_writew, s);
-register_ioport_read(addr, 32, 2, uhci_ioport_readw, s);
-register_ioport_write(addr, 32, 4, uhci_ioport_writel, s);
-register_ioport_read(addr, 32, 4, uhci_ioport_readl, s);
-register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s);
-register_ioport_read(addr, 32, 1, uhci_ioport_readb, s);
-}
+static const MemoryRegionPortio uhci_portio[] = {
+{ 0, 32, 2, .write = uhci_ioport_writew, },
+{ 0, 32, 2, .read = uhci_ioport_readw, },
+{ 0, 32, 4, .write = uhci_ioport_writel, },
+{ 0, 32, 4, .read = uhci_ioport_readl, },
+{ 0, 32, 1, .write = uhci_ioport_writeb, },
+{ 0, 32, 1, .read = uhci_ioport_readb, },
+PORTIO_END
+};
+
+static const MemoryRegionOps uhci_ioport_ops = {
+.old_portio = uhci_portio,
+};
 
 static USBPortOps uhci_port_ops = {
 .attach = uhci_attach,
@@ -1159,10 +1161,11 @@ static int usb_uhci_common_initfn(PCIDevice *dev)
 
 qemu_register_reset(uhci_reset, s);
 
+memory_region_init_io(s-io_bar, uhci_ioport_ops, s, uhci, 0x20);
 /* Use region 4 for consistency with real hardware.  BSD guests seem
to rely on this.  */
-pci_register_bar(s-dev, 4, 0x20,
-   PCI_BASE_ADDRESS_SPACE_IO, uhci_map);
+pci_register_bar_region(s-dev, 4,
+PCI_BASE_ADDRESS_SPACE_IO, s-io_bar);
 
 return 0;
 }
@@ -1182,6 +1185,14 @@ static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
 return usb_uhci_common_initfn(dev);
 }
 
+static int usb_uhci_exit(PCIDevice *dev)
+{
+UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
+
+memory_region_destroy(s-io_bar);
+return 0;
+}
+
 static Property uhci_properties[] = {
 DEFINE_PROP_STRING(masterbus, UHCIState, masterbus),
 DEFINE_PROP_UINT32(firstport, UHCIState, firstport, 0),
@@ -1194,6 +1205,7 @@ static PCIDeviceInfo uhci_info[] = {
 .qdev.size= sizeof(UHCIState),
 .qdev.vmsd= vmstate_uhci,
 .init = usb_uhci_common_initfn,
+.exit = usb_uhci_exit,
 .vendor_id= PCI_VENDOR_ID_INTEL,
 .device_id= PCI_DEVICE_ID_INTEL_82371SB_2,
 .revision = 0x01,
@@ -1204,6 +1216,7 @@ static PCIDeviceInfo uhci_info[] = {
 .qdev.size= sizeof(UHCIState),
 .qdev.vmsd= vmstate_uhci,
 .init = usb_uhci_common_initfn,
+.exit = usb_uhci_exit,
 .vendor_id= PCI_VENDOR_ID_INTEL,
 .device_id= PCI_DEVICE_ID_INTEL_82371AB_2,
 .revision = 0x01,
@@ -1214,6 +1227,7 @@ static PCIDeviceInfo uhci_info[] = {
 .qdev.size= sizeof(UHCIState),
 .qdev.vmsd= vmstate_uhci,
 .init = usb_uhci_vt82c686b_initfn,
+.exit = usb_uhci_exit,
 .vendor_id= PCI_VENDOR_ID_VIA,
 .device_id= PCI_DEVICE_ID_VIA_UHCI,
 .revision = 0x01,
-- 
1.7.5.3

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[PATCH v3 36/39] pci: remove pci_register_bar()

Superceded by pci_register_bar_region().  The implementations
are folded together.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/pci.c |   42 +-
 hw/pci.h |3 ---
 2 files changed, 17 insertions(+), 28 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index 481eb7e..e9e4874 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -881,13 +881,25 @@ static int pci_unregister_device(DeviceState *dev)
 return 0;
 }
 
-void pci_register_bar(PCIDevice *pci_dev, int region_num,
-pcibus_t size, uint8_t type,
-PCIMapIORegionFunc *map_func)
+static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num,
+  pcibus_t addr, pcibus_t size,
+  int type)
+{
+PCIIORegion *r = pci_dev-io_regions[region_num];
+
+memory_region_add_subregion_overlap(r-address_space,
+addr,
+r-memory,
+1);
+}
+
+void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
+ uint8_t type, MemoryRegion *memory)
 {
 PCIIORegion *r;
 uint32_t addr;
 uint64_t wmask;
+pcibus_t size = memory_region_size(memory);
 
 assert(region_num = 0);
 assert(region_num  PCI_NUM_REGIONS);
@@ -902,7 +914,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
 r-size = size;
 r-filtered_size = size;
 r-type = type;
-r-map_func = map_func;
+r-map_func = pci_simple_bar_mapfunc_region;
 r-memory = NULL;
 
 wmask = ~(size - 1);
@@ -920,29 +932,9 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
 pci_set_long(pci_dev-wmask + addr, wmask  0x);
 pci_set_long(pci_dev-cmask + addr, 0x);
 }
-}
-
-static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num,
-  pcibus_t addr, pcibus_t size,
-  int type)
-{
-PCIIORegion *r = pci_dev-io_regions[region_num];
-
-memory_region_add_subregion_overlap(r-address_space,
-addr,
-r-memory,
-1);
-}
-
-void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
- uint8_t attr, MemoryRegion *memory)
-{
-pci_register_bar(pci_dev, region_num, memory_region_size(memory),
- attr,
- pci_simple_bar_mapfunc_region);
 pci_dev-io_regions[region_num].memory = memory;
 pci_dev-io_regions[region_num].address_space
-= attr  PCI_BASE_ADDRESS_SPACE_IO
+= type  PCI_BASE_ADDRESS_SPACE_IO
 ? pci_dev-bus-address_space_io
 : pci_dev-bus-address_space_mem;
 }
diff --git a/hw/pci.h b/hw/pci.h
index 6e2bcea..8028176 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -201,9 +201,6 @@ PCIDevice *pci_register_device(PCIBus *bus, const char 
*name,
PCIConfigReadFunc *config_read,
PCIConfigWriteFunc *config_write);
 
-void pci_register_bar(PCIDevice *pci_dev, int region_num,
-pcibus_t size, uint8_t type,
-PCIMapIORegionFunc *map_func);
 void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
  uint8_t attr, MemoryRegion *memory);
 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
-- 
1.7.5.3

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[PATCH v3 35/39] pci: convert pci rom to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/pci.c |   20 +++-
 hw/pci.h |3 ++-
 2 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index 6aca1af..481eb7e 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1857,11 +1857,6 @@ static uint8_t pci_find_capability_list(PCIDevice *pdev, 
uint8_t cap_id,
 return next;
 }
 
-static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, 
pcibus_t size, int type)
-{
-cpu_register_physical_memory(addr, size, pdev-rom_offset);
-}
-
 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
This is needed for an option rom which is used for more than one device. */
 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
@@ -1965,9 +1960,9 @@ static int pci_add_option_rom(PCIDevice *pdev, bool 
is_default_rom)
 snprintf(name, sizeof(name), %s.rom, pdev-qdev.info-vmsd-name);
 else
 snprintf(name, sizeof(name), %s.rom, pdev-qdev.info-name);
-pdev-rom_offset = qemu_ram_alloc(pdev-qdev, name, size);
-
-ptr = qemu_get_ram_ptr(pdev-rom_offset);
+pdev-has_rom = true;
+memory_region_init_ram(pdev-rom, pdev-qdev, name, size);
+ptr = memory_region_get_ram_ptr(pdev-rom);
 load_image(path, ptr);
 qemu_free(path);
 
@@ -1978,19 +1973,18 @@ static int pci_add_option_rom(PCIDevice *pdev, bool 
is_default_rom)
 
 qemu_put_ram_ptr(ptr);
 
-pci_register_bar(pdev, PCI_ROM_SLOT, size,
- 0, pci_map_option_rom);
+pci_register_bar_region(pdev, PCI_ROM_SLOT, 0, pdev-rom);
 
 return 0;
 }
 
 static void pci_del_option_rom(PCIDevice *pdev)
 {
-if (!pdev-rom_offset)
+if (!pdev-has_rom)
 return;
 
-qemu_ram_free(pdev-rom_offset);
-pdev-rom_offset = 0;
+memory_region_destroy(pdev-rom);
+pdev-has_rom = false;
 }
 
 /*
diff --git a/hw/pci.h b/hw/pci.h
index 25e28b1..6e2bcea 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -191,7 +191,8 @@ struct PCIDevice {
 
 /* Location of option rom */
 char *romfile;
-ram_addr_t rom_offset;
+bool has_rom;
+MemoryRegion rom;
 uint32_t rom_bar;
 };
 
-- 
1.7.5.3

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[PATCH v3 26/39] pcnet: convert to memory API

Also related chips.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/lance.c |   31 ++-
 hw/pcnet-pci.c |   74 +--
 hw/pcnet.h |4 ++-
 3 files changed, 61 insertions(+), 48 deletions(-)

diff --git a/hw/lance.c b/hw/lance.c
index ddb1cbb..8e20360 100644
--- a/hw/lance.c
+++ b/hw/lance.c
@@ -55,8 +55,8 @@ static void parent_lance_reset(void *opaque, int irq, int 
level)
 pcnet_h_reset(d-state);
 }
 
-static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void lance_mem_write(void *opaque, target_phys_addr_t addr,
+uint64_t val, unsigned size)
 {
 SysBusPCNetState *d = opaque;
 
@@ -64,7 +64,8 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t 
addr,
 pcnet_ioport_writew(d-state, addr, val  0x);
 }
 
-static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint64_t lance_mem_read(void *opaque, target_phys_addr_t addr,
+   unsigned size)
 {
 SysBusPCNetState *d = opaque;
 uint32_t val;
@@ -74,16 +75,14 @@ static uint32_t lance_mem_readw(void *opaque, 
target_phys_addr_t addr)
 return val  0x;
 }
 
-static CPUReadMemoryFunc * const lance_mem_read[3] = {
-NULL,
-lance_mem_readw,
-NULL,
-};
-
-static CPUWriteMemoryFunc * const lance_mem_write[3] = {
-NULL,
-lance_mem_writew,
-NULL,
+static const MemoryRegionOps lance_mem_ops = {
+.read = lance_mem_read,
+.write = lance_mem_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.valid = {
+.min_access_size = 2,
+.max_access_size = 2,
+},
 };
 
 static void lance_cleanup(VLANClientState *nc)
@@ -117,13 +116,11 @@ static int lance_init(SysBusDevice *dev)
 SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
 PCNetState *s = d-state;
 
-s-mmio_index =
-cpu_register_io_memory(lance_mem_read, lance_mem_write, d,
-   DEVICE_NATIVE_ENDIAN);
+memory_region_init_io(s-mmio, lance_mem_ops, s, lance-mmio, 4);
 
 qdev_init_gpio_in(dev-qdev, parent_lance_reset, 1);
 
-sysbus_init_mmio(dev, 4, s-mmio_index);
+sysbus_init_mmio_region(dev, s-mmio);
 
 sysbus_init_irq(dev, s-irq);
 
diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c
index 216cf81..a25f565 100644
--- a/hw/pcnet-pci.c
+++ b/hw/pcnet-pci.c
@@ -46,6 +46,7 @@
 typedef struct {
 PCIDevice pci_dev;
 PCNetState state;
+MemoryRegion io_bar;
 } PCIPCNetState;
 
 static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
@@ -69,25 +70,41 @@ static uint32_t pcnet_aprom_readb(void *opaque, uint32_t 
addr)
 return val;
 }
 
-static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
+static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
+  unsigned size)
 {
-PCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev)-state;
+PCNetState *d = opaque;
 
-#ifdef PCNET_DEBUG_IO
-printf(pcnet_ioport_map addr=0x%04FMT_PCIBUS size=0x%04FMT_PCIBUS\n,
-   addr, size);
-#endif
+if (addr  16  size == 1) {
+return pcnet_aprom_readb(d, addr);
+} else if (addr = 0x10  addr  0x20  size == 2) {
+return pcnet_ioport_readw(d, addr);
+} else if (addr = 0x10  addr  0x20  size == 4) {
+return pcnet_ioport_readl(d, addr);
+}
+return ((uint64_t)1  (size * 8)) - 1;
+}
 
-register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
-register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d);
+static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
+   uint64_t data, unsigned size)
+{
+PCNetState *d = opaque;
 
-register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d);
-register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d);
-register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d);
-register_ioport_read(addr + 0x10, 0x10, 4, pcnet_ioport_readl, d);
+if (addr  16  size == 1) {
+return pcnet_aprom_writeb(d, addr, data);
+} else if (addr = 0x10  addr  0x20  size == 2) {
+return pcnet_ioport_writew(d, addr, data);
+} else if (addr = 0x10  addr  0x20  size == 4) {
+return pcnet_ioport_writel(d, addr, data);
+}
 }
 
+static const MemoryRegionOps pcnet_io_ops = {
+.read = pcnet_ioport_read,
+.write = pcnet_ioport_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
 static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t 
val)
 {
 PCNetState *d = opaque;
@@ -202,16 +219,12 @@ static const VMStateDescription vmstate_pci_pcnet = {
 
 /* PCI interface */
 
-static CPUWriteMemoryFunc * const pcnet_mmio_write[] = {
-pcnet_mmio_writeb,
-

[PATCH v3 17/39] es1370: convert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/es1370.c |   43 +--
 1 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/hw/es1370.c b/hw/es1370.c
index 1ed62b7..6a01797 100644
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -268,6 +268,7 @@ struct chan {
 typedef struct ES1370State {
 PCIDevice dev;
 QEMUSoundCard card;
+MemoryRegion io;
 struct chan chan[NB_CHANNELS];
 SWVoiceOut *dac_voice[2];
 SWVoiceIn *adc_voice;
@@ -775,7 +776,6 @@ IO_READ_PROTO (es1370_readl)
 return val;
 }
 
-
 static void es1370_transfer_audio (ES1370State *s, struct chan *d, int 
loop_sel,
int max, int *irq)
 {
@@ -906,23 +906,20 @@ static void es1370_adc_callback (void *opaque, int avail)
 es1370_run_channel (s, ADC_CHANNEL, avail);
 }
 
-static void es1370_map (PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
-{
-ES1370State *s = DO_UPCAST (ES1370State, dev, pci_dev);
-
-(void) region_num;
-(void) size;
-(void) type;
-
-register_ioport_write (addr, 0x40 * 4, 1, es1370_writeb, s);
-register_ioport_write (addr, 0x40 * 2, 2, es1370_writew, s);
-register_ioport_write (addr, 0x40, 4, es1370_writel, s);
+static const MemoryRegionPortio es1370_portio[] = {
+{ 0, 0x40 * 4, 1, .write = es1370_writeb, },
+{ 0, 0x40 * 2, 2, .write = es1370_writew, },
+{ 0, 0x40, 4, .write = es1370_writel, },
+{ 0, 0x40 * 4, 1, .read = es1370_readb, },
+{ 0, 0x40 * 2, 2, .read = es1370_readw, },
+{ 0, 0x40, 4, .read = es1370_readl, },
+PORTIO_END
+};
 
-register_ioport_read (addr, 0x40 * 4, 1, es1370_readb, s);
-register_ioport_read (addr, 0x40 * 2, 2, es1370_readw, s);
-register_ioport_read (addr, 0x40, 4, es1370_readl, s);
-}
+static const MemoryRegionOps es1370_io_ops = {
+.old_portio = es1370_portio,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
 
 static const VMStateDescription vmstate_es1370_channel = {
 .name = es1370_channel,
@@ -1011,7 +1008,8 @@ static int es1370_initfn (PCIDevice *dev)
 c[PCI_MIN_GNT] = 0x0c;
 c[PCI_MAX_LAT] = 0x80;
 
-pci_register_bar (s-dev, 0, 256, PCI_BASE_ADDRESS_SPACE_IO, es1370_map);
+memory_region_init_io(s-io, es1370_io_ops, s, es1370, 256);
+pci_register_bar_region(s-dev, 0, PCI_BASE_ADDRESS_SPACE_IO, s-io);
 qemu_register_reset (es1370_on_reset, s);
 
 AUD_register_card (es1370, s-card);
@@ -1019,6 +1017,14 @@ static int es1370_initfn (PCIDevice *dev)
 return 0;
 }
 
+static int es1370_exitfn(PCIDevice *dev)
+{
+ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
+
+memory_region_destroy(s-io);
+return 0;
+}
+
 int es1370_init (PCIBus *bus)
 {
 pci_create_simple (bus, -1, ES1370);
@@ -1031,6 +1037,7 @@ static PCIDeviceInfo es1370_info = {
 .qdev.size= sizeof (ES1370State),
 .qdev.vmsd= vmstate_es1370,
 .init = es1370_initfn,
+.exit = es1370_exitfn,
 .vendor_id= PCI_VENDOR_ID_ENSONIQ,
 .device_id= PCI_DEVICE_ID_ENSONIQ_ES1370,
 .class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
-- 
1.7.5.3

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[PATCH v3 14/39] ac97: convert to memory API

fixes BAR sizing as well.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/ac97.c |   88 +++-
 1 files changed, 51 insertions(+), 37 deletions(-)

diff --git a/hw/ac97.c b/hw/ac97.c
index 0b59896..bcddaa6 100644
--- a/hw/ac97.c
+++ b/hw/ac97.c
@@ -160,8 +160,9 @@ typedef struct AC97LinkState {
 SWVoiceIn *voice_mc;
 int invalid_freq[3];
 uint8_t silence[128];
-uint32_t base[2];
 int bup_flag;
+MemoryRegion io_nam;
+MemoryRegion io_nabm;
 } AC97LinkState;
 
 enum {
@@ -583,7 +584,7 @@ static uint32_t nam_readw (void *opaque, uint32_t addr)
 {
 AC97LinkState *s = opaque;
 uint32_t val = ~0U;
-uint32_t index = addr - s-base[0];
+uint32_t index = addr;
 s-cas = 0;
 val = mixer_load (s, index);
 return val;
@@ -611,7 +612,7 @@ static void nam_writeb (void *opaque, uint32_t addr, 
uint32_t val)
 static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
 {
 AC97LinkState *s = opaque;
-uint32_t index = addr - s-base[0];
+uint32_t index = addr;
 s-cas = 0;
 switch (index) {
 case AC97_Reset:
@@ -714,7 +715,7 @@ static uint32_t nabm_readb (void *opaque, uint32_t addr)
 {
 AC97LinkState *s = opaque;
 AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s-base[1];
+uint32_t index = addr;
 uint32_t val = ~0U;
 
 switch (index) {
@@ -769,7 +770,7 @@ static uint32_t nabm_readw (void *opaque, uint32_t addr)
 {
 AC97LinkState *s = opaque;
 AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s-base[1];
+uint32_t index = addr;
 uint32_t val = ~0U;
 
 switch (index) {
@@ -798,7 +799,7 @@ static uint32_t nabm_readl (void *opaque, uint32_t addr)
 {
 AC97LinkState *s = opaque;
 AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s-base[1];
+uint32_t index = addr;
 uint32_t val = ~0U;
 
 switch (index) {
@@ -848,7 +849,7 @@ static void nabm_writeb (void *opaque, uint32_t addr, 
uint32_t val)
 {
 AC97LinkState *s = opaque;
 AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s-base[1];
+uint32_t index = addr;
 switch (index) {
 case PI_LVI:
 case PO_LVI:
@@ -904,7 +905,7 @@ static void nabm_writew (void *opaque, uint32_t addr, 
uint32_t val)
 {
 AC97LinkState *s = opaque;
 AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s-base[1];
+uint32_t index = addr;
 switch (index) {
 case PI_SR:
 case PO_SR:
@@ -924,7 +925,7 @@ static void nabm_writel (void *opaque, uint32_t addr, 
uint32_t val)
 {
 AC97LinkState *s = opaque;
 AC97BusMasterRegs *r = NULL;
-uint32_t index = addr - s-base[1];
+uint32_t index = addr;
 switch (index) {
 case PI_BDBAR:
 case PO_BDBAR:
@@ -1230,31 +1231,33 @@ static const VMStateDescription vmstate_ac97 = {
 }
 };
 
-static void ac97_map (PCIDevice *pci_dev, int region_num,
-  pcibus_t addr, pcibus_t size, int type)
-{
-AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev);
-PCIDevice *d = s-dev;
-
-if (!region_num) {
-s-base[0] = addr;
-register_ioport_read (addr, 256 * 1, 1, nam_readb, d);
-register_ioport_read (addr, 256 * 2, 2, nam_readw, d);
-register_ioport_read (addr, 256 * 4, 4, nam_readl, d);
-register_ioport_write (addr, 256 * 1, 1, nam_writeb, d);
-register_ioport_write (addr, 256 * 2, 2, nam_writew, d);
-register_ioport_write (addr, 256 * 4, 4, nam_writel, d);
-}
-else {
-s-base[1] = addr;
-register_ioport_read (addr, 64 * 1, 1, nabm_readb, d);
-register_ioport_read (addr, 64 * 2, 2, nabm_readw, d);
-register_ioport_read (addr, 64 * 4, 4, nabm_readl, d);
-register_ioport_write (addr, 64 * 1, 1, nabm_writeb, d);
-register_ioport_write (addr, 64 * 2, 2, nabm_writew, d);
-register_ioport_write (addr, 64 * 4, 4, nabm_writel, d);
-}
-}
+static const MemoryRegionPortio nam_portio[] = {
+{ 0, 256 * 1, 1, .read = nam_readb, },
+{ 0, 256 * 2, 2, .read = nam_readw, },
+{ 0, 256 * 4, 4, .read = nam_readl, },
+{ 0, 256 * 1, 1, .write = nam_writeb, },
+{ 0, 256 * 2, 2, .write = nam_writew, },
+{ 0, 256 * 4, 4, .write = nam_writel, },
+PORTIO_END,
+};
+
+static const MemoryRegionOps ac97_io_nam_ops = {
+.old_portio = nam_portio,
+};
+
+static const MemoryRegionPortio nabm_portio[] = {
+{ 0, 64 * 1, 1, .read = nabm_readb, },
+{ 0, 64 * 2, 2, .read = nabm_readw, },
+{ 0, 64 * 4, 4, .read = nabm_readl, },
+{ 0, 64 * 1, 1, .write = nabm_writeb, },
+{ 0, 64 * 2, 2, .write = nabm_writew, },
+{ 0, 64 * 4, 4, .write = nabm_writel, },
+PORTIO_END
+};
+
+static const MemoryRegionOps ac97_io_nabm_ops = {
+.old_portio = nabm_portio,
+};
 
 static void ac97_on_reset (void *opaque)
 {
@@ -1311,15 +1314,25 @@ static int ac97_initfn (PCIDevice *dev)

[PATCH v3 24/39] ppc: convert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/cuda.c |6 ++-
 hw/escc.c |   42 +--
 hw/escc.h |2 +-
 hw/heathrow_pic.c |   29 --
 hw/ide.h  |2 +-
 hw/ide/macio.c|   36 ---
 hw/mac_dbdma.c|   32 ++--
 hw/mac_dbdma.h|4 ++-
 hw/mac_nvram.c|   39 ++---
 hw/macio.c|   74 +++-
 hw/openpic.c  |   81 +
 hw/openpic.h  |2 +-
 hw/ppc_mac.h  |   16 ++
 hw/ppc_newworld.c |   30 +--
 hw/ppc_oldworld.c |   23 +++
 15 files changed, 201 insertions(+), 217 deletions(-)

diff --git a/hw/cuda.c b/hw/cuda.c
index 065c362..5c92d81 100644
--- a/hw/cuda.c
+++ b/hw/cuda.c
@@ -117,6 +117,7 @@ typedef struct CUDATimer {
 } CUDATimer;
 
 typedef struct CUDAState {
+MemoryRegion mem;
 /* cuda registers */
 uint8_t b;  /* B-side data */
 uint8_t a;  /* A-side data */
@@ -722,7 +723,7 @@ static void cuda_reset(void *opaque)
 set_counter(s, s-timers[1], 0x);
 }
 
-void cuda_init (int *cuda_mem_index, qemu_irq irq)
+void cuda_init (MemoryRegion **cuda_mem, qemu_irq irq)
 {
 struct tm tm;
 CUDAState *s = cuda_state;
@@ -738,8 +739,9 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
 s-tick_offset = (uint32_t)mktimegm(tm) + RTC_OFFSET;
 
 s-adb_poll_timer = qemu_new_timer_ns(vm_clock, cuda_adb_poll, s);
-*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s,
+cpu_register_io_memory(cuda_read, cuda_write, s,
  DEVICE_NATIVE_ENDIAN);
+*cuda_mem = s-mem;
 vmstate_register(NULL, -1, vmstate_cuda, s);
 qemu_register_reset(cuda_reset, s);
 }
diff --git a/hw/escc.c b/hw/escc.c
index f6fd919..bea5873 100644
--- a/hw/escc.c
+++ b/hw/escc.c
@@ -126,7 +126,7 @@ struct SerialState {
 SysBusDevice busdev;
 struct ChannelState chn[2];
 uint32_t it_shift;
-int mmio_index;
+MemoryRegion mmio;
 uint32_t disabled;
 uint32_t frequency;
 };
@@ -490,7 +490,8 @@ static void escc_update_parameters(ChannelState *s)
 qemu_chr_ioctl(s-chr, CHR_IOCTL_SERIAL_SET_PARAMS, ssp);
 }
 
-static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t 
val)
+static void escc_mem_write(void *opaque, target_phys_addr_t addr,
+   uint64_t val, unsigned size)
 {
 SerialState *serial = opaque;
 ChannelState *s;
@@ -592,7 +593,8 @@ static void escc_mem_writeb(void *opaque, 
target_phys_addr_t addr, uint32_t val)
 }
 }
 
-static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t escc_mem_read(void *opaque, target_phys_addr_t addr,
+  unsigned size)
 {
 SerialState *serial = opaque;
 ChannelState *s;
@@ -627,6 +629,16 @@ static uint32_t escc_mem_readb(void *opaque, 
target_phys_addr_t addr)
 return 0;
 }
 
+static const MemoryRegionOps escc_mem_ops = {
+.read = escc_mem_read,
+.write = escc_mem_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.valid = {
+.min_access_size = 1,
+.max_access_size = 1,
+},
+};
+
 static int serial_can_receive(void *opaque)
 {
 ChannelState *s = opaque;
@@ -668,18 +680,6 @@ static void serial_event(void *opaque, int event)
 serial_receive_break(s);
 }
 
-static CPUReadMemoryFunc * const escc_mem_read[3] = {
-escc_mem_readb,
-NULL,
-NULL,
-};
-
-static CPUWriteMemoryFunc * const escc_mem_write[3] = {
-escc_mem_writeb,
-NULL,
-NULL,
-};
-
 static const VMStateDescription vmstate_escc_chn = {
 .name =escc_chn,
 .version_id = 2,
@@ -712,7 +712,7 @@ static const VMStateDescription vmstate_escc = {
 }
 };
 
-int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
+MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
   CharDriverState *chrA, CharDriverState *chrB,
   int clock, int it_shift)
 {
@@ -737,7 +737,7 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA, 
qemu_irq irqB,
 }
 
 d = FROM_SYSBUS(SerialState, s);
-return d-mmio_index;
+return d-mmio;
 }
 
 static const uint8_t keycodes[128] = {
@@ -901,7 +901,6 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, 
qemu_irq irq,
 static int escc_init1(SysBusDevice *dev)
 {
 SerialState *s = FROM_SYSBUS(SerialState, dev);
-int io;
 unsigned int i;
 
 s-chn[0].disabled = s-disabled;
@@ -918,10 +917,9 @@ static int escc_init1(SysBusDevice *dev)
 s-chn[0].otherchn = s-chn[1];
 s-chn[1].otherchn = s-chn[0];
 
-io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s,
-DEVICE_NATIVE_ENDIAN);
-sysbus_init_mmio(dev, ESCC_SIZE  s-it_shift, io);
-

[PATCH v3 39/39] pci: remove support for pre memory API BARs

Not used anymore.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/pci.c |   33 ++---
 1 files changed, 2 insertions(+), 31 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index 6ed08ae..e6a3e56 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -848,18 +848,7 @@ static void pci_unregister_io_regions(PCIDevice *pci_dev)
 r = pci_dev-io_regions[i];
 if (!r-size || r-addr == PCI_BAR_UNMAPPED)
 continue;
-if (r-memory) {
-memory_region_del_subregion(r-address_space, r-memory);
-} else {
-if (r-type == PCI_BASE_ADDRESS_SPACE_IO) {
-isa_unassign_ioport(r-addr, r-filtered_size);
-} else {
-cpu_register_physical_memory(pci_to_cpu_addr(pci_dev-bus,
- r-addr),
- r-filtered_size,
- IO_MEM_UNASSIGNED);
-}
-}
+memory_region_del_subregion(r-address_space, r-memory);
 }
 }
 
@@ -1058,25 +1047,7 @@ static void pci_update_mappings(PCIDevice *d)
 
 /* now do the real mapping */
 if (r-addr != PCI_BAR_UNMAPPED) {
-if (r-memory) {
-memory_region_del_subregion(r-address_space, r-memory);
-} else if (r-type  PCI_BASE_ADDRESS_SPACE_IO) {
-int class;
-/* NOTE: specific hack for IDE in PC case:
-   only one byte must be mapped. */
-class = pci_get_word(d-config + PCI_CLASS_DEVICE);
-if (class == 0x0101  r-size == 4) {
-isa_unassign_ioport(r-addr + 2, 1);
-} else {
-isa_unassign_ioport(r-addr, r-filtered_size);
-}
-} else {
-cpu_register_physical_memory(pci_to_cpu_addr(d-bus,
- r-addr),
- r-filtered_size,
- IO_MEM_UNASSIGNED);
-qemu_unregister_coalesced_mmio(r-addr, r-filtered_size);
-}
+memory_region_del_subregion(r-address_space, r-memory);
 }
 r-addr = new_addr;
 r-filtered_size = filtered_size;
-- 
1.7.5.3

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[PATCH v3 33/39] msix: convert to memory API

The msix table is defined as a subregion, to allow for a BAR that
mixes device specific regions with the msix table.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/ivshmem.c|   11 +
 hw/msix.c   |   64 +++
 hw/msix.h   |6 +---
 hw/pci.h|2 +-
 hw/virtio-pci.c |   16 -
 hw/virtio-pci.h |1 +
 6 files changed, 42 insertions(+), 58 deletions(-)

diff --git a/hw/ivshmem.c b/hw/ivshmem.c
index f80e7b6..bacba60 100644
--- a/hw/ivshmem.c
+++ b/hw/ivshmem.c
@@ -65,6 +65,7 @@ typedef struct IVShmemState {
  */
 MemoryRegion bar;
 MemoryRegion ivshmem;
+MemoryRegion msix_bar;
 uint64_t ivshmem_size; /* size of shared memory region */
 int shm_fd; /* shared memory file descriptor */
 
@@ -540,11 +541,11 @@ static void ivshmem_setup_msi(IVShmemState * s) {
 
 /* allocate the MSI-X vectors */
 
-if (!msix_init(s-dev, s-vectors, 1, 0)) {
-pci_register_bar(s-dev, 1,
- msix_bar_size(s-dev),
- PCI_BASE_ADDRESS_SPACE_MEMORY,
- msix_mmio_map);
+memory_region_init(s-msix_bar, ivshmem-msix, 4096);
+if (!msix_init(s-dev, s-vectors, s-msix_bar, 1, 0)) {
+pci_register_bar_region(s-dev, 1,
+PCI_BASE_ADDRESS_SPACE_MEMORY,
+s-msix_bar);
 IVSHMEM_DPRINTF(msix initialized (%d vectors)\n, s-vectors);
 } else {
 IVSHMEM_DPRINTF(msix initialization failed\n);
diff --git a/hw/msix.c b/hw/msix.c
index e67e700..8536c3f 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -82,7 +82,8 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned 
short nentries,
 return 0;
 }
 
-static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
+   unsigned size)
 {
 PCIDevice *dev = opaque;
 unsigned int offset = addr  (MSIX_PAGE_SIZE - 1)  ~0x3;
@@ -91,12 +92,6 @@ static uint32_t msix_mmio_readl(void *opaque, 
target_phys_addr_t addr)
 return pci_get_long(page + offset);
 }
 
-static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
-{
-fprintf(stderr, MSI-X: only dword read is allowed!\n);
-return 0;
-}
-
 static uint8_t msix_pending_mask(int vector)
 {
 return 1  (vector % 8);
@@ -169,8 +164,8 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
 }
 }
 
-static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
+uint64_t val, unsigned size)
 {
 PCIDevice *dev = opaque;
 unsigned int offset = addr  (MSIX_PAGE_SIZE - 1)  ~0x3;
@@ -179,37 +174,25 @@ static void msix_mmio_writel(void *opaque, 
target_phys_addr_t addr,
 msix_handle_mask_update(dev, vector);
 }
 
-static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
-  uint32_t val)
-{
-fprintf(stderr, MSI-X: only dword write is allowed!\n);
-}
-
-static CPUWriteMemoryFunc * const msix_mmio_write[] = {
-msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
-};
-
-static CPUReadMemoryFunc * const msix_mmio_read[] = {
-msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
+static const MemoryRegionOps msix_mmio_ops = {
+.read = msix_mmio_read,
+.write = msix_mmio_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+.valid = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
 };
 
-/* Should be called from device's map method. */
-void msix_mmio_map(PCIDevice *d, int region_num,
-   pcibus_t addr, pcibus_t size, int type)
+static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
 {
 uint8_t *config = d-config + d-msix_cap;
 uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
 uint32_t offset = table  ~(MSIX_PAGE_SIZE - 1);
 /* TODO: for assigned devices, we'll want to make it possible to map
  * pending bits separately in case they are in a separate bar. */
-int table_bir = table  PCI_MSIX_FLAGS_BIRMASK;
 
-if (table_bir != region_num)
-return;
-if (size = offset)
-return;
-cpu_register_physical_memory(addr + offset, size - offset,
- d-msix_mmio_index);
+memory_region_add_subregion(bar, offset, d-msix_mmio);
 }
 
 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
@@ -225,6 +208,7 @@ static void msix_mask_all(struct PCIDevice *dev, unsigned 
nentries)
 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
  * modified, it should be retrieved with msix_bar_size. */
 int msix_init(struct PCIDevice *dev, unsigned short nentries,
+

[PATCH v3 32/39] xen-platform: convert to memory API

Since this device bypasses PCI and registers I/O ports directly with
the system bus, it needs further attention.

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/xen_platform.c |   84 -
 1 files changed, 51 insertions(+), 33 deletions(-)

diff --git a/hw/xen_platform.c b/hw/xen_platform.c
index fb6be6a..239eefe 100644
--- a/hw/xen_platform.c
+++ b/hw/xen_platform.c
@@ -32,7 +32,6 @@
 #include xen_common.h
 #include net.h
 #include xen_backend.h
-#include rwhandler.h
 #include trace.h
 
 #include xenguest.h
@@ -51,6 +50,9 @@
 
 typedef struct PCIXenPlatformState {
 PCIDevice  pci_dev;
+MemoryRegion fixed_io;
+MemoryRegion bar;
+MemoryRegion mmio_bar;
 uint8_t flags; /* used only for version_id == 2 */
 int drivers_blacklisted;
 uint16_t driver_product_version;
@@ -221,21 +223,34 @@ static void platform_fixed_ioport_reset(void *opaque)
 platform_fixed_ioport_writeb(s, XEN_PLATFORM_IOPORT, 0);
 }
 
+const MemoryRegionPortio xen_platform_ioport[] = {
+{ 0, 16, 4, .write = platform_fixed_ioport_writel, },
+{ 0, 16, 2, .write = platform_fixed_ioport_writew, },
+{ 0, 16, 1, .write = platform_fixed_ioport_writeb, },
+{ 0, 16, 2, .read = platform_fixed_ioport_readw, },
+{ 0, 16, 1, .read = platform_fixed_ioport_readb, },
+PORTIO_END
+};
+
+static const MemoryRegionOps platform_fixed_io_ops = {
+.old_portio = xen_platform_ioport,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+#include exec-memory.h
+
 static void platform_fixed_ioport_init(PCIXenPlatformState* s)
 {
-register_ioport_write(XEN_PLATFORM_IOPORT, 16, 4, 
platform_fixed_ioport_writel, s);
-register_ioport_write(XEN_PLATFORM_IOPORT, 16, 2, 
platform_fixed_ioport_writew, s);
-register_ioport_write(XEN_PLATFORM_IOPORT, 16, 1, 
platform_fixed_ioport_writeb, s);
-register_ioport_read(XEN_PLATFORM_IOPORT, 16, 2, 
platform_fixed_ioport_readw, s);
-register_ioport_read(XEN_PLATFORM_IOPORT, 16, 1, 
platform_fixed_ioport_readb, s);
+memory_region_init_io(s-fixed_io, platform_fixed_io_ops, s,
+  xen-fixed, 16);
+memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
+s-fixed_io);
 }
 
 /* Xen Platform PCI Device */
 
 static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
 {
-addr = 0xff;
-
 if (addr == 0) {
 return platform_fixed_ioport_readb(opaque, XEN_PLATFORM_IOPORT);
 } else {
@@ -247,9 +262,6 @@ static void xen_platform_ioport_writeb(void *opaque, 
uint32_t addr, uint32_t val
 {
 PCIXenPlatformState *s = opaque;
 
-addr = 0xff;
-val  = 0xff;
-
 switch (addr) {
 case 0: /* Platform flags */
 platform_fixed_ioport_writeb(opaque, XEN_PLATFORM_IOPORT, val);
@@ -262,15 +274,23 @@ static void xen_platform_ioport_writeb(void *opaque, 
uint32_t addr, uint32_t val
 }
 }
 
-static void platform_ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t 
addr, pcibus_t size, int type)
-{
-PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, pci_dev);
+static MemoryRegionPortio xen_pci_portio[] = {
+{ 0, 0x100, 1, .read = xen_platform_ioport_readb, },
+{ 0, 0x100, 1, .write = xen_platform_ioport_writeb, },
+PORTIO_END
+};
+
+static const MemoryRegionOps xen_pci_io_ops = {
+.old_portio = xen_pci_portio,
+};
 
-register_ioport_write(addr, size, 1, xen_platform_ioport_writeb, d);
-register_ioport_read(addr, size, 1, xen_platform_ioport_readb, d);
+static void platform_ioport_bar_setup(PCIXenPlatformState *d)
+{
+memory_region_init_io(d-bar, xen_pci_io_ops, d, xen-pci, 0x100);
 }
 
-static uint32_t platform_mmio_read(ReadWriteHandler *handler, pcibus_t addr, 
int len)
+static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr,
+   unsigned size)
 {
 DPRINTF(Warning: attempted read from physical address 
 0x TARGET_FMT_plx  in xen platform mmio space\n, addr);
@@ -278,28 +298,24 @@ static uint32_t platform_mmio_read(ReadWriteHandler 
*handler, pcibus_t addr, int
 return 0;
 }
 
-static void platform_mmio_write(ReadWriteHandler *handler, pcibus_t addr,
-uint32_t val, int len)
+static void platform_mmio_write(void *opaque, target_phys_addr_t addr,
+uint64_t val, unsigned size)
 {
-DPRINTF(Warning: attempted write of 0x%x to physical 
+DPRINTF(Warning: attempted write of 0x%PRIx64 to physical 
 address 0x TARGET_FMT_plx  in xen platform mmio space\n,
 val, addr);
 }
 
-static ReadWriteHandler platform_mmio_handler = {
+static const MemoryRegionOps platform_mmio_handler = {
 .read = platform_mmio_read,
 .write = platform_mmio_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-static void platform_mmio_map(PCIDevice *d, int region_num,
-

[PATCH v3 28/39] isa-mmio: concert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/isa.h  |2 ++
 hw/isa_mmio.c |   30 +++---
 2 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/hw/isa.h b/hw/isa.h
index d2b6126..f1f2181 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -4,6 +4,7 @@
 /* ISA bus */
 
 #include ioport.h
+#include memory.h
 #include qdev.h
 
 typedef struct ISABus ISABus;
@@ -37,6 +38,7 @@ ISADevice *isa_create_simple(const char *name);
 
 extern target_phys_addr_t isa_mem_base;
 
+void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size);
 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
 
 /* dma.c */
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
index ca957fb..600225f 100644
--- a/hw/isa_mmio.c
+++ b/hw/isa_mmio.c
@@ -58,25 +58,25 @@ static uint32_t isa_mmio_readl(void *opaque, 
target_phys_addr_t addr)
 return cpu_inl(addr  IOPORTS_MASK);
 }
 
-static CPUWriteMemoryFunc * const isa_mmio_write[] = {
-isa_mmio_writeb,
-isa_mmio_writew,
-isa_mmio_writel,
+static const MemoryRegionOps isa_mmio_ops = {
+.old_mmio = {
+.write = { isa_mmio_writeb, isa_mmio_writew, isa_mmio_writel },
+.read = { isa_mmio_readb, isa_mmio_readw, isa_mmio_readl, },
+},
+.endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static CPUReadMemoryFunc * const isa_mmio_read[] = {
-isa_mmio_readb,
-isa_mmio_readw,
-isa_mmio_readl,
-};
+void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size)
+{
+memory_region_init_io(mr, isa_mmio_ops, NULL, isa-mmio, size);
+}
+
+#include exec-memory.h
 
 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
 {
-int isa_mmio_iomemtype;
+MemoryRegion *mr = qemu_malloc(sizeof(*mr));
 
-isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,
-isa_mmio_write,
-NULL,
-DEVICE_LITTLE_ENDIAN);
-cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
+isa_mmio_setup(mr, size);
+memory_region_add_subregion(get_system_memory(), base, mr);
 }
-- 
1.7.5.3

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[PATCH v3 38/39] pci: rename pci_register_bar_region() to pci_register_bar()

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/ac97.c |4 ++--
 hw/cirrus_vga.c   |5 ++---
 hw/e1000.c|5 ++---
 hw/eepro100.c |7 +++
 hw/es1370.c   |2 +-
 hw/ide/cmd646.c   |   14 +-
 hw/ide/ich.c  |2 +-
 hw/ide/piix.c |3 +--
 hw/ide/via.c  |3 +--
 hw/intel-hda.c|2 +-
 hw/ivshmem.c  |   15 +++
 hw/lsi53c895a.c   |7 +++
 hw/macio.c|3 +--
 hw/ne2000.c   |2 +-
 hw/openpic.c  |4 ++--
 hw/pci.c  |6 +++---
 hw/pci.h  |4 ++--
 hw/pcnet-pci.c|4 ++--
 hw/qxl.c  |   16 
 hw/rtl8139.c  |6 ++
 hw/sun4u.c|6 ++
 hw/usb-ehci.c |2 +-
 hw/usb-ohci.c |2 +-
 hw/usb-uhci.c |3 +--
 hw/vga-pci.c  |3 +--
 hw/virtio-pci.c   |9 -
 hw/vmware_vga.c   |8 
 hw/wdt_i6300esb.c |2 +-
 hw/xen_platform.c |7 +++
 29 files changed, 68 insertions(+), 88 deletions(-)

diff --git a/hw/ac97.c b/hw/ac97.c
index bcddaa6..48ad2ec 100644
--- a/hw/ac97.c
+++ b/hw/ac97.c
@@ -1316,8 +1316,8 @@ static int ac97_initfn (PCIDevice *dev)
 
 memory_region_init_io(s-io_nam, ac97_io_nam_ops, s, ac97-nam, 1024);
 memory_region_init_io(s-io_nabm, ac97_io_nabm_ops, s, ac97-nabm, 256);
-pci_register_bar_region(s-dev, 0, PCI_BASE_ADDRESS_SPACE_IO, s-io_nam);
-pci_register_bar_region(s-dev, 1, PCI_BASE_ADDRESS_SPACE_IO, 
s-io_nabm);
+pci_register_bar(s-dev, 0, PCI_BASE_ADDRESS_SPACE_IO, s-io_nam);
+pci_register_bar(s-dev, 1, PCI_BASE_ADDRESS_SPACE_IO, s-io_nabm);
 qemu_register_reset (ac97_on_reset, s);
 AUD_register_card (ac97, s-card);
 ac97_on_reset (s);
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 15ccf4a..033822e 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2949,10 +2949,9 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
  /* memory #0 LFB */
  /* memory #1 memory-mapped I/O */
  /* XXX: s-vga.vram_size must be a power of two */
- pci_register_bar_region(d-dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
- s-pci_bar);
+ pci_register_bar(d-dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, s-pci_bar);
  if (device_id == CIRRUS_ID_CLGD5446) {
- pci_register_bar_region(d-dev, 1, 0, s-cirrus_mmio_io);
+ pci_register_bar(d-dev, 1, 0, s-cirrus_mmio_io);
  }
  return 0;
 }
diff --git a/hw/e1000.c b/hw/e1000.c
index dfc082b..29b453f 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1158,10 +1158,9 @@ static int pci_e1000_init(PCIDevice *pci_dev)
 
 e1000_mmio_setup(d);
 
-pci_register_bar_region(d-dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
-d-mmio);
+pci_register_bar(d-dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, d-mmio);
 
-pci_register_bar_region(d-dev, 1, PCI_BASE_ADDRESS_SPACE_IO, d-io);
+pci_register_bar(d-dev, 1, PCI_BASE_ADDRESS_SPACE_IO, d-io);
 
 memmove(d-eeprom_data, e1000_eeprom_template,
 sizeof e1000_eeprom_template);
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 04723f3..a636d30 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1879,15 +1879,14 @@ static int e100_nic_init(PCIDevice *pci_dev)
 /* Handler for memory-mapped I/O */
 memory_region_init_io(s-mmio_bar, eepro100_ops, s, eepro100-mmio,
   PCI_MEM_SIZE);
-pci_register_bar_region(s-dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
-s-mmio_bar);
+pci_register_bar(s-dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, s-mmio_bar);
 memory_region_init_io(s-io_bar, eepro100_ops, s, eepro100-io,
   PCI_IO_SIZE);
-pci_register_bar_region(s-dev, 1, PCI_BASE_ADDRESS_SPACE_IO, s-io_bar);
+pci_register_bar(s-dev, 1, PCI_BASE_ADDRESS_SPACE_IO, s-io_bar);
 /* FIXME: flash aliases to mmio?! */
 memory_region_init_io(s-flash_bar, eepro100_ops, s, eepro100-flash,
   PCI_FLASH_SIZE);
-pci_register_bar_region(s-dev, 2, 0, s-flash_bar);
+pci_register_bar(s-dev, 2, 0, s-flash_bar);
 
 qemu_macaddr_default_if_unset(s-conf.macaddr);
 logout(macaddr: %s\n, nic_dump(s-conf.macaddr.a[0], 6));
diff --git a/hw/es1370.c b/hw/es1370.c
index 6a01797..f2c2d4d 100644
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -1009,7 +1009,7 @@ static int es1370_initfn (PCIDevice *dev)
 c[PCI_MAX_LAT] = 0x80;
 
 memory_region_init_io(s-io, es1370_io_ops, s, es1370, 256);
-pci_register_bar_region(s-dev, 0, PCI_BASE_ADDRESS_SPACE_IO, s-io);
+pci_register_bar(s-dev, 0, PCI_BASE_ADDRESS_SPACE_IO, s-io);
 qemu_register_reset (es1370_on_reset, s);
 
 AUD_register_card (es1370, s-card);
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 13e6f2f..4d91e2c 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -270,16 +270,12 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
 
 setup_cmd646_bar(d, 0);

[PATCH v3 18/39] ide: convert to memory API

Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
 hw/ide/cmd646.c |  208 +++
 hw/ide/pci.c|   25 ---
 hw/ide/pci.h|   19 -
 hw/ide/piix.c   |   64 +
 hw/ide/via.c|   65 +
 5 files changed, 261 insertions(+), 120 deletions(-)

diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 56302b5..13e6f2f 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -44,35 +44,95 @@
 
 static void cmd646_update_irq(PCIIDEState *d);
 
-static void ide_map(PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
+static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr,
+unsigned size)
 {
-PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
-IDEBus *bus;
-
-if (region_num = 3) {
-bus = d-bus[(region_num  1)];
-if (region_num  1) {
-register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
-register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
+CMD646BAR *cmd646bar = opaque;
+
+if (addr != 2 || size != 1) {
+return ((uint64_t)1  (size * 8)) - 1;
+}
+return ide_status_read(cmd646bar-bus, addr + 2);
+}
+
+static void cmd646_cmd_write(void *opaque, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
+{
+CMD646BAR *cmd646bar = opaque;
+
+if (addr != 2 || size != 1) {
+return;
+}
+ide_cmd_write(cmd646bar-bus, addr + 2, data);
+}
+
+static MemoryRegionOps cmd646_cmd_ops = {
+.read = cmd646_cmd_read,
+.write = cmd646_cmd_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
+{
+CMD646BAR *cmd646bar = opaque;
+
+if (size == 1) {
+return ide_ioport_read(cmd646bar-bus, addr);
+} else if (addr == 0) {
+if (size == 2) {
+return ide_data_readw(cmd646bar-bus, addr);
 } else {
-register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
-register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
-
-/* data ports */
-register_ioport_write(addr, 2, 2, ide_data_writew, bus);
-register_ioport_read(addr, 2, 2, ide_data_readw, bus);
-register_ioport_write(addr, 4, 4, ide_data_writel, bus);
-register_ioport_read(addr, 4, 4, ide_data_readl, bus);
+return ide_data_readl(cmd646bar-bus, addr);
 }
 }
+return ((uint64_t)1  (size * 8)) - 1;
 }
 
-static uint32_t bmdma_readb_common(PCIIDEState *pci_dev, BMDMAState *bm,
-   uint32_t addr)
+static void cmd646_data_write(void *opaque, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
 {
+CMD646BAR *cmd646bar = opaque;
+
+if (size == 1) {
+return ide_ioport_write(cmd646bar-bus, addr, data);
+} else if (addr == 0) {
+if (size == 2) {
+return ide_data_writew(cmd646bar-bus, addr, data);
+} else {
+return ide_data_writel(cmd646bar-bus, addr, data);
+}
+}
+}
+
+static MemoryRegionOps cmd646_data_ops = {
+.read = cmd646_data_read,
+.write = cmd646_data_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
+{
+IDEBus *bus = d-bus[bus_num];
+CMD646BAR *bar = d-cmd646_bar[bus_num];
+
+bar-bus = bus;
+bar-pci_dev = d;
+memory_region_init_io(bar-cmd, cmd646_cmd_ops, bar, cmd646-cmd, 4);
+memory_region_init_io(bar-data, cmd646_data_ops, bar, cmd646-data, 8);
+}
+
+static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
+   unsigned size)
+{
+BMDMAState *bm = opaque;
+PCIIDEState *pci_dev = bm-pci_dev;
 uint32_t val;
 
+if (size != 1) {
+return ((uint64_t)1  (size * 8)) - 1;
+}
+
 switch(addr  3) {
 case 0:
 val = bm-cmd;
@@ -100,31 +160,22 @@ static uint32_t bmdma_readb_common(PCIIDEState *pci_dev, 
BMDMAState *bm,
 return val;
 }
 
-static uint32_t bmdma_readb_0(void *opaque, uint32_t addr)
+static void bmdma_write(void *opaque, target_phys_addr_t addr,
+uint64_t val, unsigned size)
 {
-PCIIDEState *pci_dev = opaque;
-BMDMAState *bm = pci_dev-bmdma[0];
-
-return bmdma_readb_common(pci_dev, bm, addr);
-}
+BMDMAState *bm = opaque;
+PCIIDEState *pci_dev = bm-pci_dev;
 
-static uint32_t bmdma_readb_1(void *opaque, uint32_t addr)
-{
-PCIIDEState *pci_dev = opaque;
-BMDMAState *bm = pci_dev-bmdma[1];
-
-return bmdma_readb_common(pci_dev, bm, addr);
-}
+if (size != 1) {
+return;
+}
 
-static void bmdma_writeb_common(PCIIDEState *pci_dev, BMDMAState *bm,
-uint32_t addr,

Re: [Qemu-devel] [PATCH v1] qmp/hmp: add block_set_io_throttle and enhance query_block

2011-08-04 Thread Stefan Hajnoczi

On Thu, Aug 4, 2011 at 5:34 AM, Zhi Yong Wu wu...@linux.vnet.ibm.com wrote:
 @@ -1387,6 +1422,11 @@ void bdrv_set_io_limits(BlockDriverState *bs,
  {
     memset(bs-io_limits, 0, sizeof(BlockIOLimit));
     bs-io_limits = *io_limits;
 +    if (bdrv_io_limits_enabled(bs)) {
 +        bs-io_limits_enabled = true;
 +    } else {
 +        bs-io_limits_enabled = false;
 +    }

Or in one line:
bs-io_limits_enabled = bdrv_io_limits_enabled(bs);

  }

  /* Recognize floppy formats */
 @@ -1621,6 +1661,7 @@ BlockDriverState *bdrv_find(const char *name)
     return NULL;
  }

 +/* disk I/O throttling */

Looks like this should not be here.

  BlockDriverState *bdrv_next(BlockDriverState *bs)
  {
     if (!bs) {
 @@ -1784,6 +1825,16 @@ static void bdrv_print_dict(QObject *obj, void *opaque)
                             qdict_get_bool(qdict, ro),
                             qdict_get_str(qdict, drv),
                             qdict_get_bool(qdict, encrypted));
 +
 +        monitor_printf(mon,  bps=% PRId64  bps_rd=% PRId64
 +                             bps_wr=% PRId64  iops=% PRId64
 +                             iops_rd=% PRId64  iops_wr=% PRId64,
 +                            qdict_get_int(qdict, bps),
 +                            qdict_get_int(qdict, bps_rd),
 +                            qdict_get_int(qdict, bps_wr),
 +                            qdict_get_int(qdict, iops),
 +                            qdict_get_int(qdict, iops_rd),
 +                            qdict_get_int(qdict, iops_wr));
     } else {
         monitor_printf(mon,  [not inserted]);
     }
 @@ -1816,10 +1867,22 @@ void bdrv_info(Monitor *mon, QObject **ret_data)
             QDict *bs_dict = qobject_to_qdict(bs_obj);

             obj = qobject_from_jsonf({ 'file': %s, 'ro': %i, 'drv': %s, 
 -                                     'encrypted': %i },
 +                                     'encrypted': %i, 
 +                                     'bps': % PRId64 ,
 +                                     'bps_rd': % PRId64 ,
 +                                     'bps_wr': % PRId64 ,
 +                                     'iops': % PRId64 ,
 +                                     'iops_rd': % PRId64 ,
 +                                     'iops_wr': % PRId64 },
                                      bs-filename, bs-read_only,
                                      bs-drv-format_name,
 -                                     bdrv_is_encrypted(bs));
 +                                     bdrv_is_encrypted(bs),
 +                                     bs-io_limits.bps[2],
 +                                     bs-io_limits.bps[0],
 +                                     bs-io_limits.bps[1],
 +                                     bs-io_limits.iops[2],
 +                                     bs-io_limits.iops[0],
 +                                     bs-io_limits.iops[1]);
             if (bs-backing_file[0] != '\0') {
                 QDict *qdict = qobject_to_qdict(obj);
                 qdict_put(qdict, backing_file,
 @@ -2307,7 +2370,7 @@ static bool bdrv_exceed_io_limits(BlockDriverState *bs, 
 int nb_sectors,
     }

     /* If a limit was exceeded, immediately queue this request */
 -    if ((bs-req_from_queue == false)
 +    if (!bs-req_from_queue
          !QTAILQ_EMPTY(bs-block_queue-requests)) {
         if (bs-io_limits.bps[BLOCK_IO_LIMIT_TOTAL]
             || bs-io_limits.bps[is_write] || bs-io_limits.iops[is_write]
 @@ -2362,14 +2425,14 @@ BlockDriverAIOCB *bdrv_aio_readv(BlockDriverState 
 *bs, int64_t sector_num,
     trace_bdrv_aio_readv(bs, sector_num, nb_sectors, opaque);

     if (!drv || bdrv_check_request(bs, sector_num, nb_sectors)) {
 -        if (bdrv_io_limits_enable(bs-io_limits)) {
 +        if (bs-io_limits_enabled) {
             bs-req_from_queue = false;
         }
         return NULL;
     }

     /* throttling disk read I/O */
 -    if (bdrv_io_limits_enable(bs-io_limits)) {
 +    if (bs-io_limits_enabled) {
         if (bdrv_exceed_io_limits(bs, nb_sectors, false, wait_time)) {
             ret = qemu_block_queue_enqueue(bs-block_queue, bs, 
 bdrv_aio_readv,
                               sector_num, qiov, nb_sectors, cb, opaque);
 @@ -2388,14 +2451,14 @@ BlockDriverAIOCB *bdrv_aio_readv(BlockDriverState 
 *bs, int64_t sector_num,
        bs-rd_bytes += (unsigned) nb_sectors * BDRV_SECTOR_SIZE;
        bs-rd_ops ++;

 -        if (bdrv_io_limits_enable(bs-io_limits)) {
 +        if (bs-io_limits_enabled) {
             bs-io_disps.bytes[BLOCK_IO_LIMIT_READ] +=
                               (unsigned) nb_sectors * BDRV_SECTOR_SIZE;
             bs-io_disps.ios[BLOCK_IO_LIMIT_READ]++;
         }
     }

 -    if (bdrv_io_limits_enable(bs-io_limits)) {
 +    if (bs-io_limits_enabled) {
         bs-req_from_queue = false;
     }

 @@ -2451,7 +2514,7 @@ BlockDriverAIOCB *bdrv_aio_writev(BlockDriverState *bs, 
 int64_t sector_num,

     if (!drv || bs-read_only
         || bdrv_check_request(bs, sector_num, nb_sectors))

[PATCH master+STABLE-0.15] Fix default accelerator when configured with --disable-kvm

2011-08-04 Thread Daniel P. Berrange

From: Daniel P. Berrange berra...@redhat.com

The default accelerator is hardcoded to 'kvm'. This is a fine
default for qemu-kvm normally, but if the user built with
./configure --disable-kvm, then the resulting binaries will
not work by default

* vl.c: Default to 'tcg' unless CONFIG_KVM is defined
---
 vl.c |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/vl.c b/vl.c
index 7ae549e..28fd2f3 100644
--- a/vl.c
+++ b/vl.c
@@ -1953,8 +1953,13 @@ static int configure_accelerator(void)
 }
 
 if (p == NULL) {
+#ifdef CONFIG_KVM
 /* Use the default accelerator, kvm */
 p = kvm;
+#else
+/* Use the default accelerator, tcg */
+p = tcg;
+#endif
 }
 
 while (!accel_initalised  *p != '\0') {
-- 
1.7.6

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Re: unconditional CPUID propagation?

2011-08-04 Thread Marcelo Tosatti

On Wed, Aug 03, 2011 at 11:41:42AM +0200, Andre Przywara wrote:
 Hi,
 
 while looking through the code I found commit
 f79116867ec80ed5d1d10043a3fd9ac8afd182c1 (upstream QEMU: enable
 SMEP) which unconditionally propagates the bits from CPUID leaf 0x7
 to the guest. Though there is the KVM module in the line, this
 currently whitelists three feature bits.
 Doesn't that break migration? The result of the CPUID instruction
 the guess issues only depends on the host and the KVM module's
 policy, not on the CPU model QEMU uses. So I guess migrating from a
 newer CPU to an older one breaks despite a rather conservative CPU
 model has been chosen intentionally by the user.
 The same is probably true for the VIA CPUID leaf.
 
 Is that considered OK now or is that a bug? Shall the new feature
 bits be made known to QEMU like the other ones on only enabled
 explicitly (+smep) or by -cpu host?
 I can make a patch for that if that is the right way to address this.

Or if the CPU type supports it, yes.

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[BUG] Qcow2 corruption on snapshot revert

2011-08-04 Thread Philipp Hahn

Hello,

it seems like I have discovered a bug in qemu-0.14.1 which corrupts Qcow2
image files when using internal snapshots.
I tied this both on an amd64 host running our Debian bases UCS distribution
(using pure qemu-kvm_0.14 and pure qemu-kvm_0.14.1) and also on a pure Debian
i386 sid installation (patched qemu-kvm_0.14.1).
I can reproducte this every time doing the following steps:
0. Create and install VM
1. Shut down VM
2. Create offline snapshot using qemu-img snapshot -c Off image.qcow2
3. Start VM
4. Create online snapshot using savevm On
5. Shut down VM
6. Revert to snapshot using qemu-img snapshot -a Off image.qcow2
Repeat step 6 three or more times and the Image is destroyed.

My guess is that this is a but in qemu-img, which is related to having an
online snapshot (VM running) while reverting to an offline snapshot (VM
stopped), because I wasn't able to reproduce this using only offline
snapshots or only online snapshots.

I have attached a shell script to reproduce this bug on all my runs.
* It both happens with kvm-0.14.1 and also with qemu-0.14.1.
* The cache stragtegy writethrough vs. writeback is irrelevant.

The script needs an image nameded pmh_squeeze-0.qcow.bak2 of an VM where you
can login via serial console using root for login and univention for
password. You can use other images as well, as long as you modify the block
device from within the VM. You get get it from
http://download.univention.de/download/temp/qemu-0.14-qcow2/

There you will also find the beginning of a small Python program
called qcow2.py which can be used to dump the structure of an qcow2 file in
some more human readable format with some consistency checking.

Related links:
http://git.kernel.org/?p=virt/kvm/qemu-kvm.git;a=commit;h=e11480db7ff15a9e878f6b3cc1199b439bf7c825
http://git.kernel.org/?p=virt/kvm/qemu-kvm.git;a=commit;h=f0aa7a8b2d518c54430e4382309281b93e51981a
http://lists.gnu.org/archive/html/qemu-devel/2011-04/msg01376.html
https://forge.univention.org/bugzilla/show_bug.cgi?id=1

Any help is appreciated.

Sincerely
Philipp Hahn
--
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Univention GmbHLinux for Your Businessfon: +49 421 22 232- 0
Mary-Somerville-Str.1 D-28359 Bremen fax: +49 421 22 232-99
http://www.univention.de/

1_qemu_qcow2_bug.test
Description: application/shellscript

signature.asc
Description: This is a digitally signed message part.

Re: [BUG] Qcow2 corruption on snapshot revert

2011-08-04 Thread Kevin Wolf

Am 04.08.2011 16:20, schrieb Philipp Hahn:
Hello,

I have attached a shell script to reproduce this bug on all my runs.
* It both happens with kvm-0.14.1 and also with qemu-0.14.1.
* The cache stragtegy writethrough vs. writeback is irrelevant.

The script needs an image nameded pmh_squeeze-0.qcow.bak2 of an VM where
you
can login via serial console using root for login and univention for
password. You can use other images as well, as long as you modify the block
device from within the VM. You get get it from
http://download.univention.de/download/temp/qemu-0.14-qcow2/

Any help is appreciated.

Thanks for the report. This small script seems to be enough to reproduce
the corruption:

qemu-img create -f qcow2 /tmp/sn.qcow2 64M
qemu-img snapshot -c foo /tmp/sn.qcow2
qemu-io -c 'write -b 0 4M' /tmp/sn.qcow2
qemu-img snapshot -a foo /tmp/sn.qcow2

I'll look into the details tomorrow.

Kevin
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Re: [Autotest] [PATCH] KVM Test: Call postprocess_vm before postprocess_image.

2011-08-04 Thread Lucas Meneghel Rodrigues


On 08/04/2011 04:18 AM, fy...@redhat.com wrote:

From: Feng Yangfy...@redhat.com

Current we call postprocess_image befor postprocess_vm.
If exception is thrown in postprocess_image, postprocess_vm will
be skipped. So vm could not be killed, it may fail following case
  in same loop.


Looks good to me, applied, thanks!

http://autotest.kernel.org/changeset/5520


Signed-off-by: Feng Yangfy...@redhat.com
---
  client/virt/virt_env_process.py |   25 -
  1 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/client/virt/virt_env_process.py b/client/virt/virt_env_process.py
index 12918eb..8fd5c21 100644
--- a/client/virt/virt_env_process.py
+++ b/client/virt/virt_env_process.py
@@ -163,7 +163,7 @@ def process_command(test, params, env, command, 
command_timeout,
  raise


-def process(test, params, env, image_func, vm_func):
+def process(test, params, env, image_func, vm_func, vm_first=False):
  
  Pre- or post-process VMs and images according to the instructions in 
params.
  Call image_func for each image listed in params and vm_func for each VM.
@@ -177,13 +177,20 @@ def process(test, params, env, image_func, vm_func):
  # Get list of VMs specified for this test
  for vm_name in params.objects(vms):
  vm_params = params.object_params(vm_name)
-# Get list of images specified for this VM
-for image_name in vm_params.objects(images):
-image_params = vm_params.object_params(image_name)
-# Call image_func for each image
-image_func(test, image_params)
-# Call vm_func for each vm
-vm_func(test, vm_params, env, vm_name)
+if not vm_first:
+# Get list of images specified for this VM
+for image_name in vm_params.objects(images):
+image_params = vm_params.object_params(image_name)
+# Call image_func for each image
+image_func(test, image_params)
+# Call vm_func for each vm
+vm_func(test, vm_params, env, vm_name)
+else:
+vm_func(test, vm_params, env, vm_name)
+for image_name in vm_params.objects(images):
+image_params = vm_params.object_params(image_name)
+image_func(test, image_params)
+


  @error.context_aware
@@ -293,7 +300,7 @@ def postprocess(test, params, env):
  error.context(postprocessing)

  # Postprocess all VMs and images
-process(test, params, env, postprocess_image, postprocess_vm)
+process(test, params, env, postprocess_image, postprocess_vm, 
vm_first=True)

  # Terminate the screendump thread
  global _screendump_thread, _screendump_thread_termination_event


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Re: [Autotest] [PATCH] KVM Test: Remove duplicated _close_sock function calls in kvm_monitor.py

2011-08-04 Thread Lucas Meneghel Rodrigues

On Thu, Aug 4, 2011 at 4:19 AM,  fy...@redhat.com wrote:
 From: Feng Yang fy...@redhat.com

 self._close_sock will be called two times in HumanMonitor.__init__ and
 QMPMonitor.__init__ in exception.

Looks good to me, applied, thanks!

http://autotest.kernel.org/changeset/5521

 Signed-off-by: Feng Yang fy...@redhat.com
 ---
  client/virt/kvm_monitor.py |    3 ---
  1 files changed, 0 insertions(+), 3 deletions(-)

 diff --git a/client/virt/kvm_monitor.py b/client/virt/kvm_monitor.py
 index 3980da8..c96f062 100644
 --- a/client/virt/kvm_monitor.py
 +++ b/client/virt/kvm_monitor.py
 @@ -174,7 +174,6 @@ class HumanMonitor(Monitor):
             # Find the initial (qemu) prompt
             s, o = self._read_up_to_qemu_prompt(20)
             if not s:
 -                self._close_sock()
                 raise MonitorProtocolError(Could not find (qemu) prompt 
                                            after connecting to monitor. 
                                            Output so far: %r % o)
 @@ -432,7 +431,6 @@ class QMPMonitor(Monitor):
             try:
                 json
             except NameError:
 -                self._close_sock()
                 raise MonitorNotSupportedError(QMP requires the json module 
                                                (Python 2.6 and up))

 @@ -447,7 +445,6 @@ class QMPMonitor(Monitor):
                     break
                 time.sleep(0.1)
             else:
 -                self._close_sock()
                 raise MonitorProtocolError(No QMP greeting message received)

             # Issue qmp_capabilities
 --
 1.7.1

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Re: [Autotest] [PATCH] KVM Test: Drop sre module in script and use re module.

2011-08-04 Thread Lucas Meneghel Rodrigues

On Thu, Aug 4, 2011 at 4:20 AM,  fy...@redhat.com wrote:
 From: Feng Yang fy...@redhat.com

Looks good to me, applied, thanks!

http://autotest.kernel.org/changeset/5522

 sre moudle have been deprecated in python 2.6

 Signed-off-by: Feng Yang fy...@redhat.com
 ---
  client/virt/virt_test_setup.py |    4 ++--
  1 files changed, 2 insertions(+), 2 deletions(-)

 diff --git a/client/virt/virt_test_setup.py b/client/virt/virt_test_setup.py
 index 1539cac..f2ff38b 100644
 --- a/client/virt/virt_test_setup.py
 +++ b/client/virt/virt_test_setup.py
 @@ -1,7 +1,7 @@
  
  Library to perform pre/post test setup for KVM autotest.
  
 -import os, logging, time, re, sre, random
 +import os, logging, time, re, random
  from autotest_lib.client.common_lib import error
  from autotest_lib.client.bin import utils

 @@ -60,7 +60,7 @@ class TransparentHugePageConfig(object):
             tmp_list = re.split(';', test_config)
         while len(tmp_list)  0:
             tmp_cfg = tmp_list.pop()
 -            test_cfg[re.split(:, tmp_cfg)[0]] = sre.split(:, tmp_cfg)[1]
 +            test_cfg[re.split(:, tmp_cfg)[0]] = re.split(:, tmp_cfg)[1]
         # Save host current config, so we can restore it during cleanup
         # We will only save the writeable part of the config files
         original_config = {}
 --
 1.7.1

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Re: [PATCH] KVM Test: Call postprocess_vm before postprocess_image.

2011-08-04 Thread Amos Kong

On Thu, Aug 04, 2011 at 03:18:30PM +0800, fy...@redhat.com wrote:
 From: Feng Yang fy...@redhat.com
 
 Current we call postprocess_image befor postprocess_vm.
 If exception is thrown in postprocess_image, postprocess_vm will
 be skipped. So vm could not be killed, it may fail following case
  in same loop.
 
 Signed-off-by: Feng Yang fy...@redhat.com
 ---
  client/virt/virt_env_process.py |   25 -
  1 files changed, 16 insertions(+), 9 deletions(-)
 
 diff --git a/client/virt/virt_env_process.py b/client/virt/virt_env_process.py
 index 12918eb..8fd5c21 100644
 --- a/client/virt/virt_env_process.py
 +++ b/client/virt/virt_env_process.py
 @@ -163,7 +163,7 @@ def process_command(test, params, env, command, 
 command_timeout,
  raise
  
  
 -def process(test, params, env, image_func, vm_func):
 +def process(test, params, env, image_func, vm_func, vm_first=False):
  
  Pre- or post-process VMs and images according to the instructions in 
 params.
  Call image_func for each image listed in params and vm_func for each VM.
 @@ -177,13 +177,20 @@ def process(test, params, env, image_func, vm_func):
  # Get list of VMs specified for this test
  for vm_name in params.objects(vms):
  vm_params = params.object_params(vm_name)
 -# Get list of images specified for this VM
 -for image_name in vm_params.objects(images):
 -image_params = vm_params.object_params(image_name)
 -# Call image_func for each image
 -image_func(test, image_params)
 -# Call vm_func for each vm
 -vm_func(test, vm_params, env, vm_name)
 +if not vm_first:
 +# Get list of images specified for this VM
 +for image_name in vm_params.objects(images):
 +image_params = vm_params.object_params(image_name)
 +# Call image_func for each image
 +image_func(test, image_params)
 +# Call vm_func for each vm
 +vm_func(test, vm_params, env, vm_name)
 +else:
 +vm_func(test, vm_params, env, vm_name)
 +for image_name in vm_params.objects(images):
 +image_params = vm_params.object_params(image_name)
 +image_func(test, image_params)
 +

 if vm_first:
 vm_func(test, vm_params, env, vm_name)

 # Get list of images specified for this VM
 for image_name in vm_params.objects(images):
 image_params = vm_params.object_params(image_name)
 # Call image_func for each image
 image_func(test, image_params)

 if not vm_first:
 vm_func(test, vm_params, env, vm_name)


However, I'm ok for Feng's fix.
Acked-by: Amos Kong ak...@redhat.com

  @error.context_aware
 @@ -293,7 +300,7 @@ def postprocess(test, params, env):
  error.context(postprocessing)
  
  # Postprocess all VMs and images
 -process(test, params, env, postprocess_image, postprocess_vm)
 +process(test, params, env, postprocess_image, postprocess_vm, 
 vm_first=True)
  
  # Terminate the screendump thread
  global _screendump_thread, _screendump_thread_termination_event
 -- 
 1.7.1
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Re: [RFC PATCH 0/3] Avoid soft lockup message when KVM is stopped by host

2011-08-04 Thread Marcelo Tosatti

On Wed, Aug 03, 2011 at 10:24:58AM -0400, Eric B Munson wrote:
 This set is just a rough first pass at avoiding soft lockup warnings when a 
 host
 pauses the execution of a guest.  A flag is set by the host in the shared page
 used for the pvclock when the host goes to stop the guest.  When the guest
 resumes and detects a soft lockup, this flag is checked and cleared and the 
 soft
 lockup message is skipped.
 
 This currently breaks the build for non-x86 architectures but part of what I 
 am
 looking for here is how to go about adding the function stubs for everything
 else.

To fix this, you can save/restore the offset added to kvmclock on
vmstop/vmstart. See hw/kvmclock.c in the qemu source tree.

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[Bug 40542] New: overflow/panic on KVM hipervizor

https://bugzilla.kernel.org/show_bug.cgi?id=40542

   Summary: overflow/panic on KVM hipervizor
   Product: Virtualization
   Version: unspecified
Kernel Version: 3.0.0
  Platform: All
OS/Version: Linux
  Tree: Mainline
Status: NEW
  Severity: high
  Priority: P1
 Component: kvm
AssignedTo: virtualization_...@kernel-bugs.osdl.org
ReportedBy: sla...@rozbicki.eu
Regression: No


Created an attachment (id=67522)
 -- (https://bugzilla.kernel.org/attachment.cgi?id=67522)
some debug info like /proc/cpuinfo and .config from kernel

I have 2 machines virtualized with KVM on Gentoo host. There is a gentoo and
win2k8r2 guests (there is apache2 on gentoo which connects with php to mssql
server on the second guest). 

During the apache benchmark (ab -c 50 -n 10 http://address/), hipervisor
TCP stack crashes (not entirely, but random anomalies are noticed for example
iptables -Lnv makes ssh session crashed). Here is kern.log snap:

---
 Aug  4 18:54:46 flu kernel: general protection fault:  [#1] SMP
Aug  4 18:54:46 flu kernel: CPU 0
Aug  4 18:54:46 flu kernel: Modules linked in: bridge stp llc kvm_intel kvm
Aug  4 18:54:46 flu kernel:
Aug  4 18:54:46 flu kernel: Pid: 4327, comm: bash Not tainted
3.0.0--std-ipv4-64 #7 Supermicro X8STi/X8STi
Aug  4 18:54:46 flu kernel: RIP: 0010:[810f8aaa] 
[810f8aaa] fget_light+0x6a/0xc0
Aug  4 18:54:46 flu kernel: RSP: 0018:880579015f38  EFLAGS: 00010202
Aug  4 18:54:46 flu kernel: RAX: 8806196fa180 RBX: 7fffdade98f0 RCX:
0008
Aug  4 18:54:46 flu kernel: RDX: 880618ffac80 RSI: 880579015f54 RDI:
880618fc77f8
Aug  4 18:54:46 flu kernel: RBP: 880579015f38 R08:  R09:

Aug  4 18:54:46 flu kernel: R10: 0008 R11: 0246 R12:
00ff
Aug  4 18:54:46 flu kernel: R13: 5410 R14: 7fffdade985c R15:
007b6ae0
Aug  4 18:54:46 flu kernel: FS:  7f495700d700()
GS:88063fc0() knlGS:
Aug  4 18:54:46 flu kernel: CS:  0010 DS:  ES:  CR0: 80050033
Aug  4 18:54:46 flu kernel: CR2: 004620d0 CR3: 00057927b000 CR4:
26e0
Aug  4 18:54:46 flu kernel: DR0:  DR1:  DR2:

Aug  4 18:54:46 flu kernel: DR3:  DR6: 0ff0 DR7:
0400
Aug  4 18:54:46 flu kernel: Process bash (pid: 4327, threadinfo
880579014000, task 88061aacc750)
Aug  4 18:54:46 flu kernel: Stack:
Aug  4 18:54:46 flu kernel: 880579015f78 8110786a 0001

Aug  4 18:54:46 flu kernel: 7fffdade98f0 0082 7fffdade9990

Aug  4 18:54:46 flu kernel: 10e7 818fe2fb 0246
0008
Aug  4 18:54:46 flu kernel: Call Trace:
Aug  4 18:54:46 flu kernel: [8110786a] sys_ioctl+0x2a/0x80
Aug  4 18:54:46 flu kernel: [818fe2fb] system_call_fastpath+0x16/0x1b
Aug  4 18:54:46 flu kernel: Code: 74 37 31 d2 48 89 d0 c9 c3 0f 1f 84 00 00 00
00 00 48 8b 40 08 3b 38 73 e9 89 ff 48 c1 e7 03 48 03 78 08 48 8b 17 48 85 d2
74 d9 f6 42 3d 40 75 d1 48 89 d0 c9 c3 0f 1f 00 48 8b 7a 30 4c 8d 42
Aug  4 18:54:46 flu kernel: RIP  [810f8aaa] fget_light+0x6a/0xc0
Aug  4 18:54:46 flu kernel: RSP 880579015f38
Aug  4 18:54:46 flu kernel: ---[ end trace 9de898b3d5b9d4c6 ]---
Aug  4 18:54:46 flu kernel: general protection fault:  [#2] SMP
Aug  4 18:54:46 flu kernel: CPU 0
Aug  4 18:54:46 flu kernel: Modules linked in: bridge stp llc kvm_intel kvm
Aug  4 18:54:46 flu kernel:
Aug  4 18:54:46 flu kernel: Pid: 4327, comm: bash Tainted: G  D
3.0.0--std-ipv4-64 #7 Supermicro X8STi/X8STi
Aug  4 18:54:46 flu kernel: RIP: 0010:[810f5567] 
[810f5567] filp_close+0x17/0x90
Aug  4 18:54:46 flu kernel: RSP: 0018:880579015cc8  EFLAGS: 00010282
Aug  4 18:54:46 flu kernel: RAX: 880618fc77f8 RBX: 880618ffac80 RCX:
8806196fa240
Aug  4 18:54:46 flu kernel: RDX:  RSI: 880619648140 RDI:
880618ffac80
Aug  4 18:54:46 flu kernel: RBP: 880579015ce8 R08:  R09:

Aug  4 18:54:46 flu kernel: R10: 88061875c090 R11: 0446 R12:
0001
Aug  4 18:54:46 flu kernel: R13: 8806196fa180 R14: 880619648140 R15:
00ff
Aug  4 18:54:46 flu kernel: FS:  ()
GS:88063fc0() knlGS:
Aug  4 18:54:46 flu kernel: CS:  0010 DS:  ES:  CR0: 80050033
Aug  4 18:54:46 flu kernel: CR2: 004620d0 CR3: 01b93000 CR4:
26e0
Aug  4 18:54:46 flu kernel: DR0:  DR1:  DR2:

Aug  4 18:54:46 flu kernel: DR3:  DR6: 0ff0 DR7:
0400
Aug  4 18:54:46 flu kernel: Process bash (pid: 4327,

[Bug 40542] overflow/panic on KVM hipervizor

https://bugzilla.kernel.org/show_bug.cgi?id=40542





--- Comment #1 from Slawek Rozbicki sla...@rozbicki.eu  2011-08-04 17:24:03 
---
moreover, hardware tests were done. Looks like cpu, hdd and ram aren't faulty.

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[Bug 40542] overflow/panic on KVM hipervizor

https://bugzilla.kernel.org/show_bug.cgi?id=40542





--- Comment #2 from Slawek Rozbicki sla...@rozbicki.eu  2011-08-04 17:33:52 
---
http port is DNATed by iptables to gentoo guest on tap virtio adapter.

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[Bug 40542] overflow/panic on KVM hipervizor

https://bugzilla.kernel.org/show_bug.cgi?id=40542





--- Comment #3 from Slawek Rozbicki sla...@rozbicki.eu  2011-08-04 17:58:18 
---
Created an attachment (id=67532)
 -- (https://bugzilla.kernel.org/attachment.cgi?id=67532)
/etc/conf.d/net (network configuration)

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Re: Inter-Domain Communication in KVM

2011-08-04 Thread Boris Dolgov

Hi,

On Wed, Aug 3, 2011 at 08:13, Sam zgu...@gmail.com wrote:
 Dear KVM Gurus:

  I am developing a system on KVM with 2 guest OSes: one is a
 real-time operating system without a TCP/IP stack; the other is Linux.
 What's the easiest method for inter-domain communication? I am aware
 of  Nahanni for shared memory communication in KVM, but it requires a
 PCI device driver. Is there any other method with minimum development
 effort?
You can try using a serial port connected to a named pipe.

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Re: [RFC PATCH 0/3] Avoid soft lockup message when KVM is stopped by host

2011-08-04 Thread Anthony Liguori


On 08/04/2011 03:37 AM, Dor Laor wrote:

On 08/03/2011 05:24 PM, Eric B Munson wrote:

This set is just a rough first pass at avoiding soft lockup warnings
when a host
pauses the execution of a guest. A flag is set by the host in the
shared page
used for the pvclock when the host goes to stop the guest. When the guest
resumes and detects a soft lockup, this flag is checked and cleared
and the soft
lockup message is skipped.


While this will cover the case were the host stops a guest, there will
be other plain cases where the host is just over committed and will
cause a softlockup false positive on the guest.

Softlockup should use stolen time that makes use of the guest running
info would cover both cases


At least in the current steal time implementation, there are numerous 
cases where steal time is not accounted but you'd hit a soft lockup.


Pausing an idle guest via (qemu) stop is an example.  Likewise, a guest 
that is descheduled while idle but then not scheduled for prolonged 
periods of time would also not be accounted as steal time.


Regards,

Anthony Liguori
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Re: qemu-kvm aborts - vhost_dev_unassign_memory: Assertion `to = 0' failed.

2011-08-04 Thread David Ahern



On 08/03/2011 09:00 AM, Michael S. Tsirkin wrote:
 On Wed, Aug 03, 2011 at 07:55:47AM -0600, David Ahern wrote:
 Tested-by: David Ahern daah...@cisco.com

 David
 
 Applied, thanks very much.
 

I assume this will make 0.15 since it is a regression? haven't seen the
patch applied to that branch yet.

David
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Re: qemu-kvm aborts - vhost_dev_unassign_memory: Assertion `to = 0' failed.

2011-08-04 Thread Michael S. Tsirkin

On Thu, Aug 04, 2011 at 12:48:49PM -0600, David Ahern wrote:
 
 
 On 08/03/2011 09:00 AM, Michael S. Tsirkin wrote:
  On Wed, Aug 03, 2011 at 07:55:47AM -0600, David Ahern wrote:
  Tested-by: David Ahern daah...@cisco.com
 
  David
  
  Applied, thanks very much.
  
 
 I assume this will make 0.15 since it is a regression?

How is this a regression in 0.15? I thought it's an old bug
exposed by the memory API which I expect is not going into 0.15.

 haven't seen the
 patch applied to that branch yet.
 
 David

My branch will have to get merged in trunk first.

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Re: qemu-kvm aborts - vhost_dev_unassign_memory: Assertion `to = 0' failed.

2011-08-04 Thread David Ahern



On 08/04/2011 01:17 PM, Michael S. Tsirkin wrote:
 On Thu, Aug 04, 2011 at 12:48:49PM -0600, David Ahern wrote:


 On 08/03/2011 09:00 AM, Michael S. Tsirkin wrote:
 On Wed, Aug 03, 2011 at 07:55:47AM -0600, David Ahern wrote:
 Tested-by: David Ahern daah...@cisco.com

 David

 Applied, thanks very much.


 I assume this will make 0.15 since it is a regression?
 
 How is this a regression in 0.15? I thought it's an old bug
 exposed by the memory API which I expect is not going into 0.15.

Is qemu-kvm.git not tagged as 0.15 rc?

David

 
 haven't seen the
 patch applied to that branch yet.

 David
 
 My branch will have to get merged in trunk first.
 
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Re: [PATCH master+STABLE-0.15] Fix default accelerator when configured with --disable-kvm

2011-08-04 Thread Marcelo Tosatti

On Thu, Aug 04, 2011 at 03:02:24PM +0100, Daniel P. Berrange wrote:
 From: Daniel P. Berrange berra...@redhat.com
 
 The default accelerator is hardcoded to 'kvm'. This is a fine
 default for qemu-kvm normally, but if the user built with
 ./configure --disable-kvm, then the resulting binaries will
 not work by default

Signed-off-by, please.

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Re: [RFC PATCH]vhost-blk: In-kernel accelerator for virtio block device

2011-08-04 Thread Badari Pulavarty

Hi Liu Yuan,

I started testing your patches. I applied your kernel patch to 3.0
and applied QEMU to latest git.

I passed 6 blockdevices from the host to guest (4 vcpu, 4GB RAM). 
I ran simple dd read tests from the guest on all block devices 
(with various blocksizes, iflag=direct).

Unfortunately, system doesn't stay up. I immediately get into
panic on the host. I didn't get time to debug the problem. Wondering
if you have seen this issue before and/or you have new patchset
to try ?

Let me know.

Thanks,
Badari

[ cut here ]
kernel BUG at mm/slab.c:3059!
invalid opcode:  [#1] SMP 
CPU 7 
Modules linked in: vhost_blk ebtable_nat ebtables xt_CHECKSUM bridge stp llc 
autofs4 sunrpc cpufreq_ondemand acpi_cpufreq freq_table mperf cachefiles 
fscache ipt_REJECT ip6t_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_state 
nf_conntrack ip6table_filter ip6_tables ipv6 dm_mirror dm_region_hash dm_log 
dm_round_robin scsi_dh_rdac dm_multipath vhost_net macvtap macvlan tun 
kvm_intel kvm cdc_ether usbnet mii microcode serio_raw pcspkr i2c_i801 i2c_core 
iTCO_wdt iTCO_vendor_support shpchp ioatdma dca i7core_edac edac_core bnx2 sg 
ext4 mbcache jbd2 sd_mod crc_t10dif qla2xxx scsi_transport_fc scsi_tgt mptsas 
mptscsih mptbase scsi_transport_sas dm_mod [last unloaded: nf_defrag_ipv4]

Pid: 2744, comm: vhost-2698 Not tainted 3.0.0 #2 IBM  -[7870AC1]-/46M0761 
RIP: 0010:[8114932c]  [8114932c] 
cache_alloc_refill+0x22c/0x250
RSP: 0018:880258c87d00  EFLAGS: 00010046
RAX: 0002 RBX: 88027f800040 RCX: dead00200200
RDX: 880271128000 RSI: 0070 RDI: 88026eb6c000
RBP: 880258c87d50 R08: 880271128000 R09: 0003
R10: 00021fff R11: 88026b5790c0 R12: 880272cd8c00
R13: 88027f822440 R14: 0002 R15: 88026eb6c000
FS:  () GS:88027fce() knlGS:
CS:  0010 DS:  ES:  CR0: 8005003b
CR2: 00ecb100 CR3: 000270bfe000 CR4: 26e0
DR0:  DR1:  DR2: 
DR3:  DR6: 0ff0 DR7: 0400
Process vhost-2698 (pid: 2744, threadinfo 880258c86000, task 
8802703154c0)
Stack:
 88020002 000492d0 88027f822460 88027f822450
 880258c87d60 88027f800040  80d0
 80d0 0246 880258c87da0 81149c82
Call Trace:
 [81149c82] kmem_cache_alloc_trace+0x182/0x190
 [a0252f52] handle_guest_kick+0x162/0x799 [vhost_blk]
 [a02514ab] vhost_worker+0xcb/0x150 [vhost_blk]
 [a02513e0] ? vhost_dev_set_owner+0x190/0x190 [vhost_blk]
 [a02513e0] ? vhost_dev_set_owner+0x190/0x190 [vhost_blk]
 [81084c66] kthread+0x96/0xa0
 [814d2f84] kernel_thread_helper+0x4/0x10
 [81084bd0] ? kthread_worker_fn+0x1a0/0x1a0
 [814d2f80] ? gs_change+0x13/0x13
Code: 48 89 df e8 07 fb ff ff 65 8b 14 25 58 dc 00 00 85 c0 48 63 d2 4c 8b 24 
d3 74 16 41 83 3c 24 00 0f 84 fc fd ff ff e9 75 ff ff ff 0f 0b 66 90 eb fc 31 
c0 41 83 3c 24 00 0f 85 62 ff ff ff 90 e9 
RIP  [8114932c] cache_alloc_refill+0x22c/0x250
 RSP 880258c87d00
---[ end trace e286566e512cba7b ]---







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Re: [Qemu-devel] [PATCH v1] qmp/hmp: add block_set_io_throttle and enhance query_block

On Thu, Aug 4, 2011 at 9:07 PM, Stefan Hajnoczi stefa...@gmail.com wrote:
 On Thu, Aug 4, 2011 at 5:34 AM, Zhi Yong Wu wu...@linux.vnet.ibm.com wrote:
 @@ -1387,6 +1422,11 @@ void bdrv_set_io_limits(BlockDriverState *bs,
  {
     memset(bs-io_limits, 0, sizeof(BlockIOLimit));
     bs-io_limits = *io_limits;
 +    if (bdrv_io_limits_enabled(bs)) {
 +        bs-io_limits_enabled = true;
 +    } else {
 +        bs-io_limits_enabled = false;
 +    }

 Or in one line:
 bs-io_limits_enabled = bdrv_io_limits_enabled(bs);
nice.

  }

  /* Recognize floppy formats */
 @@ -1621,6 +1661,7 @@ BlockDriverState *bdrv_find(const char *name)
     return NULL;
  }

 +/* disk I/O throttling */

 Looks like this should not be here.\
Let me check when i will go to office next week.

  BlockDriverState *bdrv_next(BlockDriverState *bs)
  {
     if (!bs) {
 @@ -1784,6 +1825,16 @@ static void bdrv_print_dict(QObject *obj, void 
 *opaque)
                             qdict_get_bool(qdict, ro),
                             qdict_get_str(qdict, drv),
                             qdict_get_bool(qdict, encrypted));
 +
 +        monitor_printf(mon,  bps=% PRId64  bps_rd=% PRId64
 +                             bps_wr=% PRId64  iops=% PRId64
 +                             iops_rd=% PRId64  iops_wr=% PRId64,
 +                            qdict_get_int(qdict, bps),
 +                            qdict_get_int(qdict, bps_rd),
 +                            qdict_get_int(qdict, bps_wr),
 +                            qdict_get_int(qdict, iops),
 +                            qdict_get_int(qdict, iops_rd),
 +                            qdict_get_int(qdict, iops_wr));
     } else {
         monitor_printf(mon,  [not inserted]);
     }
 @@ -1816,10 +1867,22 @@ void bdrv_info(Monitor *mon, QObject **ret_data)
             QDict *bs_dict = qobject_to_qdict(bs_obj);

             obj = qobject_from_jsonf({ 'file': %s, 'ro': %i, 'drv': %s, 
 -                                     'encrypted': %i },
 +                                     'encrypted': %i, 
 +                                     'bps': % PRId64 ,
 +                                     'bps_rd': % PRId64 ,
 +                                     'bps_wr': % PRId64 ,
 +                                     'iops': % PRId64 ,
 +                                     'iops_rd': % PRId64 ,
 +                                     'iops_wr': % PRId64 },
                                      bs-filename, bs-read_only,
                                      bs-drv-format_name,
 -                                     bdrv_is_encrypted(bs));
 +                                     bdrv_is_encrypted(bs),
 +                                     bs-io_limits.bps[2],
 +                                     bs-io_limits.bps[0],
 +                                     bs-io_limits.bps[1],
 +                                     bs-io_limits.iops[2],
 +                                     bs-io_limits.iops[0],
 +                                     bs-io_limits.iops[1]);
             if (bs-backing_file[0] != '\0') {
                 QDict *qdict = qobject_to_qdict(obj);
                 qdict_put(qdict, backing_file,
 @@ -2307,7 +2370,7 @@ static bool bdrv_exceed_io_limits(BlockDriverState 
 *bs, int nb_sectors,
     }

     /* If a limit was exceeded, immediately queue this request */
 -    if ((bs-req_from_queue == false)
 +    if (!bs-req_from_queue
          !QTAILQ_EMPTY(bs-block_queue-requests)) {
         if (bs-io_limits.bps[BLOCK_IO_LIMIT_TOTAL]
             || bs-io_limits.bps[is_write] || bs-io_limits.iops[is_write]
 @@ -2362,14 +2425,14 @@ BlockDriverAIOCB *bdrv_aio_readv(BlockDriverState 
 *bs, int64_t sector_num,
     trace_bdrv_aio_readv(bs, sector_num, nb_sectors, opaque);

     if (!drv || bdrv_check_request(bs, sector_num, nb_sectors)) {
 -        if (bdrv_io_limits_enable(bs-io_limits)) {
 +        if (bs-io_limits_enabled) {
             bs-req_from_queue = false;
         }
         return NULL;
     }

     /* throttling disk read I/O */
 -    if (bdrv_io_limits_enable(bs-io_limits)) {
 +    if (bs-io_limits_enabled) {
         if (bdrv_exceed_io_limits(bs, nb_sectors, false, wait_time)) {
             ret = qemu_block_queue_enqueue(bs-block_queue, bs, 
 bdrv_aio_readv,
                               sector_num, qiov, nb_sectors, cb, opaque);
 @@ -2388,14 +2451,14 @@ BlockDriverAIOCB *bdrv_aio_readv(BlockDriverState 
 *bs, int64_t sector_num,
        bs-rd_bytes += (unsigned) nb_sectors * BDRV_SECTOR_SIZE;
        bs-rd_ops ++;

 -        if (bdrv_io_limits_enable(bs-io_limits)) {
 +        if (bs-io_limits_enabled) {
             bs-io_disps.bytes[BLOCK_IO_LIMIT_READ] +=
                               (unsigned) nb_sectors * BDRV_SECTOR_SIZE;
             bs-io_disps.ios[BLOCK_IO_LIMIT_READ]++;
         }
     }

 -    if (bdrv_io_limits_enable(bs-io_limits)) {
 +    if (bs-io_limits_enabled) {
         bs-req_from_queue = false;
     }

 @@ -2451,7 +2514,7 @@ BlockDriverAIOCB

Re: [Qemu-devel] [PATCH v4 0/3] The intro for QEMU disk I/O limits

On Tue, Aug 2, 2011 at 4:06 AM, Ryan Harper ry...@us.ibm.com wrote:
 * Zhi Yong Wu wu...@linux.vnet.ibm.com [2011-08-01 01:30]:
 The main goal of the patch is to effectively cap the disk I/O speed or 
 counts of one single VM.It is only one draft, so it unavoidably has some 
 drawbacks, if you catch them, please let me know.

 The patch will mainly introduce one block I/O throttling algorithm, one 
 timer and one block queue for each I/O limits enabled drive.

 When a block request is coming in, the throttling algorithm will check if 
 its I/O rate or counts exceed the limits; if yes, then it will enqueue to 
 the block queue; The timer will handle the I/O requests in it.

 Some available features follow as below:
 (1) global bps limit.
     -drive bps=xxx            in bytes/s
 (2) only read bps limit
     -drive bps_rd=xxx         in bytes/s
 (3) only write bps limit
     -drive bps_wr=xxx         in bytes/s
 (4) global iops limit
     -drive iops=xxx           in ios/s
 (5) only read iops limit
     -drive iops_rd=xxx        in ios/s
 (6) only write iops limit
     -drive iops_wr=xxx        in ios/s
 (7) the combination of some limits.
     -drive bps=xxx,iops=xxx

 Known Limitations:
 (1) #1 can not coexist with #2, #3
 (2) #4 can not coexist with #5, #6
 (3) When bps/iops limits are specified to a small value such as 511 bytes/s, 
 this VM will hang up. We are considering how to handle this senario.


 Zhi Yong Wu (3):
   v4: fix memory leaking based on ryan's feedback.

 It looks like the leak has been fixed, but I think we need to rework how
 the blk-queue is using the AIOPool.  I'll reply to that patch.
OK. Look forward to seeing it.



 --
 Ryan Harper
 Software Engineer; Linux Technology Center
 IBM Corp., Austin, Tx
 ry...@us.ibm.com




-- 
Regards,

Zhi Yong Wu
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Re: [Qemu-devel] [PATCH v4 3/3] The support for queue timer and throttling algorithm

On Tue, Aug 2, 2011 at 4:39 AM, Ryan Harper ry...@us.ibm.com wrote:
 * Zhi Yong Wu wu...@linux.vnet.ibm.com [2011-08-01 01:32]:
 Note:
       1.) When bps/iops limits are specified to a small value such as 511 
 bytes/s, this VM will hang up. We are considering how to handle this senario.
       2.) When dd command is issued in guest, if its option bs is set to a 
 large value such as bs=1024K, the result speed will slightly bigger than 
 the limits.

 For these problems, if you have nice thought, pls let us know.:)

 Signed-off-by: Zhi Yong Wu wu...@linux.vnet.ibm.com
 ---
  block.c     |  302 
 +--
  block.h     |    1 -
  block_int.h |   29 ++
  3 files changed, 323 insertions(+), 9 deletions(-)

 diff --git a/block.c b/block.c
 index 24a25d5..42763a3 100644
 --- a/block.c
 +++ b/block.c
 @@ -29,6 +29,9 @@
  #include module.h
  #include qemu-objects.h

 +#include qemu-timer.h
 +#include block/blk-queue.h
 +
  #ifdef CONFIG_BSD
  #include sys/types.h
  #include sys/stat.h
 @@ -58,6 +61,13 @@ static int bdrv_read_em(BlockDriverState *bs, int64_t 
 sector_num,
  static int bdrv_write_em(BlockDriverState *bs, int64_t sector_num,
                           const uint8_t *buf, int nb_sectors);

 +static bool bdrv_exceed_bps_limits(BlockDriverState *bs, int nb_sectors,
 +        bool is_write, double elapsed_time, uint64_t *wait);
 +static bool bdrv_exceed_iops_limits(BlockDriverState *bs, bool is_write,
 +        double elapsed_time, uint64_t *wait);
 +static bool bdrv_exceed_io_limits(BlockDriverState *bs, int nb_sectors,
 +        bool is_write, uint64_t *wait);
 +
  static QTAILQ_HEAD(, BlockDriverState) bdrv_states =
      QTAILQ_HEAD_INITIALIZER(bdrv_states);

 @@ -90,6 +100,20 @@ int is_windows_drive(const char *filename)
  }
  #endif

 +static int bdrv_io_limits_enable(BlockIOLimit *io_limits)
 +{
 +    if ((io_limits-bps[0] == 0)
 +          (io_limits-bps[1] == 0)
 +          (io_limits-bps[2] == 0)
 +          (io_limits-iops[0] == 0)
 +          (io_limits-iops[1] == 0)
 +          (io_limits-iops[2] == 0)) {
 +        return 0;


 I'd add a field to BlockIOLimit structure, and just do:

  static int bdrv_io_limits_enabled(BlockIOLimit *io_limits)
  {
       return io_limist-enabled;
  }

 Update bdrv_set_io_limits() to do the original check you have, and if
 one of the fields is set, update the enabled flag.

 We incur that logic on *every* request, so let's make it as cheap as
 possible.
Good point, it has been adopted in qmp/hmp patch.

 +    }
 +
 +    return 1;
 +}
 +
  /* check if the path starts with protocol: */
  static int path_has_protocol(const char *path)
  {
 @@ -167,6 +191,28 @@ void path_combine(char *dest, int dest_size,
      }
  }

 +static void bdrv_block_timer(void *opaque)
 +{
 +    BlockDriverState *bs = opaque;
 +    BlockQueue *queue = bs-block_queue;
 +
 +    while (!QTAILQ_EMPTY(queue-requests)) {
 +        BlockIORequest *request = NULL;
 +        int ret = 0;
 +
 +        request = QTAILQ_FIRST(queue-requests);
 +        QTAILQ_REMOVE(queue-requests, request, entry);
 +
 +        ret = qemu_block_queue_handler(request);
 +        if (ret == 0) {
 +            QTAILQ_INSERT_HEAD(queue-requests, request, entry);
 +            break;

 btw, I did some tracing and I never saw a request get re-added here.
 Now, ideally, I think you were try to do the following:

 The request is coming from the queue, if we exceed our limits, then we'd
 get back NULL from the handler and we'd requeue the request at the
Right.
 head... but that doesn't actually happen.
It could take place. For example, if block req1 comes, it exceed the
limits, the block timer is set to fire in 10ms; When block req2 comes,
it also exceed this limits, the block timer is updated to 3ms; Let us
assume that no block request is coming. When the firing time arrives,
req2 will be serviced; but when next enqueued request req1 is got from
block queue, it could still exceed the limits, it will need to be
enqueued. right?

 Rather, if we exceed our limits, we invoke qemu_block_queue_enqueue()
 again, which allocates a whole new request and puts it at the tail.
 I think we want to update the throttling logic in readv/writev to return
 NULL if bs-req_from_queue == true and we exceed the limits.  Then this
No, NULL indicate that the block emulation layer fails to start
readv/writev request.
 logic will do the right thing by inserting the request back to the head.
We've used a request pool, Maybe we can release it to this pool when
the request need to be freed.


 +        }
 +
 +        qemu_free(request);


 See my email to blk-queue.c on how we can eliminate free'ing the request
 here.
After i go to office next week, i will check it.

 +    }
 +}
 +
  void bdrv_register(BlockDriver *bdrv)
  {
      if (!bdrv-bdrv_aio_readv) {
 @@ -642,6 +688,19 @@ int bdrv_open(BlockDriverState *bs, const char 
 *filename, int flags,
              bs-change_cb(bs-change_opaque,

Re: [Qemu-devel] [PATCH v4 2/3] The support for block queue