Application level interface for ARMv8.5-BTI?
This seems like a tricky extension to deploy to the operating system. What is the proposed interface for setting GP on application pages? There are several things that seem plausible to me, and I wondered how far planning has gotten. An mmap/mprotect flag? An ELF program header PT_ARM_BTI (a-la PT_GNU_RELRO) to direct the loader to set said flag when mapping binaries? Or equivalently, a PF_MASKOS bit that could be set on the normal PT_LOAD header. An ELF section flag set by the compiler for sections that use -mbti, which are then collected into the PT_GNU_BTI segment by the linker? That seems like the most plausible way to indicate on a per-binary basis that it has been compiled with the BTI hints in place. But probably there are other ways that make an equal amount of sense. Is there any coordination going on with Intel wrt their similar gadget protection scheme(s)? r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending Dec. 16 2018
QEMU Tooling ([VIRT-252]) = QEMU plugin support ([VIRT-280]) - port my example tools to his Emilio's framework :todo - there is now a {RFC v2 00/38} Plugin support Message-Id: <20181209193749.12277-1-c...@braap.org> to review - tracking regression in [softmmu demacro operation] - again I wish for better objdiffing tools with per-function resolution [VIRT-280] https://projects.linaro.org/browse/VIRT-280 [softmmu demacro operation] https://github.com/stsquad/qemu/tree/ldst/demacrofy-v1 Upstream Work ([VIRT-109]) == - posted {RFC PATCH 00/13} Enabling tcg/tests for xtensa, mips and cris Message-Id: <20181210152829.29271-1-alex.ben...@linaro.org> - posted {PATCH v1 0/2} Fix kvm guest debugging of AA32 guests on AA64 Message-Id: <20181213115503.24188-1-alex.ben...@linaro.org> - prepared {PULL 00/15} Hardfloat + softfloat maintainers update and gitdm Message-Id: <20181214135452.25936-1-alex.ben...@linaro.org> [VIRT-109] https://projects.linaro.org/browse/VIRT-109 Other Tasks === - JIRA Tweaking - created [VIRT-326] to cover maintainer activities - moved [VIRT-65] and [VIRT-109] and created [VIRT-327] (for rth) - promoted [ARMv8.x] to initiative and the .n ticks to Epics - iterated {PATCH v3} contrib: add a basic gitdm config Message-Id: <20181214111032.2084-1-alex.ben...@linaro.org> - maybe as basis for maintainership metrics? - respin {PATCH v3 0/5} support reading some CPUID/CNT registers from user-space Message-Id: <20180625160009.17437-1-alex.ben...@linaro.org> :todo - in branch [https://github.com/stsquad/qemu/tree/misc/cnt-and-misc-reg-fixes-v3] [VIRT-326] https://projects.linaro.org/browse/VIRT-326 [VIRT-65] https://projects.linaro.org/browse/VIRT-65 [VIRT-109] https://projects.linaro.org/browse/VIRT-109 [VIRT-327] https://projects.linaro.org/browse/VIRT-327 [ARMv8.x] https://projects.linaro.org/browse/VIRT-241 Completed Reviews [0/0] === Absences - Christmas Holidays - Connect BKK19 (1-5th April 2019) Current Review Queue * {Qemu-devel} {PATCH v2 00/27} target/arm: Implement ARMv8.3-PAuth Message-Id: <20181214052410.11863-1-richard.hender...@linaro.org> * {PATCH v5 00/73} per-CPU locks Message-Id: <20181213050453.9677-1-c...@braap.org> * {RFC PATCH v3 00/24} KVM: arm64: SVE guest support Message-Id: <1544570941-7377-1-git-send-email-dave.mar...@arm.com> * {RFC v2 00/38} Plugin support Message-Id: <20181209193749.12277-1-c...@braap.org> * {Qemu-devel} {PATCH v8 00/16} gdbstub: support for the multiprocess extension Message-Id: <20181207090135.7651-1-luc.mic...@greensocs.com> * {RFC} arm: Allow system registers for KVM guests to be changed by QEMU code Message-Id: <20181206151401.13455-1-peter.mayd...@linaro.org> -- Alex Bennée ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 16 Dec 2018
Progress: [VIRT-246 # ARMv8.1-LOR Limited Ordering Regions ] Merged to target-arm.next. [VIRT-294 # ARMv8.3-PAuth, Pointer Authentication ] Posted v2. Now booting Will's kernel, which properly detects and enables support. Once that gets to mainline I'll add the prctl to linux-user/. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Started. [VIRT-327 # Richard's upstream QEMU work ] Put the ool softmmu patch set on hold for now, as that is not clearly ready when development opens again. Rebased all of the other queued tcg patch sets around that. Generated pull request. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] report week ending Dec 14
Progress: * VIRT-65 [QEMU upstream maintainership] - QEMU 3.1.0 finally released - sent out a couple of pull requests - some easy patches fixing more clang warnings about taking the address of a member in a packed struct - read through the Memory Tagging extension specification (and a bunch of arm-internal meetings etc this week) thanks -- PMM ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 10 - 14 December 2018
[TCWG-1492] Add timeout and retry to git fetches in Linaro ci infrastructure. [LLVM-505] LLD implement --pic-veneer for AArch32 linux kernel (pr39886) In upstream review [LLVM-509] Add support for v6m range extension thunks to LLD In upstream review pr34928 fixed undefined weak reference handling for AArch64 Spent quite a bit of time revisiting cross-compilation of compiler-rt after helping out on llvm-dev. Posted a review D55709 to improve the documentation. Planned Absences Next 3 weeks on Christmas holiday back Monday 7th January ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 10 - 14 December 2018
== Progress == GlobalISel support for Thumb2: # [LLVM-506] G_LOAD, G_STORE # [LLVM-500] G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR # [LLVM-516] G_SEXT, G_ZEXT, G_ANYEXT, G_TRUNC # G_INTTOPTR, G_PTRTOINT - Committed upstream # [LLVM-518] Support G_CONSTANT for Thumb - Started adding tests == Plan == # [LLVM-518] Support G_CONSTANT for Thumb ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 10-14 December 2018
== Progress == * FDPIC - (GNU-499) GCC: wait for feedback on v4 patches - (GNU-411) GDB: will try to keep as much as possible in common with frv * GCC upstream validation: - reported a few regressions, helped testing some patches - dealing with some random results, still - qemu-3.1.0-rc3, memory consumption: no time to really look at the problem. Unable to match time's figures with LSF's * GCC: - (GNU-99) rebased ubsan / bare-metal patches. Trying to build an LLVM toolchain to see how to properly apply my patches: still trying, thanks to Peter Smith for the support! * misc (conf-calls, meetings, emails, ) - reviewing/submitted infra script patches - ran Spec2006 on aarch32 using gcc-8.2 sysroot, on cortex-a57, results match the previous ones, so the improvements are only imputable to the compiler. 1 regression on gobmk (created GNU-596 to look at this) - dealing with nasty ST-internal infrastructure problems - (GNU-141) noinit/persistent attributes: they are already supported by GCC for TI msp430. The patches are small, plus one libgloss patch. - (GNU-592): started improving benchmarking scripts == Next == FDPIC: - GCC: handle feedback on v4 patches - GDB: update patches - uclibc-ng: look at how to test fdpic mode with openadk Validation: - isolate if/why qemu-3.1.0-rc3 consumes more memory than 2.11 for aarch64-linux target Misc: GNU-592 ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain