Re: [PATCH] EDAC, mpc85xx: Fix PCIe error capture
On Wed, Aug 17, 2016 at 10:44:56AM +0200, Johannes Thumshirn wrote: > On Mon, Aug 15, 2016 at 09:08:49PM +0200, Tillmann Heidsieck wrote: > > According to the reference manual of MPC8572 and T4240, bit 31 of > > PEX_ERR_CAP_STAT is W1C (write 1 to clear). > > This patch adds the corresponding write to PEX_ERR_CAP_STAT in order to > > fix the PCIe error capture. > > > > Tested on a T4240 processor. > > > > Signed-off-by: Tillmann Heidsieck> > --- > > drivers/edac/mpc85xx_edac.c | 12 +--- > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > > Acked-by: Johannes Thumshirn Applied, thanks. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. --
Re: [PATCH] EDAC, mpc85xx: Fix PCIe error capture
On Wed, Aug 17, 2016 at 10:44:56AM +0200, Johannes Thumshirn wrote: > On Mon, Aug 15, 2016 at 09:08:49PM +0200, Tillmann Heidsieck wrote: > > According to the reference manual of MPC8572 and T4240, bit 31 of > > PEX_ERR_CAP_STAT is W1C (write 1 to clear). > > This patch adds the corresponding write to PEX_ERR_CAP_STAT in order to > > fix the PCIe error capture. > > > > Tested on a T4240 processor. > > > > Signed-off-by: Tillmann Heidsieck > > --- > > drivers/edac/mpc85xx_edac.c | 12 +--- > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > > Acked-by: Johannes Thumshirn Applied, thanks. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. --
Re: [PATCH] EDAC, mpc85xx: Fix PCIe error capture
On Mon, Aug 15, 2016 at 09:08:49PM +0200, Tillmann Heidsieck wrote: > According to the reference manual of MPC8572 and T4240, bit 31 of > PEX_ERR_CAP_STAT is W1C (write 1 to clear). > This patch adds the corresponding write to PEX_ERR_CAP_STAT in order to > fix the PCIe error capture. > > Tested on a T4240 processor. > > Signed-off-by: Tillmann Heidsieck> --- > drivers/edac/mpc85xx_edac.c | 12 +--- > 1 file changed, 9 insertions(+), 3 deletions(-) > Acked-by: Johannes Thumshirn -- Johannes Thumshirn Storage jthumsh...@suse.de+49 911 74053 689 SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) Key fingerprint = EC38 9CAB C2C4 F25D 8600 D0D0 0393 969D 2D76 0850
Re: [PATCH] EDAC, mpc85xx: Fix PCIe error capture
On Mon, Aug 15, 2016 at 09:08:49PM +0200, Tillmann Heidsieck wrote: > According to the reference manual of MPC8572 and T4240, bit 31 of > PEX_ERR_CAP_STAT is W1C (write 1 to clear). > This patch adds the corresponding write to PEX_ERR_CAP_STAT in order to > fix the PCIe error capture. > > Tested on a T4240 processor. > > Signed-off-by: Tillmann Heidsieck > --- > drivers/edac/mpc85xx_edac.c | 12 +--- > 1 file changed, 9 insertions(+), 3 deletions(-) > Acked-by: Johannes Thumshirn -- Johannes Thumshirn Storage jthumsh...@suse.de+49 911 74053 689 SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg) Key fingerprint = EC38 9CAB C2C4 F25D 8600 D0D0 0393 969D 2D76 0850
[PATCH] EDAC, mpc85xx: Fix PCIe error capture
According to the reference manual of MPC8572 and T4240, bit 31 of PEX_ERR_CAP_STAT is W1C (write 1 to clear). This patch adds the corresponding write to PEX_ERR_CAP_STAT in order to fix the PCIe error capture. Tested on a T4240 processor. Signed-off-by: Tillmann Heidsieck--- drivers/edac/mpc85xx_edac.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c index ca63d0da8889..f5283f5c07cb 100644 --- a/drivers/edac/mpc85xx_edac.c +++ b/drivers/edac/mpc85xx_edac.c @@ -187,14 +187,14 @@ static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci) { struct mpc85xx_pci_pdata *pdata = pci->pvt_info; - u32 err_detect; + u32 err_detect, err_cap_stat; err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); + err_cap_stat = in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR); pr_err("PCIe error(s) detected\n"); pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect); - pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", - in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR)); + pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", err_cap_stat); pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n", in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0)); pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n", @@ -206,6 +206,9 @@ static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci) /* clear error bits */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); + + /* reset error capture */ + out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, err_cap_stat | 0x1); } static int mpc85xx_pcie_find_capability(struct device_node *np) @@ -344,6 +347,9 @@ static int mpc85xx_pci_err_probe(struct platform_device *op) /* clear error bits */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); + /* reset error capture */ + out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, 0x1); + if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { edac_dbg(3, "failed edac_pci_add_device()\n"); goto err; -- 2.9.3
[PATCH] EDAC, mpc85xx: Fix PCIe error capture
According to the reference manual of MPC8572 and T4240, bit 31 of PEX_ERR_CAP_STAT is W1C (write 1 to clear). This patch adds the corresponding write to PEX_ERR_CAP_STAT in order to fix the PCIe error capture. Tested on a T4240 processor. Signed-off-by: Tillmann Heidsieck --- drivers/edac/mpc85xx_edac.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c index ca63d0da8889..f5283f5c07cb 100644 --- a/drivers/edac/mpc85xx_edac.c +++ b/drivers/edac/mpc85xx_edac.c @@ -187,14 +187,14 @@ static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci) { struct mpc85xx_pci_pdata *pdata = pci->pvt_info; - u32 err_detect; + u32 err_detect, err_cap_stat; err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); + err_cap_stat = in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR); pr_err("PCIe error(s) detected\n"); pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect); - pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", - in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR)); + pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", err_cap_stat); pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n", in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0)); pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n", @@ -206,6 +206,9 @@ static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci) /* clear error bits */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); + + /* reset error capture */ + out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, err_cap_stat | 0x1); } static int mpc85xx_pcie_find_capability(struct device_node *np) @@ -344,6 +347,9 @@ static int mpc85xx_pci_err_probe(struct platform_device *op) /* clear error bits */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); + /* reset error capture */ + out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, 0x1); + if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { edac_dbg(3, "failed edac_pci_add_device()\n"); goto err; -- 2.9.3