Re: [PATCH 6/10] clk: sunxi-ng: Add A10s CCU driver
On Sun, Nov 13, 2016 at 05:34:44PM +0800, Chen-Yu Tsai wrote: > > +static struct ccu_nkmp pll_ve_clk = { > > + .enable = BIT(31), > > + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0), > > + .k = _SUNXI_CCU_MULT(4, 2), > > + .m = _SUNXI_CCU_DIV(0, 2), > > + .p = _SUNXI_CCU_DIV(16, 2), > > Any chance we'll support the bypass switch on this one? I'm not sure this will be useful to have it running at 24MHz. > > +static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2, 0); > > Maybe we should set CLK_IS_CRITICAL on this one as well... in case the > bootloader uses pll-periph for mbus, and none of the dram gates are enabled. Ack. > > +static SUNXI_CCU_GATE(hosc_clk,"hosc", "osc24M", 0x050, BIT(0), 0); > > Why the extra "hosc" clock here? You should probably just internalize > "osc24M". I'd prefer to model it as it is modelled in hardware: you have two crystals, and then a gate within the CCU. > > +static const char * const csi_parents[] = { "hosc", "pll-video0", > > "pll-video1", > > + "pll-video0-2x", > > "pll-video1-2x" }; > > +static const u8 csi_table[] = { 0, 1, 2, 5, 6 }; > > +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", > > + csi_parents, csi_table, > > + 0x134, 0, 5, 24, 2, BIT(31), 0); > > Do you know if CSI needs to change the module clock? Apparently not. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature
Re: [PATCH 6/10] clk: sunxi-ng: Add A10s CCU driver
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard wrote: > Signed-off-by: Maxime Ripard > --- > drivers/clk/sunxi-ng/Kconfig | 10 +- > drivers/clk/sunxi-ng/Makefile | 1 +- > drivers/clk/sunxi-ng/ccu-sun5i-a10s.c | 755 +++- > drivers/clk/sunxi-ng/ccu-sun5i.h | 129 +- > 4 files changed, 895 insertions(+), 0 deletions(-) > create mode 100644 drivers/clk/sunxi-ng/ccu-sun5i-a10s.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun5i.h > > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig > index 8454c6e3dd65..e2becd36a1f9 100644 > --- a/drivers/clk/sunxi-ng/Kconfig > +++ b/drivers/clk/sunxi-ng/Kconfig > @@ -64,6 +64,16 @@ config SUN50I_A64_CCU > select SUNXI_CCU_PHASE > default ARM64 && ARCH_SUNXI > > +config SUN5I_A10S_CCU > + bool "Support for the Allwinner A10s CCM" > + select SUNXI_CCU_DIV > + select SUNXI_CCU_NK > + select SUNXI_CCU_NKM > + select SUNXI_CCU_NM > + select SUNXI_CCU_MP > + select SUNXI_CCU_PHASE > + default MACH_SUN5I > + > config SUN6I_A31_CCU > bool "Support for the Allwinner A31/A31s CCU" > select SUNXI_CCU_DIV > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > index 24fbc6e5deb8..79e9a166dc83 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -19,6 +19,7 @@ obj-$(CONFIG_SUNXI_CCU_MP)+= ccu_mp.o > > # SoC support > obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o > +obj-$(CONFIG_SUN5I_A10S_CCU) += ccu-sun5i-a10s.o > obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o > obj-$(CONFIG_SUN8I_A23_CCU)+= ccu-sun8i-a23.o > obj-$(CONFIG_SUN8I_A33_CCU)+= ccu-sun8i-a33.o > diff --git a/drivers/clk/sunxi-ng/ccu-sun5i-a10s.c > b/drivers/clk/sunxi-ng/ccu-sun5i-a10s.c > new file mode 100644 > index ..94d9a5cbf60b > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun5i-a10s.c > @@ -0,0 +1,755 @@ > +/* > + * Copyright (c) 2016 Maxime Ripard. All rights reserved. > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include > +#include > + > +#include "ccu_common.h" > +#include "ccu_reset.h" > + > +#include "ccu_div.h" > +#include "ccu_gate.h" > +#include "ccu_mp.h" > +#include "ccu_mult.h" > +#include "ccu_nk.h" > +#include "ccu_nkm.h" > +#include "ccu_nkmp.h" > +#include "ccu_nm.h" > +#include "ccu_phase.h" > + > +#include "ccu-sun5i.h" > + > +static struct ccu_nkmp pll_core_clk = { > + .enable = BIT(31), > + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0), > + .k = _SUNXI_CCU_MULT(4, 2), > + .m = _SUNXI_CCU_DIV(0, 2), > + .p = _SUNXI_CCU_DIV(16, 2), > + .common = { > + .reg= 0x000, > + .hw.init= CLK_HW_INIT("pll-core", > + "hosc", > + &ccu_nkmp_ops, > + 0), > + }, > +}; > + > +/* > + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from > + * the base (2x, 4x and 8x), and one variable divider (the one true > + * pll audio). > + * > + * We don't have any need for the variable divider for now, so we just > + * hardcode it to match with the clock names > + */ > +#define SUN5I_PLL_AUDIO_REG0x008 > + > +static struct ccu_nm pll_audio_base_clk = { > + .enable = BIT(31), > + .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0), > + .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0), Nit: a note explaining that the datasheet is wrong would be nice. > + .common = { > + .reg= 0x008, > + .hw.init= CLK_HW_INIT("pll-audio-base", > + "hosc", > + &ccu_nm_ops, > + 0), > + }, > +}; > + > +static struct ccu_mult pll_video0_clk = { > + .enable = BIT(31), > + .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127), > + .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14), > + 27000, 29700), > + .common = { > + .reg= 0x010, > + .features = CCU_FEATURE_FRACTIONAL, > + .hw.init= CLK_HW_INIT("pll-video0", > + "osc3M", >
[PATCH 6/10] clk: sunxi-ng: Add A10s CCU driver
Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/Kconfig | 10 +- drivers/clk/sunxi-ng/Makefile | 1 +- drivers/clk/sunxi-ng/ccu-sun5i-a10s.c | 755 +++- drivers/clk/sunxi-ng/ccu-sun5i.h | 129 +- 4 files changed, 895 insertions(+), 0 deletions(-) create mode 100644 drivers/clk/sunxi-ng/ccu-sun5i-a10s.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun5i.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 8454c6e3dd65..e2becd36a1f9 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -64,6 +64,16 @@ config SUN50I_A64_CCU select SUNXI_CCU_PHASE default ARM64 && ARCH_SUNXI +config SUN5I_A10S_CCU + bool "Support for the Allwinner A10s CCM" + select SUNXI_CCU_DIV + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NM + select SUNXI_CCU_MP + select SUNXI_CCU_PHASE + default MACH_SUN5I + config SUN6I_A31_CCU bool "Support for the Allwinner A31/A31s CCU" select SUNXI_CCU_DIV diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 24fbc6e5deb8..79e9a166dc83 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_SUNXI_CCU_MP)+= ccu_mp.o # SoC support obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o +obj-$(CONFIG_SUN5I_A10S_CCU) += ccu-sun5i-a10s.o obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o obj-$(CONFIG_SUN8I_A23_CCU)+= ccu-sun8i-a23.o obj-$(CONFIG_SUN8I_A33_CCU)+= ccu-sun8i-a33.o diff --git a/drivers/clk/sunxi-ng/ccu-sun5i-a10s.c b/drivers/clk/sunxi-ng/ccu-sun5i-a10s.c new file mode 100644 index ..94d9a5cbf60b --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun5i-a10s.c @@ -0,0 +1,755 @@ +/* + * Copyright (c) 2016 Maxime Ripard. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun5i.h" + +static struct ccu_nkmp pll_core_clk = { + .enable = BIT(31), + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0), + .k = _SUNXI_CCU_MULT(4, 2), + .m = _SUNXI_CCU_DIV(0, 2), + .p = _SUNXI_CCU_DIV(16, 2), + .common = { + .reg= 0x000, + .hw.init= CLK_HW_INIT("pll-core", + "hosc", + &ccu_nkmp_ops, + 0), + }, +}; + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN5I_PLL_AUDIO_REG0x008 + +static struct ccu_nm pll_audio_base_clk = { + .enable = BIT(31), + .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0), + .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0), + .common = { + .reg= 0x008, + .hw.init= CLK_HW_INIT("pll-audio-base", + "hosc", + &ccu_nm_ops, + 0), + }, +}; + +static struct ccu_mult pll_video0_clk = { + .enable = BIT(31), + .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127), + .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14), + 27000, 29700), + .common = { + .reg= 0x010, + .features = CCU_FEATURE_FRACTIONAL, + .hw.init= CLK_HW_INIT("pll-video0", + "osc3M", + &ccu_mult_ops, + 0), + }, +}; + +static struct ccu_nkmp pll_ve_clk = { + .enable = BIT(31), + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0), + .k = _SUNXI_CCU_MULT(4, 2), + .m = _SUNXI_CCU_DIV(0, 2), + .p