Re: [PATCH] ppc32: refactor FPU exception handling
Ben, Sorry about that, we have had some back and forth on this on the ppc embedded list. Not sure I understand your concern about the duplication of the fast exception return path? Jason's patch pretty much just moved code out of head.S into fpu.S so we dont duplicate it between head.S and head_44x.S & head_fsl_booke.S - kumar On Apr 11, 2005, at 9:28 PM, Benjamin Herrenschmidt wrote: On Mon, 2005-04-11 at 17:02 -0500, Kumar Gala wrote: > Andrew, > > Moved common FPU exception handling code out of head.S so it can be used > by several of the sub-architectures that might of a full PowerPC FPU. > > Also, uses new CONFIG_PPC_FPU define to fix alignment exception > handling for floating point load/store instructions to only occur if we > have a hardware FPU. > > Signed-off-by: Jason McMullan <[EMAIL PROTECTED]> > Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> Andrew, please hold on this patch, it hasn't been properly discussed with the relevant maintainer, that is Paul Mackerras. I can see matter for debate in there, like the whole duplication of the fast exception return path... It's also touching quite sensitive bits of kernel code (head.S) that needs careful auditing and testing before beeing pushed upstream. Ben. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ppc32: refactor FPU exception handling
On Mon, 2005-04-11 at 17:02 -0500, Kumar Gala wrote: > Andrew, > > Moved common FPU exception handling code out of head.S so it can be used > by several of the sub-architectures that might of a full PowerPC FPU. > > Also, uses new CONFIG_PPC_FPU define to fix alignment exception > handling for floating point load/store instructions to only occur if we > have a hardware FPU. > > Signed-off-by: Jason McMullan <[EMAIL PROTECTED]> > Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> Andrew, please hold on this patch, it hasn't been properly discussed with the relevant maintainer, that is Paul Mackerras. I can see matter for debate in there, like the whole duplication of the fast exception return path... It's also touching quite sensitive bits of kernel code (head.S) that needs careful auditing and testing before beeing pushed upstream. Ben. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ppc32: refactor FPU exception handling
Andrew, Moved common FPU exception handling code out of head.S so it can be used by several of the sub-architectures that might of a full PowerPC FPU. Also, uses new CONFIG_PPC_FPU define to fix alignment exception handling for floating point load/store instructions to only occur if we have a hardware FPU. Signed-off-by: Jason McMullan <[EMAIL PROTECTED]> Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> --- diff -Nru a/arch/ppc/Kconfig b/arch/ppc/Kconfig --- a/arch/ppc/Kconfig 2005-04-11 17:00:36 -05:00 +++ b/arch/ppc/Kconfig 2005-04-11 17:00:36 -05:00 @@ -53,6 +53,7 @@ config 6xx bool "6xx/7xx/74xx/52xx/82xx/83xx" + select PPC_FPU help There are four types of PowerPC chips supported. The more common types (601, 603, 604, 740, 750, 7400), the Motorola embedded @@ -85,6 +86,9 @@ bool "e500" endchoice + +config PPC_FPU + bool config BOOKE bool diff -Nru a/arch/ppc/Makefile b/arch/ppc/Makefile --- a/arch/ppc/Makefile 2005-04-11 17:00:36 -05:00 +++ b/arch/ppc/Makefile 2005-04-11 17:00:36 -05:00 @@ -53,6 +53,7 @@ head-$(CONFIG_6xx) += arch/ppc/kernel/idle_6xx.o head-$(CONFIG_POWER4) += arch/ppc/kernel/idle_power4.o +head-$(CONFIG_PPC_FPU) += arch/ppc/kernel/fpu.o core-y += arch/ppc/kernel/ arch/ppc/platforms/ \ arch/ppc/mm/ arch/ppc/lib/ arch/ppc/syslib/ diff -Nru a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile --- a/arch/ppc/kernel/Makefile 2005-04-11 17:00:36 -05:00 +++ b/arch/ppc/kernel/Makefile 2005-04-11 17:00:36 -05:00 @@ -9,6 +9,7 @@ extra-$(CONFIG_8xx):= head_8xx.o extra-$(CONFIG_6xx)+= idle_6xx.o extra-$(CONFIG_POWER4) += idle_power4.o +extra-$(CONFIG_PPC_FPU)+= fpu.o extra-y+= vmlinux.lds obj-y := entry.o traps.o irq.o idle.o time.o misc.o \ diff -Nru a/arch/ppc/kernel/align.c b/arch/ppc/kernel/align.c --- a/arch/ppc/kernel/align.c 2005-04-11 17:00:36 -05:00 +++ b/arch/ppc/kernel/align.c 2005-04-11 17:00:36 -05:00 @@ -368,16 +368,24 @@ /* Single-precision FP load and store require conversions... */ case LD+F+S: +#ifdef CONFIG_PPC_FPU preempt_disable(); enable_kernel_fp(); cvt_fd(, , >thread.fpscr); preempt_enable(); +#else + return 0; +#endif break; case ST+F+S: +#ifdef CONFIG_PPC_FPU preempt_disable(); enable_kernel_fp(); cvt_df(, , >thread.fpscr); preempt_enable(); +#else + return 0; +#endif break; } diff -Nru a/arch/ppc/kernel/fpu.S b/arch/ppc/kernel/fpu.S --- /dev/null Wed Dec 31 16:00:00 196900 +++ b/arch/ppc/kernel/fpu.S 2005-04-11 17:00:36 -05:00 @@ -0,0 +1,190 @@ +/* + * FPU support code, moved here from head.S so that it can be used + * by chips which use other head-whatever.S files. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * This task wants to use the FPU now. + * On UP, disable FP for the task which had the FPU previously, + * and save its floating-point registers in its thread_struct. + * Load up this task's FP registers from its thread_struct, + * enable the FPU for the current task and return to the task. + */ + .globl load_up_fpu +load_up_fpu: + mfmsr r5 + ori r5,r5,MSR_FP +#ifdef CONFIG_PPC64BRIDGE + clrldi r5,r5,1 /* turn off 64-bit mode */ +#endif /* CONFIG_PPC64BRIDGE */ + SYNC + MTMSRD(r5) /* enable use of fpu now */ + isync +/* + * For SMP, we don't do lazy FPU switching because it just gets too + * horrendously complex, especially when a task switches from one CPU + * to another. Instead we call giveup_fpu in switch_to. + */ +#ifndef CONFIG_SMP + tophys(r6,0)/* get __pa constant */ + addis r3,r6,[EMAIL PROTECTED] + lwz r4,[EMAIL PROTECTED](r3) + cmpwi 0,r4,0 + beq 1f + add r4,r4,r6 + addir4,r4,THREAD/* want last_task_used_math->thread */ + SAVE_32FPRS(0, r4) + mffsfr0 + stfdfr0,THREAD_FPSCR-4(r4) + lwz r5,PT_REGS(r4) + add r5,r5,r6 + lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) + li r10,MSR_FP|MSR_FE0|MSR_FE1 + andcr4,r4,r10 /* disable FP for previous task */ + stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#endif /* CONFIG_SMP */ + /*
[PATCH] ppc32: refactor FPU exception handling
Andrew, Moved common FPU exception handling code out of head.S so it can be used by several of the sub-architectures that might of a full PowerPC FPU. Also, uses new CONFIG_PPC_FPU define to fix alignment exception handling for floating point load/store instructions to only occur if we have a hardware FPU. Signed-off-by: Jason McMullan [EMAIL PROTECTED] Signed-off-by: Kumar Gala [EMAIL PROTECTED] --- diff -Nru a/arch/ppc/Kconfig b/arch/ppc/Kconfig --- a/arch/ppc/Kconfig 2005-04-11 17:00:36 -05:00 +++ b/arch/ppc/Kconfig 2005-04-11 17:00:36 -05:00 @@ -53,6 +53,7 @@ config 6xx bool 6xx/7xx/74xx/52xx/82xx/83xx + select PPC_FPU help There are four types of PowerPC chips supported. The more common types (601, 603, 604, 740, 750, 7400), the Motorola embedded @@ -85,6 +86,9 @@ bool e500 endchoice + +config PPC_FPU + bool config BOOKE bool diff -Nru a/arch/ppc/Makefile b/arch/ppc/Makefile --- a/arch/ppc/Makefile 2005-04-11 17:00:36 -05:00 +++ b/arch/ppc/Makefile 2005-04-11 17:00:36 -05:00 @@ -53,6 +53,7 @@ head-$(CONFIG_6xx) += arch/ppc/kernel/idle_6xx.o head-$(CONFIG_POWER4) += arch/ppc/kernel/idle_power4.o +head-$(CONFIG_PPC_FPU) += arch/ppc/kernel/fpu.o core-y += arch/ppc/kernel/ arch/ppc/platforms/ \ arch/ppc/mm/ arch/ppc/lib/ arch/ppc/syslib/ diff -Nru a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile --- a/arch/ppc/kernel/Makefile 2005-04-11 17:00:36 -05:00 +++ b/arch/ppc/kernel/Makefile 2005-04-11 17:00:36 -05:00 @@ -9,6 +9,7 @@ extra-$(CONFIG_8xx):= head_8xx.o extra-$(CONFIG_6xx)+= idle_6xx.o extra-$(CONFIG_POWER4) += idle_power4.o +extra-$(CONFIG_PPC_FPU)+= fpu.o extra-y+= vmlinux.lds obj-y := entry.o traps.o irq.o idle.o time.o misc.o \ diff -Nru a/arch/ppc/kernel/align.c b/arch/ppc/kernel/align.c --- a/arch/ppc/kernel/align.c 2005-04-11 17:00:36 -05:00 +++ b/arch/ppc/kernel/align.c 2005-04-11 17:00:36 -05:00 @@ -368,16 +368,24 @@ /* Single-precision FP load and store require conversions... */ case LD+F+S: +#ifdef CONFIG_PPC_FPU preempt_disable(); enable_kernel_fp(); cvt_fd(data.f, data.d, current-thread.fpscr); preempt_enable(); +#else + return 0; +#endif break; case ST+F+S: +#ifdef CONFIG_PPC_FPU preempt_disable(); enable_kernel_fp(); cvt_df(data.d, data.f, current-thread.fpscr); preempt_enable(); +#else + return 0; +#endif break; } diff -Nru a/arch/ppc/kernel/fpu.S b/arch/ppc/kernel/fpu.S --- /dev/null Wed Dec 31 16:00:00 196900 +++ b/arch/ppc/kernel/fpu.S 2005-04-11 17:00:36 -05:00 @@ -0,0 +1,190 @@ +/* + * FPU support code, moved here from head.S so that it can be used + * by chips which use other head-whatever.S files. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include linux/config.h +#include asm/processor.h +#include asm/page.h +#include asm/mmu.h +#include asm/pgtable.h +#include asm/cputable.h +#include asm/cache.h +#include asm/thread_info.h +#include asm/ppc_asm.h +#include asm/offsets.h + +/* + * This task wants to use the FPU now. + * On UP, disable FP for the task which had the FPU previously, + * and save its floating-point registers in its thread_struct. + * Load up this task's FP registers from its thread_struct, + * enable the FPU for the current task and return to the task. + */ + .globl load_up_fpu +load_up_fpu: + mfmsr r5 + ori r5,r5,MSR_FP +#ifdef CONFIG_PPC64BRIDGE + clrldi r5,r5,1 /* turn off 64-bit mode */ +#endif /* CONFIG_PPC64BRIDGE */ + SYNC + MTMSRD(r5) /* enable use of fpu now */ + isync +/* + * For SMP, we don't do lazy FPU switching because it just gets too + * horrendously complex, especially when a task switches from one CPU + * to another. Instead we call giveup_fpu in switch_to. + */ +#ifndef CONFIG_SMP + tophys(r6,0)/* get __pa constant */ + addis r3,r6,[EMAIL PROTECTED] + lwz r4,[EMAIL PROTECTED](r3) + cmpwi 0,r4,0 + beq 1f + add r4,r4,r6 + addir4,r4,THREAD/* want last_task_used_math-thread */ + SAVE_32FPRS(0, r4) + mffsfr0 + stfdfr0,THREAD_FPSCR-4(r4) + lwz r5,PT_REGS(r4) + add r5,r5,r6 + lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) + li r10,MSR_FP|MSR_FE0|MSR_FE1 +
Re: [PATCH] ppc32: refactor FPU exception handling
On Mon, 2005-04-11 at 17:02 -0500, Kumar Gala wrote: Andrew, Moved common FPU exception handling code out of head.S so it can be used by several of the sub-architectures that might of a full PowerPC FPU. Also, uses new CONFIG_PPC_FPU define to fix alignment exception handling for floating point load/store instructions to only occur if we have a hardware FPU. Signed-off-by: Jason McMullan [EMAIL PROTECTED] Signed-off-by: Kumar Gala [EMAIL PROTECTED] Andrew, please hold on this patch, it hasn't been properly discussed with the relevant maintainer, that is Paul Mackerras. I can see matter for debate in there, like the whole duplication of the fast exception return path... It's also touching quite sensitive bits of kernel code (head.S) that needs careful auditing and testing before beeing pushed upstream. Ben. - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ppc32: refactor FPU exception handling
Ben, Sorry about that, we have had some back and forth on this on the ppc embedded list. Not sure I understand your concern about the duplication of the fast exception return path? Jason's patch pretty much just moved code out of head.S into fpu.S so we dont duplicate it between head.S and head_44x.S head_fsl_booke.S - kumar On Apr 11, 2005, at 9:28 PM, Benjamin Herrenschmidt wrote: On Mon, 2005-04-11 at 17:02 -0500, Kumar Gala wrote: Andrew, Moved common FPU exception handling code out of head.S so it can be used by several of the sub-architectures that might of a full PowerPC FPU. Also, uses new CONFIG_PPC_FPU define to fix alignment exception handling for floating point load/store instructions to only occur if we have a hardware FPU. Signed-off-by: Jason McMullan [EMAIL PROTECTED] Signed-off-by: Kumar Gala [EMAIL PROTECTED] Andrew, please hold on this patch, it hasn't been properly discussed with the relevant maintainer, that is Paul Mackerras. I can see matter for debate in there, like the whole duplication of the fast exception return path... It's also touching quite sensitive bits of kernel code (head.S) that needs careful auditing and testing before beeing pushed upstream. Ben. - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
