[PATCH 4.14 132/146] ARM: dts: rockchip: Remove @0 from the veyron memory node
4.14-stable review patch. If anyone has any objections, please let me know.
--
From: Heiko Stuebner
commit 672e60b72bbe7aace88721db55b380b6a51fb8f9 upstream.
The Coreboot version on veyron ChromeOS devices seems to ignore
memory@0 nodes when updating the available memory and instead
inserts another memory node without the address.
This leads to 4GB systems only ever be using 2GB as the memory@0
node takes precedence. So remove the @0 for veyron devices.
Fixes: 0b639b815f15 ("ARM: dts: rockchip: Add missing unit name to memory nodes
in rk3288 boards")
Cc: sta...@vger.kernel.org
Reported-by: Heikki Lindholm
Signed-off-by: Heiko Stuebner
Signed-off-by: Greg Kroah-Hartman
---
arch/arm/boot/dts/rk3288-veyron.dtsi |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -47,7 +47,11 @@
#include "rk3288.dtsi"
/ {
- memory@0 {
+ /*
+* The default coreboot on veyron devices ignores memory@0 nodes
+* and would instead create another memory node.
+*/
+ memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x8000>;
};
[PATCH 4.14 132/146] ARM: dts: rockchip: Remove @0 from the veyron memory node
4.14-stable review patch. If anyone has any objections, please let me know.
--
From: Heiko Stuebner
commit 672e60b72bbe7aace88721db55b380b6a51fb8f9 upstream.
The Coreboot version on veyron ChromeOS devices seems to ignore
memory@0 nodes when updating the available memory and instead
inserts another memory node without the address.
This leads to 4GB systems only ever be using 2GB as the memory@0
node takes precedence. So remove the @0 for veyron devices.
Fixes: 0b639b815f15 ("ARM: dts: rockchip: Add missing unit name to memory nodes
in rk3288 boards")
Cc: sta...@vger.kernel.org
Reported-by: Heikki Lindholm
Signed-off-by: Heiko Stuebner
Signed-off-by: Greg Kroah-Hartman
---
arch/arm/boot/dts/rk3288-veyron.dtsi |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -47,7 +47,11 @@
#include "rk3288.dtsi"
/ {
- memory@0 {
+ /*
+* The default coreboot on veyron devices ignores memory@0 nodes
+* and would instead create another memory node.
+*/
+ memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x8000>;
};
