[PATCH 80/83] drm/radeon: Add register access functions to kfd2kgd interface
From: Ben Goz This patch extends the kfd2kgd interface by adding functions that perform direct register access. These functions can be called from kfd and will allow to eliminate all direct register accesses from within the kfd. Signed-off-by: Ben Goz Signed-off-by: Oded Gabbay --- drivers/gpu/drm/radeon/cikd.h | 51 +- drivers/gpu/drm/radeon/radeon_kfd.c | 354 include/linux/radeon_kfd.h | 11 ++ 3 files changed, 415 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index 0c6e1b5..0a2a403 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h @@ -1137,6 +1137,9 @@ #defineSH_MEM_ALIGNMENT_MODE_UNALIGNED 3 #defineDEFAULT_MTYPE(x)((x) << 4) #defineAPE1_MTYPE(x) ((x) << 7) +/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ +#defineMTYPE_CACHED0 +#defineMTYPE_NONCACHED 3 #defineSX_DEBUG_1 0x9060 @@ -1447,6 +1450,16 @@ #define CP_HQD_ACTIVE 0xC91C #define CP_HQD_VMID 0xC920 +#define CP_HQD_PERSISTENT_STATE 0xC924u +#defineDEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8) + +#define CP_HQD_PIPE_PRIORITY 0xC928u +#define CP_HQD_QUEUE_PRIORITY 0xC92Cu +#define CP_HQD_QUANTUM 0xC930u +#defineQUANTUM_EN 1U +#defineQUANTUM_SCALE_1MS (1U << 4) +#defineQUANTUM_DURATION(x) ((x) << 8) + #define CP_HQD_PQ_BASE0xC934 #define CP_HQD_PQ_BASE_HI 0xC938 #define CP_HQD_PQ_RPTR0xC93C @@ -1474,12 +1487,32 @@ #definePRIV_STATE (1 << 30) #defineKMD_QUEUE (1 << 31) -#define CP_HQD_DEQUEUE_REQUEST 0xC974 +#define CP_HQD_IB_BASE_ADDR0xC95Cu +#define CP_HQD_IB_BASE_ADDR_HI 0xC960u +#define CP_HQD_IB_RPTR 0xC964u +#define CP_HQD_IB_CONTROL 0xC968u +#defineIB_ATC_EN (1U << 23) +#defineDEFAULT_MIN_IB_AVAIL_SIZE (3U << 20) + +#define CP_HQD_DEQUEUE_REQUEST 0xC974 +#defineDEQUEUE_REQUEST_DRAIN 1 +#define DEQUEUE_REQUEST_RESET 2 #define CP_MQD_CONTROL 0xC99C #defineMQD_VMID(x) ((x) << 0) #defineMQD_VMID_MASK (0xf << 0) +#define CP_HQD_SEMA_CMD0xC97Cu +#define CP_HQD_MSG_TYPE0xC980u +#define CP_HQD_ATOMIC0_PREOP_LO0xC984u +#define CP_HQD_ATOMIC0_PREOP_HI0xC988u +#define CP_HQD_ATOMIC1_PREOP_LO0xC98Cu +#define CP_HQD_ATOMIC1_PREOP_HI0xC990u +#define CP_HQD_HQ_SCHEDULER0 0xC994u +#define CP_HQD_HQ_SCHEDULER1 0xC998u + +#define SH_STATIC_MEM_CONFIG 0x9604u + #define DB_RENDER_CONTROL 0x28000 #define PA_SC_RASTER_CONFIG 0x28350 @@ -2069,4 +2102,20 @@ #define VCE_CMD_IB_AUTO0x0005 #define VCE_CMD_SEMAPHORE 0x0006 +#define ATC_VMID0_PASID_MAPPING0x339Cu +#defineATC_VMID_PASID_MAPPING_UPDATE_STATUS0x3398u +#defineATC_VMID_PASID_MAPPING_VALID(1U << 31) + +#define ATC_VM_APERTURE0_CNTL 0x3310u +#defineATS_ACCESS_MODE_NEVER 0 +#defineATS_ACCESS_MODE_ALWAYS 1 + +#define ATC_VM_APERTURE0_CNTL2 0x3318u +#define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u +#define ATC_VM_APERTURE0_LOW_ADDR 0x3300u +#define ATC_VM_APERTURE1_CNTL
[PATCH 80/83] drm/radeon: Add register access functions to kfd2kgd interface
From: Ben Goz ben@amd.com This patch extends the kfd2kgd interface by adding functions that perform direct register access. These functions can be called from kfd and will allow to eliminate all direct register accesses from within the kfd. Signed-off-by: Ben Goz ben@amd.com Signed-off-by: Oded Gabbay oded.gab...@amd.com --- drivers/gpu/drm/radeon/cikd.h | 51 +- drivers/gpu/drm/radeon/radeon_kfd.c | 354 include/linux/radeon_kfd.h | 11 ++ 3 files changed, 415 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index 0c6e1b5..0a2a403 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h @@ -1137,6 +1137,9 @@ #defineSH_MEM_ALIGNMENT_MODE_UNALIGNED 3 #defineDEFAULT_MTYPE(x)((x) 4) #defineAPE1_MTYPE(x) ((x) 7) +/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ +#defineMTYPE_CACHED0 +#defineMTYPE_NONCACHED 3 #defineSX_DEBUG_1 0x9060 @@ -1447,6 +1450,16 @@ #define CP_HQD_ACTIVE 0xC91C #define CP_HQD_VMID 0xC920 +#define CP_HQD_PERSISTENT_STATE 0xC924u +#defineDEFAULT_CP_HQD_PERSISTENT_STATE (0x33U 8) + +#define CP_HQD_PIPE_PRIORITY 0xC928u +#define CP_HQD_QUEUE_PRIORITY 0xC92Cu +#define CP_HQD_QUANTUM 0xC930u +#defineQUANTUM_EN 1U +#defineQUANTUM_SCALE_1MS (1U 4) +#defineQUANTUM_DURATION(x) ((x) 8) + #define CP_HQD_PQ_BASE0xC934 #define CP_HQD_PQ_BASE_HI 0xC938 #define CP_HQD_PQ_RPTR0xC93C @@ -1474,12 +1487,32 @@ #definePRIV_STATE (1 30) #defineKMD_QUEUE (1 31) -#define CP_HQD_DEQUEUE_REQUEST 0xC974 +#define CP_HQD_IB_BASE_ADDR0xC95Cu +#define CP_HQD_IB_BASE_ADDR_HI 0xC960u +#define CP_HQD_IB_RPTR 0xC964u +#define CP_HQD_IB_CONTROL 0xC968u +#defineIB_ATC_EN (1U 23) +#defineDEFAULT_MIN_IB_AVAIL_SIZE (3U 20) + +#define CP_HQD_DEQUEUE_REQUEST 0xC974 +#defineDEQUEUE_REQUEST_DRAIN 1 +#define DEQUEUE_REQUEST_RESET 2 #define CP_MQD_CONTROL 0xC99C #defineMQD_VMID(x) ((x) 0) #defineMQD_VMID_MASK (0xf 0) +#define CP_HQD_SEMA_CMD0xC97Cu +#define CP_HQD_MSG_TYPE0xC980u +#define CP_HQD_ATOMIC0_PREOP_LO0xC984u +#define CP_HQD_ATOMIC0_PREOP_HI0xC988u +#define CP_HQD_ATOMIC1_PREOP_LO0xC98Cu +#define CP_HQD_ATOMIC1_PREOP_HI0xC990u +#define CP_HQD_HQ_SCHEDULER0 0xC994u +#define CP_HQD_HQ_SCHEDULER1 0xC998u + +#define SH_STATIC_MEM_CONFIG 0x9604u + #define DB_RENDER_CONTROL 0x28000 #define PA_SC_RASTER_CONFIG 0x28350 @@ -2069,4 +2102,20 @@ #define VCE_CMD_IB_AUTO0x0005 #define VCE_CMD_SEMAPHORE 0x0006 +#define ATC_VMID0_PASID_MAPPING0x339Cu +#defineATC_VMID_PASID_MAPPING_UPDATE_STATUS0x3398u +#defineATC_VMID_PASID_MAPPING_VALID(1U 31) + +#define ATC_VM_APERTURE0_CNTL 0x3310u +#defineATS_ACCESS_MODE_NEVER 0 +#defineATS_ACCESS_MODE_ALWAYS 1 + +#define ATC_VM_APERTURE0_CNTL2 0x3318u +#define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u +#define ATC_VM_APERTURE0_LOW_ADDR 0x3300u +#define
